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University/Government/Industry Microelectronics Symposium, 2006 16th Biennial

Date 25-28 June 2006

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  • [Front cover]

    Publication Year: 2006 , Page(s): C1
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  • Sixteenth Biennial University/Government/Industry Microelectronics Symposium

    Publication Year: 2006 , Page(s): nil1
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  • [Copyright notice]

    Publication Year: 2006 , Page(s): nil2
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  • Welcome to UGIM 2006

    Publication Year: 2006 , Page(s): nil3
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  • Executive Committee

    Publication Year: 2006 , Page(s): nil4
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  • Technical Program Committee

    Publication Year: 2006 , Page(s): nil4
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  • Session

    Publication Year: 2006 , Page(s): nil5 - nil7
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  • Establishing Chip Scale Packaging (CSP) Capabilities at the University of Alaska Fairbanks: Lessons Learned in Tech Transfer, R&D and Sustaining

    Publication Year: 2006 , Page(s): 1 - 5
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    UAF's Office of Electronic Miniaturization (OEM) has successfully transferred technology and established a prototyping chip scale packaging line in Alaska. This was accomplished by carefully managing each operational interface in the academic environment consistent with our mission. Our program offers significant benefits to the University of Alaska system, its academic partners at other universities, governmental agencies that support our activities, the community and its many industrial partners. Chip Scale Packaging is a very successful technology particularly in the consumer electronics sector. It has a proven track record. It has not penetrated as well in high value systems, entrepreneurial technologies, and government sector electronics. Our facility offers an excellent opportunity to apply CSP technologies to many unexplored areas without requiring high volume commitments. OEM is keenly interested in collaborative R&D as well as pilot projects. View full abstract»

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  • Development of a Deep-Submicron CMOS Process for Fabrication of High Performance 0.25 μm Transistors

    Publication Year: 2006 , Page(s): 7 - 11
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    A process for fabrication of 0.25 mum CMOS transistors has been demonstrated. NMOS transistors with drain current of 177 muA/mum at VG=VD=2.5 V and a PMOS transistors with drain current of 131 muA/mum at VG=VD=-2.5 V are reported. The threshold voltages are 1.0 V for the NMOS and -0.735 V for the PMOS transistors. The mask defined gate lengths are 0.5 mum and 0.6 mum for the NMOS and PMOS, respectively. Through a photoresist trimming process, the poly gate lengths are 0.25 mum and 0.35 mum or smaller. Electrical extraction of the gate lengths should yield effective gate lengths of 0.25 mum or smaller. These are the smallest transistors ever fabricated in the SMFL at RIT. Large off-state leakage is reported for the NMOS due to drain leakage induced by implant damage or aggressive titanium silicide formation. A better understanding of this leakage is being investigated and process recommendations given. View full abstract»

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  • RIT MEMS Fabrication Course; University Government Industry Microelectronics Symposium

    Publication Year: 2006 , Page(s): 13 - 17
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    This paper describes a simple, reliable; bulk micro- machined, micro-electro-mechanical system (MEMS) process flow for the fabrication of a wide variety of devices which has been implemented within the Microelectronic Engineering Department at the Rochester Institute of Technology. The fabrication and testing results for thermopiles, pressure sensors, micro-speakers, micro- pumps, accelerometers and inductors in a ten week fabrication course are reported. View full abstract»

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  • Building the New Berkeley Microlab

    Publication Year: 2006 , Page(s): 19 - 21
    Cited by:  Papers (1)
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    The University of California at Berkeley is proceeding with construction of a new nanofabrication laboratory - the CITRIS Nanolab. This new facility is a key component of the College of Engineering's CITRIS research center - the Center for Information Technology Research in the Interest of Society. The new lab will enable world class faculty research and stimulate creative partnerships with industry to address nanoscale CMOS electronics, nanoelectromechanical systems (NEMS), integration of opto and bioelectronics, and nano/micro/macro interface technologies. This laboratory will be the successor to The Berkeley Microlab and will continue and expand the Microlab tradition of a professionally managed, shared laboratory resource open to all academic researchers and supported on a recharge basis to insure the lowest possible barrier to entry. This presentation will provide an overview of the design and planning process with specific commentary on some of the challenges unique to the academic laboratory. Sample questions that will be addressed are as follows. How do you define facility and utility needs when future research requests are unknown? How do you efficiently translate the extensive industry experience of design consultants to a university situation? Is it possible to communicate directly with the architect and design team when working within the procedural confines of a large state university? Construction budget versus fit-up budget - are there strategies to take advantage of the Capital Projects process? Value engineering - does it provide either? And finally, is it possible to build a research laboratory this decade without including the word nano in the facility name? View full abstract»

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  • 25 Years of Microelectronic Engineering Education

    Publication Year: 2006 , Page(s): 23 - 31
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5511 KB) |  | HTML iconHTML  

    Rochester Institute of Technology started the nation's first Bachelor of Science program in Microelectronic Engineering in 1982. The program has kept pace with the rapid advancements in semiconductor technology, sharing 25 of the 40 years characterized by Moore's Law. The program has constantly advanced its integrated circuit fabrication laboratory in order to graduate students with state-of-the-art knowledge, who become immediate and efficient contributors to their company or graduate program. Today, this facility serves as a key resource for research in semiconductor devices, processes, MEMS, nanotechnology, and microsystems. This has led to the creation of the first PhD program in engineering at RIT, a Doctorate in Microsystems Engineering. The department enjoys strong support from the semiconductor industry through its industrial affiliate program. Recently the department received a $1 million department level reform grant to address the imminent need for a highly educated workforce for the US high tech industry that is on the verge of nanotechnology revolution. View full abstract»

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  • RF Physical Device Simulation for Wireless Applications

    Publication Year: 2006 , Page(s): 33 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (838 KB) |  | HTML iconHTML  

    In the RF TCAD community routine large signal RF TCAD simulation has been a goal for some time. Several methods of doing large signal simulation from TCAD are discussed and compared. An example is shown from one approach based on extraction of compact models from TCAD data. This method has several advantages not the least of which is allowing the full capability of the circuit simulator to be used. View full abstract»

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  • Three-dimensional TCAD Process and Device Simulations

    Publication Year: 2006 , Page(s): 41 - 46
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    Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process. View full abstract»

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  • Investigation of the Performance Limits of III-V Double-Gate n-MOSFETs

    Publication Year: 2006 , Page(s): 47 - 50
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    The performance limits of ultra-thin body double-gated (DG) III-V channel MOSFETs are presented in this paper. An analytical ballistic model including all the valleys (Gamma-, X- and L-), was used to simulate the source to drain current. The band-to-band tunneling (BTBT) limited off currents, including both the direct and the indirect components, were simulated using TAURUSTM. Our results show that at significantly high gate fields, the current in the III-V materials is largely carried in the heavier L-valleys than the lighter Gamma-valleys, due to the low density of states (DOS) in the Gamma, similar to current conduction in Ge. Moreover, these high mobility materials like In As, InSb and Ge suffer from excessive BTBT which seriously limits device performance. Large bandgap III-V materials like GaAs exhibit best performance due to an ideal combination of low conductivity effective electron mass. View full abstract»

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  • Simulation of quasi-stationary and transient effects in gan based heterostructure field effect transistors

    Publication Year: 2006 , Page(s): 51 - 56
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    Numerical simulations to compute stress distributions resulting from stressed overlayers reveal that significant stress fields can penetrate deep into device. Piezoelectric polarization effects from stressed overlayers are only mild due to relatively high stiffness in nitrides but can change band profile along the channel, especially under gate edges. Fringing fields in passivation layers with large dielectric constants can play important role in collapse reduction. View full abstract»

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  • A 2-Mask NMOS Process Design Fabricate and Test Module for Use In Microelectronics Instruction and Process Development

    Publication Year: 2006 , Page(s): 57 - 62
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    We have developed a simplified 2-mask n-type metal oxide semiconductor (NMOS) transistor process design and verification module for electrical engineering students enrolled in the Microelectronic Manufacturing Methods class/laboratory at San Jose State University. We have run this module for three years and have found that the simplified process allows the students to learn more because they have the time to design the process fabricate and test in one semester. Student learning is also enhanced because it allows students to make and correct mistakes in the processing the devices. We have also found that the simplified process saves time in process development of more complex processes, by reducing the number of photolithography steps required to fabricate a transistor. View full abstract»

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  • Effect of Process and Layout on Strain Enhancement from Dual Stress Liners

    Publication Year: 2006 , Page(s): 63
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (33 KB) |  | HTML iconHTML  

    Tensile and compressive stressed nitride liners have been used to increase the carrier mobility in n-channel and p-channel silicon transistors respectively. Simulations indicate how much of the stress in the film is transferred to the channel region and the magnitude of the stress in different directions. A simple bulk piezoresistive model was used to estimate the effect on carrier mobility. It is shown in the case of the n-channel transistors that the enhancement is due to the vertical stress component whereas in the case of p-channel devices the enhancement is due to the in-plane stresses. The effect of different process conditions such as film stress, thickness and method of deposition, on mobility enhancement, was also characterized. It is shown that the enhancement saturates with increasing nitride thickness but scales proportionally with the film stress. Detailed studies of the effect of the circuit layout on the final channel stress allow the critical layout parameters to be identified. The variation of device performance with the layout parameters is quantified and can be used to define design rules as well as equations to modify the device characteristics based on layout. View full abstract»

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  • Modeling Process Impact on Cu/Low k Interconnect Performance and Reliability

    Publication Year: 2006 , Page(s): 65 - 70
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (394 KB) |  | HTML iconHTML  

    This paper studies the impact of layout alteration and structural variation on capacitance and spatial variations of electric and thermal mismatch stress fields. The fabrication process related layout alteration and structural variation include floating dummy fill insertions, silicon nitride cap layers thickness selections, and metal line cross-section shape changes. It is demonstrated that the spatial distributions of electric field and thermal-mechanical stress field have different geometric dependence and process variations have different implications. The layout pattern and interconnect architecture that are optimized for electric performance may be inferior in reliability due to large stress concentrations. The numerical results suggest that in pursuit of manufacturability the tradeoffs between electrical performance and mechanical reliability need to be considered together for future interconnect architecture and process technology developments. View full abstract»

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  • Lithography Challenges toward Nano Scaled Device

    Publication Year: 2006 , Page(s): 71 - 75
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    Lithography has been eagerly explored into nanoscale beyond sub-micrometer in the fields of leading-edge technology applications. NNFC (National NanoFab Center) has specially concentrated on direct electron beam lithography and nanoimprint which are flexible and effective methods to be applicable to sub-100 nm patterning. Nanoscaled FinFET and MRAM(magnetic RAM) were evaluated, using hybrid e-beam lithography (double masking method, mix & matching method), i.e. optical exposure tool used to reduce the total patterning time of direct electron beam. The results from these patterning methods were able to fabricate the world's smallest transistor, 5 nm FinFET and to adapt new material and device structure to magnetic device. Also 50 nm (line & space) fabrication capability of UV imprint template (stamp in UV nanoimprint) is demonstrated in this paper. View full abstract»

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  • Academic Development in Test Engineering

    Publication Year: 2006 , Page(s): 77 - 80
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    A 2-semester program of lectures and laboratory work in mixed-signal test development engineering has been initiated at San Jose State University. Class one involves bench-top assessment on a specifically-designed printed circuit board to explore basic issues of testing: accuracy, guard bands, repeatability, correlation, and printed circuit board design. Class two revisits many of these issues in off-line and on-line programs for manufacturing testers like Agilent's 93k. The trade-offs in accuracy versus test time are focal. This paper outlines the courses and presents an example of student ATE lab work. View full abstract»

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  • Low Budget Undergraduate Microelectronics Laboratory; University Government Industry Microelectronics Symposium

    Publication Year: 2006 , Page(s): 81 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7767 KB) |  | HTML iconHTML  

    Equipment costs for semiconductor fabrication can be millions of dollars just to get started, not to mention the specialized facility expenses required to house such intricate equipment. Specialized facilities such as clean-rooms, special exhaust systems, cryo-pumps, and gas cylinder storage are a huge investment and sometimes hard to justify for undergraduate education. Chemical usage and disposal can also be a considerable expense. Very few institutions can even afford an undergraduate microelectronics laboratory due to the high start-up costs, high equipment costs and continuous and constant maintenance of such equipment. Many colleges have acquired used equipment through donations from industry. However, donated equipment from industry is not always the most feasible option for small colleges with limited budgets and resources. The technical costs of keeping the equipment going can be expensive, not to mention the difficulty of obtaining parts on used industrial equipment. Through a recent New York State Science, Technology, and Academic Research (NYSTARreg) grant opportunity, obtained in collaborations with Alfred University and Rochester Institute of Technology, Alfred State College, a small technical college in rural western New York, has started its own low budget undergraduate microelectronics laboratory facility at a fraction of the cost of comparable industrial equipment. This new undergraduate microelectronics laboratory at Alfred State College has been equipped with Modu-Labtrade semiconductor device manufacturing equipment, which gives students realistic exposure to the semiconductor planer processes. Oxidation, diffusion, photolithography, etch, and vapor deposition stations allow the students the opportunity to design, fabricate, and test their own simple diffused resistors and PMOS devices while gaining experience in microelectronic fabrication techniques. The Microelectronics Laboratory at Alfred State College gives students a realistic experience- in semiconductor manufacturing processes. An important concept of this laboratory is hands-on training. Although it is unlikely that the students will work with this type of equipment in industry, the understanding of general processes gained through laboratory experiences will prepare them to either continue their education in the microelectronics field or work in a modern industrial laboratory. Mask layers can be designed on just about any good quality CAD program. Individual layers can be printed out on transparent paper using a good quality laser printer. Diffused resistor and PMOS devices can be designed, fabricated and tested without spending millions of dollars. Functional resistors and aluminum gate PMOSFET transistors have been successfully fabricated, even though the device sizes are 100-1000 times larger than typical devices fabricated in a clean-room facility. This grant has also led to collaboration with other institutions such as Alfred University and Rochester Institute of Technology who have provided technical expertise and faculty training. Student field trips have enhanced the students' overall experience. With Modu-Lab microelectronics laboratory equipment, IC design and fabrication at the undergraduate level is now a feasible proposition for small undergraduate technical colleges. View full abstract»

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  • Survey of University Micro/Nanotechnology Cleanroom Facilities as the First Phase in the Development of a U of L Business Model

    Publication Year: 2006 , Page(s): 89 - 95
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    Approximately ten years ago, the University of Louisville made a serious research commitment in the emerging fields of micro/nano/biotechnology by allocating funds towards the construction of an effective, but relatively-small, state-of-the-art, class 100 cleanroom. In 1997 that facility (the Lutz MicroTechnology Cleanroom) was unveiled, placing U of L in the select group of US academic institutions with such facilities and the only university in the state of Kentucky with a cleanroom for general micro/nano-fabrication research and educational training. With the addition of new faculty in recent years and with the unprecedented success of those faculty, the university effectively out-grew the original 1,500 square foot cleanroom facility. To address this critical need, the University committed state funds to the construction of a new state-of-the-art $50M 120,000 sq. ft. Belknap Campus Research Building (BRB) which houses a greatly-expanded, true multi-user cleanroom "core facility" to support our escalating research/educational programs micro/nano/biotechnology. View full abstract»

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  • National NanoFab Center (NNFC): Nanofabrication Facility

    Publication Year: 2006 , Page(s): 97 - 100
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    Nanotechnology predicts revolutionary changes in human civilization for its applicability to all science, engineering and technical fields, including electronics, materials, medicine, energy etc. It has recently emerged as a new strategic field following information technology and biotechnology. The Korean government has invested on the various national programs, such as nanoFab centers, tera-level nanodevices etc. since 2001 according to a basic plan it formulated for promoting nanotechnology development efforts. It has employed a focused investment strategy on such selected fields as nano electronic devices, especially for infrastructure. The National NanoFab Center was established to encourage and support nanotechnology R&D activities in the academic, research institutes and industry as a centralized public facility for nanofabrication service. In this paper, the overview of representative facilities in Korea, and equipments and activities of NanoFab centers were introduced. View full abstract»

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  • A University-Technical College Nanoscience Training Program

    Publication Year: 2006 , Page(s): 101 - 104
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    The projected growth in successful commercialization of nanoscience products and technologies will be slowed without an adequately trained force of technician-level skilled workers. To this end, Dakota County Technical College (DCTC), a two year school in Rosemount, MN received in 2004 an NSF ATE grant to develop a nanoscience training program. The program consists of 3 semesters of coursework at DCTC in various aspects of nanotechnology, followed by a capstone semester at the University of Minnesota (UM). The capstone semester consists of 4 lecture-based courses and 3 lab courses. One of the lab courses is a fabrication course taking place in the UM Nanofabrication Center cleanroom facility. At the conclusion of the capstone semester the students graduate from DCTC with a AAS degree in Nanoscience Technology, and also have 16 credits from the University of MN. View full abstract»

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