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Proceedings Tenth International Conference on VLSI Design

4-7 Jan. 1997

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Displaying Results 1 - 25 of 107
  • Proceedings Tenth International Conference on VLSI Design

    Publication Year: 1997
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    Freely Available from IEEE
  • Design for testability: today and in the future

    Publication Year: 1997, Page(s):314 - 315
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (170 KB)

    Summary form only given. The author reviews the current techniques with a particular emphasis on today's Scan Designs. This entails distinguishing the differences between scan techniques, since all scans are not created equal! From this point the Testability Standards are discussed; these include the Boundary Scan activities and the Analog activities. Fault models are taking on more robust attribu... View full abstract»

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  • Author index

    Publication Year: 1997, Page(s):564 - 566
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    Freely Available from IEEE
  • Low-power configurable processor array for DLMS adaptive filtering

    Publication Year: 1997, Page(s):198 - 203
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    In this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance and power dissipation. This architecture is the... View full abstract»

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  • Low-power design by hazard filtering

    Publication Year: 1997, Page(s):193 - 197
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Before signals of a digital circuit reach steady state, gates can have multiple transitions. Since the power is dissipated in a CMOS circuit mainly due to transitions, the extra transitions increase power consumption. These transitions are the hazard pulses generated by a logic gate when signals arrive by paths of varying delays. The maximum width of a hazard pulse produced by a gate is the maximu... View full abstract»

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  • Some recent advances in software and hardware logic simulation

    Publication Year: 1997, Page(s):232 - 238
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Logic simulation is a critical step in the design of a logic circuit. With the growing complexity of designs today, a large number of test vectors needs to be applied to the circuit to determine if the circuit behaves logically as it is supposed to. Not surprisingly, then, simulation is one of the major bottlenecks in the design process. Significant advances have been made in both software and har... View full abstract»

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  • Dynamic power management for microprocessors: a case study

    Publication Year: 1997, Page(s):185 - 192
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB)

    Dynamic power management is one of the most popular and successful low power design techniques in commercial integrated circuits, especially microprocessors. However, despite its significance, relatively little has been published about it. The purpose of this paper is to provide an open discussion of the application of dynamic power management for a real microprocessor. TORCH, a statically schedul... View full abstract»

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  • Inductive verification of sequential circuits with a datapath

    Publication Year: 1997, Page(s):226 - 231
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    A backward reasoning approach to verify a digital circuit is described. The proposed proof procedure is an augmentation of inductive reasoning over the states of a finite state machine. The augmentation addresses the issues related to reasoning with both the data and control paths of the circuit. The methodology has been illustrated with a lift controller example. Limitation of this proof approach... View full abstract»

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  • Synthesis for logical initializability of synchronous finite state machines

    Publication Year: 1997, Page(s):76 - 80
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    We present a new method for the synthesis for logical initializability of synchronous state machines. The goal is to produce a gate-level implementation that is initializable when simulated by a 3-valued (0,1,X) simulator. We build on the approach of Cheng and Agrawal (1989,92) who constrain state assignment to translate functional initializability into logic initializability. We propose an altern... View full abstract»

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  • Interconnection delay and clock cycle selection in high level synthesis

    Publication Year: 1997, Page(s):504 - 505
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    This paper presents a method to estimate the delay of interconnections. It uses a simple model based exclusively on point to point interconnections. The method has a very low complexity so it can be used during the clock cycle selection in a High Level Synthesis process. In this way it is possible to settle securely the right electrical behavior of the final circuit View full abstract»

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  • Behavioral array mapping into multiport memories targeting low power

    Publication Year: 1997, Page(s):268 - 272
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Off chip memories are typically used during behavioral synthesis to store large arrays that do not fit into on-chip registers. An important power-optimization problem that arises in this context is the minimization of signal transitions on the off-chip buses connecting the ASIC and the memory. We address the problem of system power reduction through transition count minimization on the multiported... View full abstract»

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  • Low-power driven logic synthesis using accurate power estimation technique

    Publication Year: 1997, Page(s):179 - 184
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    With the increasing use of portable computing and wireless communication systems, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Towards this end we introduce algebraic procedures for node extraction and factorization that target low power consumption in combinational logic circuits. A new cost function is also proposed for the sum-of-products ... View full abstract»

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  • Formal verification of combinational circuits

    Publication Year: 1997, Page(s):218 - 225
    Cited by:  Papers (15)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are generally inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal methods to guarantee the correctness of their designs. In this paper we survey some state-of-the-art... View full abstract»

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  • Simulated annealing based parallel state assignment of finite state machines

    Publication Year: 1997, Page(s):69 - 75
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Simulated annealing has been an effective tool in many optimization problems in VLSI CAD but its time requirements are prohibitive. In this paper, we report a parallel algorithm for a well established, simulated annealing based algorithm for the state assignment problem for finite state machines. Our parallel annealing strategy uses parallel moves by multiple processes, each performing local moves... View full abstract»

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  • A 2.5 V 10 bit SAR ADC

    Publication Year: 1997, Page(s):525 - 526
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    Presented here is a 10 bit SAR ADC working over a wide supply range of 5.5 V to 2.5 V. The circuit is built in a CMOS process with Metal-Poly capacitors. Issues related to low voltage sampling circuitry design and low voltage high speed comparator design are discussed. Silicon evaluation results are presented View full abstract»

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  • An enhanced genetic solution for scheduling, module allocation, and binding in VLSI design

    Publication Year: 1997, Page(s):51 - 56
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper presents a novel approach to the high-level synthesis problems of scheduling, module allocation, and module binding for behavioral descriptions. A very general version of this problem is considered where modules may perform different operations in different numbers of control steps. These inherently interdependent problems are solved using an Enhanced Genetic Algorithm (EGA) which is bo... View full abstract»

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  • Optimal design of checksum-based checkers for fault detection in linear analog circuits

    Publication Year: 1997, Page(s):393 - 397
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Traditionally, built-in self-test (BIST) techniques have assumed access to only the input and output nodes of the circuit under test (CUT). It has been shown earlier, that checksum-based checkers can be designed to perform on-line fault detection in linear analog circuits using access to certain internal nodes of CUT. In this paper, we address the problem of optimizing the checker circuitry to max... View full abstract»

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  • Overcoming the serial logic simulation bottleneck in parallel fault simulation

    Publication Year: 1997, Page(s):495 - 501
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    We propose a new approach to parallelizing fault simulation in which the test set is partitioned among the available processors. The approach can be used for any of the sequential circuit fault simulation algorithms commonly used, and it can be implemented on various different parallel architectures. This approach for the first time overcomes the limitations of serial logic simulation. In addition... View full abstract»

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  • The design of a digital IC for thyristor triggering

    Publication Year: 1997, Page(s):461 - 464
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    This paper presents the functional description and the design of a fully digital integrated circuit for thyristor firing control in a 1 μm CMOS technology. The architecture is based on the equidistant firing method, which allows the change of the displacement between two consecutive pulses before the zero crossing of the AC power source that is used as a synchronism signal. The circuit is desig... View full abstract»

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  • Input pattern classification for detection of stuck-ON and bridging faults using IDDQ testing in BiCMOS and CMOS circuits

    Publication Year: 1997, Page(s):545 - 546
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    Quiescent power supply current monitoring (IDDQ) has been shown to be effective for testing CMOS devices. BiCMOS is emerging as a major technology for high speed, high performance, digital and mixed signal applications. Stuck-ON faults as well as bridging faults in BiCMOS circuits cause enhanced IDDQ. An input pattern classification scheme is presented for detection of stuck-... View full abstract»

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  • A method for synthesizing area efficient multilevel PTL circuits

    Publication Year: 1997, Page(s):516 - 518
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    Pass transistor logic (PTL) circuits are known to be well suited for pipelined circuits and have been receiving considerable interest in recent times. Existing techniques for synthesizing PTL circuits are based on two level networks of transistors. In this paper, we have proposed a new decision diagram based model for multilevel PTL circuits. We have described a number of transformations on our mo... View full abstract»

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  • Synthesis of analog CMOS circuits

    Publication Year: 1997, Page(s):439 - 444
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    In this paper we describe an efficient method for transistor sizing in cell level analog circuits. An equation based method is used. SPICE quality device models are used and the sizing problem is posed as an optimisation problem. KCL, KVL and matching constraints are taken in to account in the formulation of the optimisation problem without explicitly introducing them as constraints as was done pr... View full abstract»

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  • Energy-efficiency of VLSI caches: a comparative study

    Publication Year: 1997, Page(s):261 - 267
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    We investigate the use of organizational alternatives that lead to more energy-efficient caches for contemporary microprocessors. Dissipative transitions are likely to be highly correlated and skewed in caches, precluding the use of simplistic hit/miss ratio based power dissipation models for accurate power estimations. We use a detailed register-level simulator for a typical pipelined CPU and its... View full abstract»

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  • Algorithms for low power FIR filter realization using differential coefficients

    Publication Year: 1997, Page(s):174 - 178
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    We present a set of new algorithms for low-power realization of FIR filters which use various orders of differences between coefficients for computing the convolution with the input data. Also the results of computations are stored and reused, thus requiring more storage and storage accesses. These techniques result in a reduction in the computations necessary per convolution as compared to direct... View full abstract»

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  • Formal verification of digital systems

    Publication Year: 1997, Page(s):213 - 217
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A formal verifier is an automated decision procedure that can prove or disprove a set of statements in some logical system of reasoning. Problems informal verification have been posed and studied in a variety of disciplines for many years. However the last ten years have produced significant advances in both the theory and practical art of building formal verifiers. Various formal proof techniques... View full abstract»

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