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VLSI Design, 1997. Proceedings., Tenth International Conference on

Date 4-7 Jan. 1997

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  • Proceedings Tenth International Conference on VLSI Design

    Publication Year: 1997
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    Freely Available from IEEE
  • Author index

    Publication Year: 1997, Page(s):564 - 566
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    Freely Available from IEEE
  • Optimizing test hardware for at-speed testing of datapaths in an integrated circuit

    Publication Year: 1997, Page(s):289 - 296
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    In this paper, we introduce a new representation method for datapath tests-called test template representation-and also introduce a new analysis technique to minimize the test logic overhead, through careful processing of the test templates. The resultant test structures represent the next systematic step beyond the multiplexer bypass method commonly found in commercial test tools View full abstract»

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  • A novel hierarchical test generation method for processors

    Publication Year: 1997, Page(s):540 - 541
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    This paper describes a novel method for hierarchical functional test generation for processors. This method targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Since the commercial tools are unable to deal with the entire design, functional constraints are first extracted for the module. The extracted constraints are described in Veril... View full abstract»

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  • A practical method for selecting partial scan flip-flops for large circuits

    Publication Year: 1997, Page(s):284 - 288
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    This paper describes a method of flip-flop selection (for BIST or Partial Scan) where the selection process proceeds in a module by module basis. A complete circuit is assumed to be made up of different modules. The method uses the circuit graph of an individual module and uses the top level connectivity information in between modules to select flip-flops in that module. It then deletes the module... View full abstract»

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  • Faster fault simulation through distributed computing

    Publication Year: 1997, Page(s):482 - 487
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors -test set partition and fault set partition. The sequential algorithm for fault simu... View full abstract»

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  • Impact of partial reset on fault independent testing and BIST

    Publication Year: 1997, Page(s):537 - 539
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    Partial reset has been shown to have significant impact on deterministic test generation for sequential circuits. In this paper we explore the use of partial reset in fault-independent testing and application to built-in self-test. We take the following approach: based on fault propagation analysis, we select a subset of the circuit flip-flops to be initialized to 0 or 1. The initialization (set/r... View full abstract»

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  • Characterization and implicit identification of sequential indistinguishability

    Publication Year: 1997, Page(s):376 - 380
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Effective diagnosis of integrated circuits relies critically on the quality of diagnostic test vectors. Diagnostic test pattern generation aims at producing test vectors that distinguish between all distinguishable pairs of faults, and proving the remaining pairs of faults to be indistinguishable. Proving indistinguishabilities, much like proving undetectabilities in the case of detection-oriented... View full abstract»

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  • Pseudo Kronecker expressions for symmetric functions

    Publication Year: 1997, Page(s):511 - 513
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Pseudo Kronecker Expressions (PSDKROs) are a class of AND/EXOR expressions. In this paper it is proven that exact minimization of PSDKROs for totally symmetric functions can be performed in polynomial time. A new implementation method for PSDKROs is presented. Experimental results are given to show the efficiency of the presented approach in comparison to previously published work on AND/EXOR mini... View full abstract»

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  • Synthesis for testability by two-clock control

    Publication Year: 1997, Page(s):279 - 283
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    In previous studies clock control has been inserted after design to improve the testability of a sequential circuit. In this paper we propose a two-clock control scheme that is included as a part of the logic synthesis of a finite state machine (FSM). The scheme has low area overhead and competes well with scan methods in its ability to initialize and observe circuit states. The states of the mach... View full abstract»

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  • Parallel genetic algorithms for simulation-based sequential circuit test generation

    Publication Year: 1997, Page(s):475 - 481
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more difficult as the complexity of VLSI circuits increases, and as long as execution times pose an additional problem. Parallel implementations can potentially provide significant speedups while retaining good quality results. In this paper, we present three parallel genetic algorithms for simu... View full abstract»

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  • (Quasi-) linear path delay fault tests for adders

    Publication Year: 1997, Page(s):101 - 105
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    We investigate the path delay fault testability of the adder function. A method to reduce the number of tests is presented and applied to several well-known hardware realizations, like the Carry Ripple Adder (CRA) and the the Carry Look Ahead Adder (CLA). Depending on the structure we obtain linear or quasi-linear, i.e. O(n) or O(n log n), respectively, size for a complete test of the whole adder ... View full abstract»

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  • On full reset as a design-for-testability technique

    Publication Year: 1997, Page(s):534 - 536
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Full scan design allows every combinationally irredundant fault in a synchronous sequential circuit to be tested. In this paper, we derive a similar result applicable to design-for-testability techniques that use reset instead of scan. We show that if reset states can be selected arbitrarily, a test sequence can be generated for every irredundant fault, i.e., for every fault which is not sequentia... View full abstract»

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  • FLYER: fast fault simulation of linear analog circuits using polynomial waveform and perturbed state representation

    Publication Year: 1997, Page(s):408 - 412
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    In this paper we propose a methodology for obtaining a closed form expression for the output of a linear analog circuits from its state-space description. Voltage waveforms at all the nodes of the circuit are obtained as polynomials in time. This closed form expressions for the circuit response together with the adjoint network method and sparse matrix techniques enhances fast parallel fault simul... View full abstract»

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  • A novel reconfigurable co-processor architecture

    Publication Year: 1997, Page(s):370 - 375
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Back-end processors have been conventionally used for speeding up of only a specific set of compute intensive functions. Such co-processors are, generally, “hardwired” and cannot be used for a new function. In this paper, we discuss the design considerations and parameters of a general purpose reconfigurable co-processor. We also propose architecture of such a co-processor and discuss ... View full abstract»

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  • A new methodology for the design of asynchronous digital circuits

    Publication Year: 1997, Page(s):342 - 347
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    This paper discusses a new design methodology for asynchronous digital circuits. The methodology is based on an event driven scheme and follows the double-rail logic handshake protocol. A new logic gate, called the Universal Gate, is designed; this is the basic building block of the methodology. It is shown that the methodology, is completely delay insensitive. As an example, the Shift Multiplier ... View full abstract»

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  • Algorithms for low power FIR filter realization using differential coefficients

    Publication Year: 1997, Page(s):174 - 178
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    We present a set of new algorithms for low-power realization of FIR filters which use various orders of differences between coefficients for computing the convolution with the input data. Also the results of computations are stored and reused, thus requiring more storage and storage accesses. These techniques result in a reduction in the computations necessary per convolution as compared to direct... View full abstract»

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  • A simulation methodology for software energy evaluation

    Publication Year: 1997, Page(s):509 - 510
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    We describe a comprehensive simulation methodology and tool for evaluation of software energy for the pipelined DLX processor. Energy models for each module of DLX are built and the energy is evaluated during run time execution. The input to the simulator are the instructions of the program and the simulator estimates energy of each micro-instruction using the energy models. Our simulator allows e... View full abstract»

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  • Sequential circuit testing: from DFT to SFT

    Publication Year: 1997, Page(s):274 - 278
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Sequential circuit testing is an active research area due to its applicability, its practicality, and its complexity. This paper gives an overview of the sequential automatic test pattern generation approaches and the classical and more recent design-for-testability methods. However, recent trend is to move towards synthesis-for-testability (SFT) approach. In this paper, we describe some of the wo... View full abstract»

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  • Industrial strength formal verification techniques for hardware designs

    Publication Year: 1997, Page(s):208 - 212
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The past decade has seen tremendous progress in the application of formal methods for hardware design and verification. While a number of different techniques based on BDDs, symbolic simulation, special-purpose decision procedures, model checking, and theorem proving have been applied with varying degrees of success, no one technique by itself has proven to be effective enough to verify a complex ... View full abstract»

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  • On the detection of reset faults; in synchronous sequential circuits

    Publication Year: 1997, Page(s):470 - 474
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    We consider the problem of testing reset faults in synchronous sequential circuits with reset hardware. The reset hardware is assumed to consist of a reset input connected to all the flip-flops through a reset line. We propose a fault model that accommodates any routing of the reset line to the flip-flops. This is important since test generation is typically carried out without knowledge of the wa... View full abstract»

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  • Macro block based FPGA floorplanning

    Publication Year: 1997, Page(s):21 - 26
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper describes the floorplanning for FPGA based designs. In order to perform placement for very large designs, the currently followed approach of placing flat netlists is extremely time consuming. Also, managing large data sets, as in flat netlist files, is not trivial for performance driven designs. In this paper we describe an approach for the constraint-based FPGA floorplanning of flexibl... View full abstract»

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  • Analyzing controllability of a hardware circuit for its reuse

    Publication Year: 1997, Page(s):151 - 154
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    In this paper, a scheme has been proposed to identify under what condition a circuit, capable of performing a given set of operations/functions, can be reused while designing another circuit. This is characterized by a concept called external controllability of a function. When a function is externally controllable, the circuit executing the function, can be reused subsequently. The concept of ext... View full abstract»

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  • Primitive path delay fault identification

    Publication Year: 1997, Page(s):95 - 100
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    We present a novel and efficient method to identify all primitive single and multi path delay faults (PDFs) in multi-level combinational circuits. Our method is the first one to successfully target the primitive PDF identification problem for multi-level circuits-previous research results in this area have been limited either to the identification of primitive PDFs only for 2-level circuits, or to... View full abstract»

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  • Asynchronous implementation of synchronous Esterel specifications

    Publication Year: 1997, Page(s):348 - 353
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this trans... View full abstract»

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