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Application of Concurrency to System Design, 2007. ACSD 2007. Seventh International Conference on

Date 10-13 July 2007

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Displaying Results 1 - 25 of 38
  • Seventh International Conference on Application of Concurrency to System Design - Cover

    Publication Year: 2007 , Page(s): c1
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  • Seventh International Conference on Application of Concurrency to System Design-Title

    Publication Year: 2007 , Page(s): i - iii
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  • Seventh International Conference on Application of Concurrency to System Design-Copyright

    Publication Year: 2007 , Page(s): iv
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  • Seventh International Conference on Application of Concurrency to System Design - TOC

    Publication Year: 2007
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  • Foreword

    Publication Year: 2007 , Page(s): viii
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  • ACSD 2007 Organization

    Publication Year: 2007 , Page(s): ix
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  • Program Committee

    Publication Year: 2007 , Page(s): x
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  • Additional reviewers

    Publication Year: 2007 , Page(s): xi
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  • Finding Structure in Unstructured Processes: The Case for Process Mining

    Publication Year: 2007 , Page(s): 3 - 12
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (788 KB) |  | HTML iconHTML  

    Today there are many process mining techniques that allow for the automatic construction of process models based on event logs. Unlike synthesis techniques (e.g., based on regions), process mining aims at the discovery of models (e.g., Petri nets) from incomplete information (i.e., only example behavior is given). The more mature process mining techniques perform well on structured processes. Howe... View full abstract»

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  • Synthesis and Control of Asynchronous and Distributed Systems

    Publication Year: 2007 , Page(s): 13 - 22
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    We survey research works on asynchronous systems synthesis, including PN synthesis and control synthesis. View full abstract»

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  • Composable Guarded Atomic Actions: a Bridging Model for SoC Design

    Publication Year: 2007 , Page(s): 23 - 28
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (176 KB) |  | HTML iconHTML  

    We discuss the approach to concurrency in Bluespec's commercial tools that enable chip designers to deal with complex concurrency, the hallmark of today's systems on a chip. We discuss the basic concurrency model (rules, or guarded atomic actions); modular construction of rules; scheduling into clocked synchronous hardware, including multiple clock domains; non-determinism vs. determinism, and pre... View full abstract»

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  • Mapping Applications to Tiled Multiprocessor Embedded Systems

    Publication Year: 2007 , Page(s): 29 - 40
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    Modern multiprocessor embedded systems execute a large number of tasks on shared processors and handle their complex communications on shared communication networks. Traditional methods from the HW /SW codesign or general purpose computing domain cannot be applied any more to cope with this new class of complex systems. To overcome this problem, a framework called Distributed Operation Layer (DOL)... View full abstract»

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  • Emptiness Check of Powerset Buchi Automata using Inclusion Tests

    Publication Year: 2007 , Page(s): 41 - 50
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (310 KB) |  | HTML iconHTML  

    We introduce two emptiness checks for buchi automata whose states represent sets that may include each other. The first is equivalent to a traditional emptiness check but uses inclusion tests to direct the on-the-fly construction of the automaton. The second is impressively faster but may return false negatives. We illustrate and benchmark the improvement on a symmetry-based reduction. View full abstract»

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  • Hazard Checking of Timed Asynchronous Circuits Revisited

    Publication Year: 2007 , Page(s): 51 - 60
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion, or efficient algorithms which use a (conservative) approximation to avoid state-space explosion but can result in the rejection of designs which are valid. In particular, [7] presents a timed extention of the work in [1... View full abstract»

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  • A more efficient time Petri net state space abstraction preserving linear properties

    Publication Year: 2007 , Page(s): 61 - 70
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (303 KB) |  | HTML iconHTML  

    We consider here time Petri nets (TPN model). We first propose an abstraction to its generally infinite state space which preserves linear properties of the TPN model. Comparing with TPN abstractions proposed in the literature, our abstraction produces graphs which are both smaller and faster to compute. In addition, our characterization of abstracted states allows a significative gain in space. A... View full abstract»

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  • A Formal Model for Integrating Multiple Views

    Publication Year: 2007 , Page(s): 71 - 79
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (219 KB) |  | HTML iconHTML  

    In this paper we show how to use labelled event structures as a unique mathematical representation for design models consisting of different UML 2.0 diagrams/notation. Each diagram is used to capture a particular aspect or view of the system including structural and behavioural aspects. Our approach enables the analysis of complex systems designed in a combination of UML 2.0 notation, and serves a... View full abstract»

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  • Using CTL formulae as component abstraction in a design and verification flow

    Publication Year: 2007 , Page(s): 80 - 89
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (185 KB) |  | HTML iconHTML  

    In the context of component-based design, the verification of global properties (involving several components) is difficult to achieve, due to combinatorial explosion problem, while the verification of each component is easier to perform. Following the idea of [24], we propose to build an abstraction of a component already verified, starting from a subset of its specification described as CTL form... View full abstract»

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  • Sensor Minimization Problems with Static or Dynamic Observers for Fault Diagnosis

    Publication Year: 2007 , Page(s): 90 - 99
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    We study sensor minimization problems in the context of fault diagnosis. Fault diagnosis consists of synthesizing a diagnoser that observes a given plant and identifies faults in the plant as soon as possible after their occurrence. Existing literature on this problem has considered the case of static observers, where the set of observable events does not change during execution of the system. In ... View full abstract»

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  • The Design of Virtual Self-timed Block for Activity Communication in SOC

    Publication Year: 2007 , Page(s): 100 - 109
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (750 KB) |  | HTML iconHTML  

    In this paper we present the architecture for virtual self-timed blocks. Being globally asynchronous locally synchronous (GALS) and lazy reactive processing units, such blocks target multi-processing on-chip systems where power consumption is an important factor. The architecture provides a hardware foundation which transparently supports the systematic organization of application-level activities... View full abstract»

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  • Modelling Mobility in High-level Petri Nets

    Publication Year: 2007 , Page(s): 110 - 119
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    We propose a structural translation of terms from a variant of the KLAIM process algebra which includes arbitrary tuples of data values as well as conditionals into behaviourally equivalent high-level Petri nets. This defines a semantics for mobility allowing one to deal directly with concurrency and causality. View full abstract»

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  • Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector

    Publication Year: 2007 , Page(s): 120 - 126
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (333 KB) |  | HTML iconHTML  

    The Plessey corner detector is a key technological component in scene analysis, stereo matching, and object tracking. Due to its high computation complexity, earlier fast implementations mainly focused on hardware implementations. This paper explores the viability of a multi-processor software implementation. A scalable task partitioning for efficiently mapping the Plessey algorithm on a multi-pro... View full abstract»

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  • A model-driven design approach for mechatronic systems

    Publication Year: 2007 , Page(s): 127 - 136
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    The software design is one of the most challenging tasks during the design of a mechatronic system. On one hand, it has to provide solutions to deal with concurrency and timeliness issues of the system. On the other hand, it has to glue different disciplines (such as software, control and mechanical) of the system as a whole. In this paper, we propose a model-driven approach to design the software... View full abstract»

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  • Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings

    Publication Year: 2007 , Page(s): 137 - 146
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. In this paper, a fully automatic technique for resolving such conflicts by means of insertion of new signals is proposed. It is based on conflict cores, i.e., sets of transitions causing encoding conflicts, which are represented at the ... View full abstract»

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  • Output-Determinacy and Asynchronous Circuit Synthesis

    Publication Year: 2007 , Page(s): 147 - 156
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (271 KB) |  | HTML iconHTML  

    Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour. In this paper we propose (and justify) a formal semantics of nondeterministic STGs with dummies and OR-causality. For this, we introduce the concept of output-determinacy, which is a relaxation of determinism, and argue that it is reasonable and useful in the speed-independent context. With our th... View full abstract»

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  • Synthesis of Petri Nets from Finite Partial Languages

    Publication Year: 2007 , Page(s): 157 - 166
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (231 KB) |  | HTML iconHTML  

    In this paper we present an algorithm to synthesize a finite place/transition Petri net (p/t-net) from a finite set of labeled partial orders (a finite partial language). This p/t-net has minimal non-sequential behavior including the specified partial language. Consequently, either this net has exactly the non-sequential behavior specified by the partial language, or there is no such p/t-net. We f... View full abstract»

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