By Topic

13th IEEE International On-Line Testing Symposium (IOLTS 2007)

Date 8-11 July 2007

Filter Results

Displaying Results 1 - 25 of 67
  • 13th IEEE International On-Line Testing Symposium - Cover

    Publication Year: 2007, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (4014 KB)
    Freely Available from IEEE
  • 13th IEEE International On-Line Testing Symposium-Title

    Publication Year: 2007, Page(s):i - iii
    Request permission for commercial reuse | PDF file iconPDF (52 KB)
    Freely Available from IEEE
  • 13th IEEE International On-Line Testing Symposium-Copyright

    Publication Year: 2007, Page(s): iv
    Request permission for commercial reuse | PDF file iconPDF (43 KB)
    Freely Available from IEEE
  • 13th IEEE International On-Line Testing Symposium - TOC

    Publication Year: 2007, Page(s): v
    Request permission for commercial reuse | PDF file iconPDF (66 KB)
    Freely Available from IEEE
  • Message from the General Co-Chairs and the Program Co-Chairs

    Publication Year: 2007, Page(s): xi
    Request permission for commercial reuse | PDF file iconPDF (33 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2007, Page(s): xii
    Request permission for commercial reuse | PDF file iconPDF (27 KB)
    Freely Available from IEEE
  • Program Committee

    Publication Year: 2007, Page(s): xiii
    Request permission for commercial reuse | PDF file iconPDF (30 KB)
    Freely Available from IEEE
  • IEEE Computer Society TTTC: Test Technology Technical Council

    Publication Year: 2007, Page(s): xiv
    Request permission for commercial reuse | PDF file iconPDF (60 KB) | HTML iconHTML
    Freely Available from IEEE
  • Soft Errors: Technology Trends, System Effects, and Protection Techniques

    Publication Year: 2007, Page(s): 4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (197 KB)

    Radiation-induced soft errors are getting worse in digital systems manufactured in advanced technologies. Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors in sequential elements and combinational logic. This tutorial will discuss the impact of technology scaling on soft error rates, circuit-level mode... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Soft-Errors Phenomenon Impacts on Design for Reliability Technologies

    Publication Year: 2007, Page(s): 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (131 KB) | HTML iconHTML

    Summary form only given. We mainly address here the "alter ego" of quality, which is reliability, and is becoming a growing concern for designers using the latest technologies. After the DFM nodes in 90 nm and 65 nm, we are entering the DFR area, or design for reliability straddling from 65 nm to 45 nm and beyond. Because of the randomness character of reliability - failures can happen anytime any... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accelerating Yield Ramp through Real-Time Testing

    Publication Year: 2007, Page(s): 11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (102 KB)

    With the increasing need for design specific yield optimization in nanometer technologies, it is becoming increasingly important to accelerate the identification of the root cause of systematic defects under very tight test cost constraints. This talk will give a high level overview of addressing these demanding challenges through a mix of cross-disciplinary EDA technologies spanning scan diagnost... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fuse: A Technique to Anticipate Failures due to Degradation in ALUs

    Publication Year: 2007, Page(s):15 - 22
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (357 KB) | HTML iconHTML

    This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measure its degradation. By mimicking the behavior of the replicated transistor the fuse anticipates the failure short before the first failure in the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design for Resilience to Soft Errors and Variations

    Publication Year: 2007, Page(s):23 - 28
    Cited by:  Papers (10)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB) | HTML iconHTML

    This paper presents adaptive variation-and-error-resilient agent (AVERA), an approach to address the challenge of designing reliable systems in the presence of soft errors and variations. AVERA extends our previous built-in soft error resilience (BISER) approach by adding additional capabilities to support process variation diagnosis, degradation detection, and system adaptation, besides soft erro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield

    Publication Year: 2007, Page(s):29 - 36
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    High defect rate in emerging nano-devices mandates new computational models that can tolerate defects thereby rendering reliability of operation and reasonable manufacturing yield. In a bottom-up system design approach using nano-crossbar applications are typically mapped into a crossbar using either PLA or lookup table (LUT) implementation of a logic circuits. LUT-based implementation has some de... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Essential Fault-Tolerance Metrics for NoC Infrastructures

    Publication Year: 2007, Page(s):37 - 42
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    Fault-tolerant design of network-on-chip communication architectures requires the addressing of issues pertaining to different elements described at different levels of design abstraction - these may be specific to architecture, interconnection, communication and application issues. Assessing the effectiveness of a particular fault-tolerant implementation can be a challenging task for designers, c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Configurable Error Control Scheme for NoC Signal Integrity

    Publication Year: 2007, Page(s):43 - 48
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB) | HTML iconHTML

    In this paper we propose a novel error control scheme to cope with errors affecting the communication links of a NoC. Our scheme can be configured in correction mode, detection mode, and mixed mode, depending on the particular application, thus allowing to meet different quality of service (QoS) levels in terms of error control. For each configuration mode, we propose different error control polic... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Analytical Model for Reliability Evaluation of NoC Architectures

    Publication Year: 2007, Page(s):49 - 56
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (317 KB) | HTML iconHTML

    This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The proposed method classifies switch faults of an NoC according to their impact on system functionality. Based on this classification, the contribution of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An On-Line Fault Detection Scheme for SBoxes in Secure Circuits

    Publication Year: 2007, Page(s):57 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (294 KB) | HTML iconHTML

    In this paper we propose an on-line fault detection architecture for bijective Substitution Boxes used in cryptographic circuits. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults, it also protects the system against side-channel attacks, in particular those based on fault injection. We will prove that our solution is ve... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks?

    Publication Year: 2007, Page(s):63 - 70
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (507 KB) | HTML iconHTML

    Latchup is a short-circuit that can be triggered in CMOS ICs when a current pulse is produced by parasitic perturbations. It is usually regarded as very disturbing for reliability, especially in space applications where it is triggered by ionizing particles naturally present in the environment. But in another context, the one of crypto-processors, it could be used as a way to protect the device fr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding

    Publication Year: 2007, Page(s):71 - 78
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (191 KB) | HTML iconHTML

    In this paper we present an efficient design technique for implementing the elliptic curve cryptographic (ECC) scheme in FPGAs. Our technique is based on a novel and efficient implementation of modular multiplication which is the core operation of ECC. To implement large bit-length multiplications we used a novel partitioning and pipeline folding scheme to fit at least 256-bit modular multiplicati... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Online monitoring of FPGA-based co-processing engines embedded in dependable workstations

    Publication Year: 2007, Page(s):79 - 84
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB) | HTML iconHTML

    An assertion-based monitoring system was implemented to enforce the operation of a FPGA coprocessing engine, which is part of a dependable workstation. The monitor was built in VHDL using simple state machines. Concurrent error detection is an important aspect in dependable workstations helping to prevent the propagation of errors within the system. The functionality of the implemented monitoring ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant Spacecraft Supercomputers

    Publication Year: 2007, Page(s):85 - 92
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    Commercial off-the-shelf (COTS) electronic components are attractive for space applications. However, fault-tolerant architectures are required to cope with the Single Event Effect sensitivity of these components. CNES has developed a methodology, and the related validation tools, by injecting faults into these fault- tolerant architectures for validation purposes. The methodology is a hybrid one,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs

    Publication Year: 2007, Page(s):93 - 100
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (607 KB) | HTML iconHTML

    This paper presents a new approach based on a watchdog infrastructure intellectual property (I-IP) core to detect control-flow faults that affect CPU execution time. More precisely, this approach aims at detecting those faults that change the expected CPU instruction sequence and that as consequence, change also (by increasing or reducing) the expected CPU time allocated for the execution of the m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors

    Publication Year: 2007, Page(s):101 - 106
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (221 KB) | HTML iconHTML

    Processors are very common components in current digital systems and to assess their reliability is an essential task during the design process. In this paper a new fault injection solution to measure SEU sensitivity in processors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). It can be widely applic... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Hybrid Approach to Fault Detection and Correction in SoCs

    Publication Year: 2007, Page(s):107 - 112
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    The reliability of Systems-on-Chip (SoCs) is very important with respect to their use in different types of critical applications. Several fault tolerance techniques have been proposed to improve their fault detection and correction capabilities. These approaches can be classified in two basic categories: software-based and hardware-based techniques. In this paper, we propose a hybrid approach to ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.