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18th IEEE Symposium on Computer Arithmetic (ARITH '07)

Date 25-27 June 2007

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Displaying Results 1 - 25 of 38
  • 18th IEEE Symposium on Computer Arithmetic - Cover

    Publication Year: 2007, Page(s): c1
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  • 18th IEEE Symposium on Computer Arithmetic - Title

    Publication Year: 2007, Page(s):i - iii
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  • 18th IEEE Symposium on Computer Arithmetic - Copyright

    Publication Year: 2007, Page(s): iv
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  • 18th IEEE Symposium on Computer Arithmetic - Table of contents

    Publication Year: 2007, Page(s):v - viii
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  • Foreword

    Publication Year: 2007, Page(s): ix
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  • Program Committee

    Publication Year: 2007, Page(s): x
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  • Steering Committee / Symposium Committee

    Publication Year: 2007, Page(s): xi
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  • list-reviewer

    Publication Year: 2007, Page(s): xii
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  • The Return of Silicon Efficiency

    Publication Year: 2007, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (91 KB) | HTML iconHTML

    Summary form only given. The economic and physical forces which have always shaped the business of digital chip design are again evolving to change the priorities of designers. Key physical trends include the end of gate oxide thickness scaling, and the effect of small dopant populations on threshold voltage variance. Key economic trends include the need to tolerate specification shift and design ... View full abstract»

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  • Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

    Publication Year: 2007, Page(s):7 - 15
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (651 KB) | HTML iconHTML

    An emerging nanotechnology, quantum-dot cellular automata (QCA), has the potential for attractive features such as faster speed, smaller size, and lower power consumption than transistor based technology. Quantum-dot cellular automata has a simple cell as the basic element. The cell is used as a building block to construct gates, wires, and memories. Several adder designs have been proposed, but m... View full abstract»

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  • Robust Energy-Efficient Adder Topologies

    Publication Year: 2007, Page(s):16 - 28
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB) | HTML iconHTML

    In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32- bit adder topologies, to determine how architectural features and design techniques affect energy efficiency. Optimizing different adders for the supply and threshold voltages, and transistor sizing, we show that topologies with the least number of log... View full abstract»

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  • A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format

    Publication Year: 2007, Page(s):29 - 37
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    The IEEE Standard 754-1985 for binary floating-point arithmetic [1] was revised [2], and an important addition is the definition of decimal floating-point arithmetic. This is intended mainly to provide a robust, reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic ma... View full abstract»

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  • Solving Constraints on the Intermediate Result of Decimal Floating-Point Operations

    Publication Year: 2007, Page(s):38 - 45
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (166 KB) | HTML iconHTML

    The draft revision of the IEEE Standard for Floating- Point Arithmetic (IEEE P754) includes a definition for decimal floating-point (FP) in addition to the widely used binary FP specification. The decimal standard raises new concerns with regard to the verification of hardware- and software-based designs. The verification process normally emphasizes intricate corner cases and uncommon events. The ... View full abstract»

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  • Decimal Floating-Point Multiplication Via Carry-Save Addition

    Publication Year: 2007, Page(s):46 - 55
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (175 KB) | HTML iconHTML

    Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of a decimal floating-point multiplier that complies with specifications for decimal multiplication given in the draft revision of the IEEE 754 standard for floating-point arithmetic (IEEE 754R). T... View full abstract»

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  • Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding

    Publication Year: 2007, Page(s):56 - 68
    Cited by:  Papers (9)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 standard for binary floating-point arithmetic to include specifications for decimal floating-point arithmetic and IBM recently announced incorporating a decimal floatingpoint unit into their POWER6 processor. As processor support for de... View full abstract»

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  • A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design

    Publication Year: 2007, Page(s):69 - 76
    Cited by:  Papers (15)  |  Patents (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This paper proposes a new architecture for the MAF unit that supports multiple IEEE precisions multiply-add operation (AtimesB+C) with Single Instruction Multiple Data (SIMD) feature. The proposed MAF unit can perform either one ... View full abstract»

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  • P6 Binary Floating-Point Unit

    Publication Year: 2007, Page(s):77 - 86
    Cited by:  Papers (14)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a technology independent measure. For most dependent instructions, its fused multiply-add dataflow has only 6 effective pipeline stages. This is nearly equivalent to its predecessor, the Power 5, even though its technology inde... View full abstract»

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  • Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell

    Publication Year: 2007, Page(s):87 - 96
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    This paper presents the detailed design of the ARM VFP11 divide and square root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit recurrence algorithm, and this paper describes a novel acceleration technique employed to achieve the required processor clock frequency of up to 750 MHz in 90 nm CMOS. Logical effort theory is used to provide a delay ana... View full abstract»

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  • An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation

    Publication Year: 2007, Page(s):97 - 104
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (221 KB) | HTML iconHTML

    In this paper, we propose a modified etaT pairing algorithm in characteristic three which does not need any cube root extraction. We also discuss its implementation on a low cost platform which hosts an Altera Cyclone II FPGA device. Our pairing accelerator is ten times faster than previous known FPGA implementations in characteristic three. View full abstract»

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  • An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2)

    Publication Year: 2007, Page(s):105 - 112
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (182 KB) | HTML iconHTML

    An algorithm for inversion in GF(2m) suitable for implementation using a polynomial multiply instruction on GF(2) is proposed. It is based on the extended Euclid's algorithm. In the algorithm, operations corresponding to several contiguous iterations of the VLSI algorithm proposed by Brunner et al. is represented as a matrix. They are calculated at once through the matrix efficiently by... View full abstract»

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  • Asymmetric Squaring Formulae

    Publication Year: 2007, Page(s):113 - 122
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (190 KB) | HTML iconHTML

    We present efficient squaring formulae based on the Toom-Cook multiplication algorithm. The latter always requires at least one non-trivial constant division in the interpolation step. We show such non-trivial divisions are not needed in the case two operands are equal for three, four and five-way squarings. Our analysis shows that our 3-way squaring algorithms have much less overhead than the bes... View full abstract»

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  • Spectral Modular Exponentiation

    Publication Year: 2007, Page(s):123 - 132
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    We describe a new method to perform the modular exponentiation operation, i.e., the computation of c = me mod n, where c, m, e and n are large integers. The new method uses the discrete Fourier transform over a finite ring, and relies on new techniques to perform multiplication and reduction operations. The method yields efficient and highly parallel architectures for hardware realizati... View full abstract»

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  • Worst Cases of a Periodic Function for Large Arguments

    Publication Year: 2007, Page(s):133 - 140
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    One considers the problem of finding hard to round cases of a periodic function for large floating-point inputs, more precisely when the function cannot be efficiently approximated by a polynomial. This is one of the last few issues that prevents from guaranteeing an efficient computation of correctly rounded transcendentals for the whole IEEE-754 double precision format. The first non-naive algor... View full abstract»

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  • How to Ensure a Faithful Polynomial Evaluation with the Compensated Horner Algorithm

    Publication Year: 2007, Page(s):141 - 149
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    The compensated Horner algorithm improves the accuracy of polynomial evaluation in IEEE-754 floating point arithmetic: the computed result is as accurate as if it was computed with the classic Horner algorithm in twice the working precision. Since the condition number still governs the accuracy of this computation, it may return an arbitrary number of inexact digits. We address here how to compute... View full abstract»

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  • Accurate Multiple-Precision Gauss-Legendre Quadrature

    Publication Year: 2007, Page(s):150 - 160
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (394 KB) | HTML iconHTML

    Numerical integration is an operation that is frequently available in multiple precision numerical software packages. The different quadrature schemes used are considered well studied but the rounding errors that result from the computation are often neglected, and the actual accuracy of the results are therefore seldom rigorously proven. We propose an implementation of the Gauss-Legendre quadratu... View full abstract»

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