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ASIC, 1996., 2nd International Conference on

Date 21-24 Oct. 1996

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Displaying Results 1 - 25 of 115
  • Proceedings of 2nd International Conference on ASIC

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  • Author index

    Page(s): 444 - 447
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    Freely Available from IEEE
  • Using the C language to reduce the design cycle of an MPEG-2 video IC: a case study

    Page(s): 364 - 367
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    Designing a very large chip requires very long simulation time. For example, to simulate an MPEG-2 video decompression circuit using the Verilog simulator on a top-of-the-line workstation (using Ross 150 MHz CPU with 256 MB memory) takes 24 hours to produce one frame (704×480) of data. One minute worth of video will need 5 years of Verilog time. Facing this impossibility, we adopted a methodology in which a hardware model of MPEG described in the C language is developed in parallel with the HDL design. Cross verification of the C and the HDL descriptions led to increased confidence. Eventually, simulation was driven by the C description: the C model was used to screen MPEG-2 bitstreams and to identify new test cases for Verilog simulation. The reduction of simulation time makes the design cycle manageable View full abstract»

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  • A chip architecture for 2.048 Mbits/s PDH/SDH mapping/desynchronisation

    Page(s): 163 - 166
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    In this paper, a chip architecture for PDH/SDH multiplexing/demultiplexing is presented, including mapping/desynchronisation and the 1+1 protection transmission/reception. The one-step mapping scheme is used to insert/extract 21 tributary units of 2.048 Mbits/s directly into/from STM-1 frame. The time slot a VC-12 occupies in C-4 can be programmed by an external CPU. Programmable control mechanism allows the user to have a leaking period up to 34952 multi-frames and an error of 0.0167UI only at low end desynchronisation output View full abstract»

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  • Aliasing probability of hybrid linear feedback signature registers

    Page(s): 388 - 391
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    Signature analysis techniques that use linear feedback shift register attract increasing attention in the field of IC testing. This paper shows the linkage between aliasing probability of hybrid design LFSR's and its own cycling sequences. We give the condition that the aliasing probability on a single input of hybrid type LFSR approaches a value greater than 2-n. Finally, we point out that the probabilistic behaviors of hybrid design of LFSR's and the normal design are the same under primitive realization View full abstract»

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  • Bi-directional 3-port ATM CAM supporting fast look-up and reduced cycle time

    Page(s): 159 - 162
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    This paper presents an architecture of a bi-directional 3-port ATM CAM. It satisfies one of the fundamental requirements that ATM cell header translation has to be performed in real time. It also reduces the access cycle time to get a retrieval header and reduces the header converted as a result of the match processing. The proposed architecture is composed of three access ports. Each port operates independently of each other. To realize this 3-port function, a bit architecture based on the presented requirements of the functional ATM CAM is proposed. Using such a bit architecture, an architecture of CAM part which includes each module for GFC, VPI, VCI, and PTI field, is also proposed. To provide bi-directional translation of VPI/VCI, two CAM architectures for receiving and transmitting directions are used in each block respectively. The two CAMs reciprocate their matching addresses and the data corresponding to the addresses. It provides control cell extraction such as OAM, unassigned, and physical layer cells. It optionally provides 3-byte tagging for cell switching function for both UNI and NNI modes View full abstract»

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  • Power management in high-level design

    Page(s): 357 - 363
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    Power is significant concern for any application that distinguishes itself by battery life (e.g., pagers, cellular phones, etc.), but this is not the only power sensitive market. Power management is just as critical for today's ASIC and IC designers in nearly every market segment. Consider the following: Increased power increases electromigration and reduces reliability in long-life-cycle telecom products. Adding heat sinks or moving from plastic to ceramic packaging significantly increases the cost per unit in high volume' chips. In deep-submicron design, increasing complexity and higher clock frequencies result in higher power consumption. There are many opportunities in the design process for designers to reduce power consumption. Following is an overview of how designers can reduce power consumption throughout the design process using power analysis and optimization View full abstract»

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  • Enhancing ASICs reliability through the use of fault secure fail-safe multiplexer

    Page(s): 368 - 371
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    In order to achieve the design of state-of-the-art high-safety systems implemented in ASICs, we must incorporate totally self-checking (TSC) functional blocks, totally self-checking checkers, error-indicators and fail-safe interfaces. This paper presents a design and implementation of a fault secure fail-safe multiplexer. The proposed multiplexer is constructed using a reliable fail-safe interface as basic building block that combines the checker function, the error-indication and the fault-tolerant output controller into one functional block View full abstract»

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  • A dual token ring and Ethernet LAN interface chip

    Page(s): 167 - 170
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    A CMOS LAN interface chip that combines the physical layer functions for both the token ring and Ethernet networks is described. The 4/16 mbps Token Ring interface exceeds the jitter tolerance (0.5 ns/UI) and accumulated phase slope (0.25 ns/UI) requirements at 16 Mbps of the IEEE 802.5 draft standard for STP/UTP transmission media. The 10 Mbps Ethernet interface supports both the AUI and 10BaseT functions of the IEEE 802.3 standard View full abstract»

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  • The algorithm design in the field of structure optimization of logic synthesis

    Page(s): 85 - 88
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    This paper discusses the algorithm design for a special type of structure optimization in the field of logic synthesis. The data structure used inhere is a kind of directed graph. We'll give the algorithm framework on the basis of analysis and comparison. A substantial logic network used as input data can demonstrate the efficiency and the feasibility of the software programmed in this algorithm View full abstract»

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  • O2ADL: an object-oriented analog VLSI design language

    Page(s): 27 - 30
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    Object technology can be applied to analog VLSI design to exploit circuit compositional hierarchy, design process hierarchy and design module reuse. Conventional object-oriented programming languages are not suitable for such application due to the difficulties in describing VLSI circuit behaviour, modelling design technology/process hierarchy, implementing class name sharing and dynamically configuring design database. To overcome these difficulties, we have developed an object-oriented analog VLSI design language which provides a set of high-level constructs to conveniently describe and design VLSI circuits. A number of new concepts have been introduced in O2ADL and a dynamic-and-selective inheritance algorithm has been developed to model the design technology/process, to reduce the size of the design database and to achieve code sharing and reusability View full abstract»

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  • A systolic linear array for modular multiplication

    Page(s): 171 - 174
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    In this paper, a novel systolic, linear-array modular multiplier is presented which ideally performs the algorithm of P.L. Montgomery (1985). The total execution time for an n-bit modular multiplication is 4n+1 cycles. With only one full adding in one pipeline stage and the purely nearest neighbor communication, it can operate at a high clock frequency. On the other hand, every processing element is simple, mainly consisting of one full adder and five flip-flops. For n-bit modular multiplication, the cost of implementation is 29n gates. So our designed systolic array for modular multiplication is a speed and area efficient system suitable for the VLSI implementation of modular exponentiation which is a kernel operation used in many public-key cryptosystems such as RSA. With clock frequency of 200 megahertz which is practical in 0.8 μm CMOS processing, the throughput can be 64k bits per second View full abstract»

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  • A special purpose parallel processing ASIC for the first-level calorimeter trigger for the ATLAS detector

    Page(s): 344 - 347
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    Modern high energy physics experiments require massively parallel special purpose computers (triggers) to reduce the extremely large primary data flow to manageable amounts. We present a prototype processing ASIC intended as the basic computational unit in a first-level calorimeter trigger for the ATLAS collider detector to be built at CERN, Switzerland. The proposed trigger is a compact highly parallel pipelined system with 4096 systolic processors partitioned into 256 weakly-interacting custom-designed ASICs. Local results from these ASICs are then merged by a second, less complex type of ASIC. Data is received at 800 Mbit/s by bipolar input circuits, while the processing is performed in CMOS at 320 MHz, using the true single phase clocking scheme (TSPC). This method promotes fast and compact implementations well suited for pipelined bit-serial applications. A 0.5 μm BiCMOS process with 4 metal layers was chosen for the implementation View full abstract»

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  • On fast exploration of ASIC design space

    Page(s): 96 - 99
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    Ever-increasing microelectronics technology and market drive the ASICs more and more complex. Design space exploration become a crucial problem in high level synthesis. In this paper, an efficient precedence bipartite model and algorithms is proposed to explore the large design space. Experimental results show that with this model both the efficiency and the performance of synthesizing large digital system are greatly improved View full abstract»

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  • BiCMOS gate array circuits

    Page(s): 333 - 335
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    BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 μm BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns. BiCMOS 500 gate array circuits are optimized and 2000 gate array circuits are designed. The delay time of BiCMOS is less than CMOS with large load capacitance View full abstract»

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  • VLSI implementation of the SS7 TCAP

    Page(s): 66 - 68
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    The Transaction Capabilities Application Part (TCAP) is the most recent addition to the Signaling System Number 7 (SS7), an open-ended common channel signaling standard that can be used over a variety of digital circuit-switched networks, in particular, ISDN. In this paper, we present an efficient VLSI implementation of TCAP that was obtained using state-of-the-art logic design and verification tools View full abstract»

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  • A generic convolutional code Viterbi decoder generator

    Page(s): 206 - 209
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    This paper presents a unified branch metric calculation method and a unified path-metric update scheduling algorithm to realize the Viterbi decoding process for decoding rate=1/2 convolutional codes. By using punctuation, the proposed algorithm can be extended to decode convolutional codes of any rate. With consideration of the tradeoffs between performance and hardware cost, one can also select different architectures toward different design objectives by specifying the number of processors being used, which results a fully-parallel, fully-serial, or a parallel-serial mixed architecture View full abstract»

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  • A novel VLSI design for survivor memory unit in Viterbi decoder

    Page(s): 127 - 130
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    Since Viterbi Decoder (VD) plays an important role in the realization of HDTV and other digital systems, many efforts have been made on the research and development of the integration of VDs. Survivor Memory Unit (SMU) is one of the three major units which consist of a Viterbi decoder. A novel VLSI approach for realizing SMU differing from the traditional technique is proposed in this paper. A rate=4/5, v=3, L=15, 32 QAM Viterbi decoder with this new structure has been designed and passed the computer simulation View full abstract»

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  • Self-timed Booth's multiplier

    Page(s): 280 - 283
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    This paper presents some methods to improve the performance of an asynchronous system. Firstly, the structure of micropipeline, 2-phase and 4-phase handshake control protocol, asymmetrical delay element and delay selection circuit are discussed. Then we demonstrate how to use these circuit techniques to design the self-timed 8×8 Booth's multiplier. The performance of the circuit using these improvement techniques and different handshake control protocols are discussed and compared View full abstract»

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  • A 2 K-gate high performance merged complementary BiCMOS gate array

    Page(s): 306 - 309
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    Using high performance merged complementary BiCMOS circuit structure, a 2 K-gate BiCMOS gate array master slice and its unit cell library have been designed and created by 2 μm rules. On this master slice, a double 64 bits high speed shift register has also been customized. An internal gate delay of the gate array is 0.65 ns (typical). The operating frequency of the custom IC is more than 100 MHz View full abstract»

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  • Automatic energy-saving switch ASIC CTH945

    Page(s): 313 - 316
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    CTH945 is an mixed analog-digital CMOS LSI with a gain-variable low-noise OPA and 6-class switched capacitor band-pass filter, which uses a new type of unit circuit specially designed for the ASIC. It is mainly used in automatic energy-saving switch and warning devices View full abstract»

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  • A 2.4 kbps MBE-LPC speech codec algorithm suitable for VLSI implementation

    Page(s): 143 - 146
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    A speech code/decode algorithm which combines MBE and LPC speech model is proposed. In this model, the spectral envelope is represented using Linear Prediction Coefficients, which are coded using Line Spectrum Frequencies (LSFs). It can operate at 2.4 kbps with much higher quality of synthesised speech than LPC-10e and less computation complexity than CELP, VSELP and so on. Therefore it is particularly attractive for VLSI implementation View full abstract»

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  • Timing verification for two-phase, level-clocked synchronous circuitry

    Page(s): 31 - 34
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    Because the performance requirements of synchronous circuits are higher, many two-phase, level-clocked circuits are designed. Unlike edge-triggered circuits, two-phase and level-clocked circuits must satisfy more complex timing constraints. In the paper, a novel timing verification algorithm is proposed based on the dynamic programming algorithm and is used to performed on some synchronous circuits View full abstract»

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  • P+P: parallel pattern and parallel fault simulator for synchronous sequential circuit

    Page(s): 380 - 383
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    This paper describes P+P, a fast fault simulator for synchronous sequential circuits. P+P uses parallel patterns in good machine simulation (GMS) and parallel faults in faulty machine simulation (FMS). In addition, P+P features several new techniques, such as global circuit levelization, cone operation, global fault grouping, levelized events and improved ID etc., in order to increase performance. The algorithm is realized on SUN SPARC-2 with random patterns. P+P runs on most of the ISCAS benchmark circuits. These experiments show that P+P is much faster than primary P+P algorithm View full abstract»

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