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21-24 Oct. 1996

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Displaying Results 1 - 25 of 115
  • Proceedings of 2nd International Conference on ASIC

    Publication Year: 1996
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    Freely Available from IEEE
  • Structured Methods Applied to CAD Design Flows

    Publication Year: 1996, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB)

    First Page of the Article
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  • Author index

    Publication Year: 1996, Page(s):444 - 447
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    Freely Available from IEEE
  • CMP services: basic principles and developments

    Publication Year: 1996, Page(s):417 - 420
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    This paper is about the CMP Service (Circuits Multi-Projects). CMP aims at providing Universities, Research Laboratories and Industries with the possibility to have their integrated circuits projects fabricated. The Service has started in 1981. Presently customers are serviced for CMOS, BiCMOS, bipolar and GaAs technologies, and for Multi Chip Module fabrication. Recently, the Service has been ext... View full abstract»

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  • ASAP: an asynchronous array processor for hardware-software coprocessing and codesign

    Publication Year: 1996, Page(s):151 - 154
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Traditional field programmable gate arrays (FPGAs) originate and are used to prototype digital designs. Recently, there has been increasing interest in using FPGAs as attached systems for hardware-software coprocessing and codesign. However, existing FPGAs on the market all implement general purpose logic designs. They are not well defined for the coprocessing and codesign purpose. In this paper, ... View full abstract»

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  • Combinational ATPG acceleration by dynamic circuit partition

    Publication Year: 1996, Page(s):413 - 416
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    If no FOS exists in the circuit under test, the execution time of DTM and STM linearly increase proportional to circuit size. The non-linear factors in the algorithm are introduced by FOSs. To limit the affection of FOS's as small as possible, a technique called Dynamic Search Space Reduction is introduced in this paper and only the FOSs who have more then two branches in the sensitive region have... View full abstract»

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  • Design of a digital speech processor

    Publication Year: 1996, Page(s):147 - 150
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    This paper describes the design of a flexible hardware structure called Digital Speech Processor (DSP), which is the core module of implementing several code-excited linear prediction (CELP) algorithms such as IS-96, IS-54, RCR-27, G.728, etc. In China, there are a lot of communication systems being used, therefore, it is very difficult to determine a common speech coding algorithm, instead, many ... View full abstract»

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  • ASIC design considerations for address vector generation in memory test system

    Publication Year: 1996, Page(s):409 - 412
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    In this paper an application-specific integrated circuit (ASIC) is presented for the generation of address vector of memory test system View full abstract»

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  • A 2.4 kbps MBE-LPC speech codec algorithm suitable for VLSI implementation

    Publication Year: 1996, Page(s):143 - 146
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A speech code/decode algorithm which combines MBE and LPC speech model is proposed. In this model, the spectral envelope is represented using Linear Prediction Coefficients, which are coded using Line Spectrum Frequencies (LSFs). It can operate at 2.4 kbps with much higher quality of synthesised speech than LPC-10e and less computation complexity than CELP, VSELP and so on. Therefore it is particu... View full abstract»

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  • Generalised Reed-Muller ASIC converter

    Publication Year: 1996, Page(s):73 - 76
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The paper outlines the design of a new IC for bi-directional conversion between the functional and operational domains of logic functions. The circuit can generate all fixed polarities of Generalised Reed-Muller expansions for a given Boolean expression. Since all polarities are computed simultaneously, they may be compared to find the optimal polarity of the logic function. Further, the chip can ... View full abstract»

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  • Analog design-for-testability for analog/mixed-signal ASICs

    Publication Year: 1996, Page(s):404 - 408
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    This paper discusses the concept and issues of Analog Design-for-Testability (ADFT) for analog/mixed-signal ASICs, and describes an algorithm for selecting the accessible nodes for excitation, a scheme for simplifying the ADFT with using of the macro-model circuit instead of the original circuit of the analog macros for including in ASIC chips, an architecture for a practically testable mixed-sign... View full abstract»

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  • A novel VLSI transform kernel based on fast rotation

    Publication Year: 1996, Page(s):138 - 142
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    This paper presents a new VLSI transform kernel which can perform non-overlapped and overlapped, orthogonal and biorthogonal transforms of any reasonable dimension. The architecture is based on a new fast recursive transform decomposition algorithm involving fast rotation only. As a result, a highly regular structure is achieved with a minimum of control overhead. The fast recursive transform deco... View full abstract»

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  • BiCMOS gate array circuits

    Publication Year: 1996, Page(s):333 - 335
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 μm BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns. BiCMOS 500 gate array circuits are optimized and 2000 gate array circuits are designed. The delay time o... View full abstract»

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  • ASICs design for an MTD radar

    Publication Year: 1996, Page(s):69 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    In an MTD (Moving Target Detect) radar, the digital signal processing is implemented by some real-time processing pipelines which consist of ASICs and FIFO or dual-port memory. We designed six ASICs with Xilinx FPGA, including the clutter-map unit former, the moving target signal extractor, the video signal integrator and the CFAR (Constant False Alarm Rate) operator. While all the timing and cont... View full abstract»

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  • Analog integrated circuit parameter fault diagnosis using artificial neural network

    Publication Year: 1996, Page(s):400 - 403
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    An artificial neural network method used for analog IC parameter fault diagnosis is presented in this paper. It is fast and accurate. Therefore it has boundless prospects in the field of analog IC parameter fault diagnosis. With the rapid development in IC technology, the fault diagnosis problem of analog IC has become more acute. The traditional methods' computation complexity and inaccuracy of r... View full abstract»

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  • ISP solution for radar video processing: resolution improvement and side-lobe cancellation

    Publication Year: 1996, Page(s):53 - 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    A navigation radar video processing algorithm is implemented, which can improve both range and bearing resolution by 20% and reduce side-lobe level by 6 dB or more, theoretically. An In-System Programmable (ISP) HDPLD (or CPLD) design scheme is given along with logic details and timing analysis View full abstract»

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  • Research on ASIC for multi-speaker isolated word recognition

    Publication Year: 1996, Page(s):135 - 137
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    The ASIC for multi-speaker speech recognition is design in this paper. The LPC-derived cepstral coefficients are chosen as speech features. Templates are trained by K-means clustering algorithm. Two stage recognition system can not only improve recognition accuracy, but also reduce the delay. The first stage of recognition system uses speech spectrum difference (SSD) algorithm. The second stage us... View full abstract»

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  • A full-parallel architecture ASIC implementation of FP-based multilayered feedforward neural networks

    Publication Year: 1996, Page(s):329 - 332
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    This paper describes an approach to the ASIC implementation of a multilayered feedforward neural network. Based on a new learning algorithm (Forward Propagation Algorithm), our system realizes a real full-parallel architecture and allows all of the neurons to work parallelly and independently. Hardware cost is greatly reduced and the network is easy to expand. The current results of our implementa... View full abstract»

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  • Practical solutions for scan design

    Publication Year: 1996, Page(s):384 - 387
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    This paper discusses structure of system clocks in circuits, and points out effective methods for scan design. Using these methods we can easily achieve testable design for synchronistic circuits View full abstract»

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  • On fast exploration of ASIC design space

    Publication Year: 1996, Page(s):96 - 99
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Ever-increasing microelectronics technology and market drive the ASICs more and more complex. Design space exploration become a crucial problem in high level synthesis. In this paper, an efficient precedence bipartite model and algorithms is proposed to explore the large design space. Experimental results show that with this model both the efficiency and the performance of synthesizing large digit... View full abstract»

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  • The design of high-speed sigma-delta modulator

    Publication Year: 1996, Page(s):248 - 251
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    The design for high speed ΣΔ modulator is discussed, Comparison between current-mode and switched-capacitor ΣΔ modulator performance is given. Fast-speed CMOS amplifier and comparator are designed to implement the circuit. In 1.08 μm CMOS process current-mode ΣΔ modulator achieves 100 MHz sampling rate View full abstract»

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  • Using the C language to reduce the design cycle of an MPEG-2 video IC: a case study

    Publication Year: 1996, Page(s):364 - 367
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Designing a very large chip requires very long simulation time. For example, to simulate an MPEG-2 video decompression circuit using the Verilog simulator on a top-of-the-line workstation (using Ross 150 MHz CPU with 256 MB memory) takes 24 hours to produce one frame (704×480) of data. One minute worth of video will need 5 years of Verilog time. Facing this impossibility, we adopted a method... View full abstract»

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  • VLSI implementation of the SS7 TCAP

    Publication Year: 1996, Page(s):66 - 68
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    The Transaction Capabilities Application Part (TCAP) is the most recent addition to the Signaling System Number 7 (SS7), an open-ended common channel signaling standard that can be used over a variety of digital circuit-switched networks, in particular, ISDN. In this paper, we present an efficient VLSI implementation of TCAP that was obtained using state-of-the-art logic design and verification to... View full abstract»

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  • System level test generation and fault simulation for VLSI circuits

    Publication Year: 1996, Page(s):396 - 399
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    This paper presents a new concept in VLSI test domain: System Level Test Generation and Fault Simulation. In the paper, we describe the process of VLSI circuit design, discuss abstraction of information processed by the circuit, and address the outline of system level test generation and fault simulation View full abstract»

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  • An interface ASIC design using FPGA

    Publication Year: 1996, Page(s):224 - 227
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    An interface ASIC chip for smart stream tape recorder has been designed using CMOS gate array technology. It is realized by XILINX FPGA, and has good performance in a 1/4 inch stream tape recorder View full abstract»

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