21-24 Oct. 1996

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Displaying Results 1 - 25 of 115
  • Proceedings of 2nd International Conference on ASIC

    Publication Year: 1996
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    Freely Available from IEEE
  • Structured Methods Applied to CAD Design Flows

    Publication Year: 1996, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB)

    First Page of the Article
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  • Author index

    Publication Year: 1996, Page(s):444 - 447
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    Freely Available from IEEE
  • Design and analysis of loop code recognition circuits

    Publication Year: 1996, Page(s):187 - 190
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    This paper introduces the design of some circuits that can recognize loop code from an input code stream. The loop code in the stream can be arbitrary or a template specified by the user. We especially discuss the design method of these circuits, along with some simulation results View full abstract»

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  • Digital correlator EPLD design

    Publication Year: 1996, Page(s):183 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    This paper begins with the imperativeness of applying EPLD technique to digital correlator design of communication systems. On this basis, it explains the relative technical problems existing in the EPLD design of a digital correlator, analyses the hardware resource provided by EPLD and gives a description of an example of design as well as relevant test results. It concludes with several suggesti... View full abstract»

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  • Design a pocket multi-bit multiplier in FPGA

    Publication Year: 1996, Page(s):275 - 279
    Cited by:  Patents (60)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The multi-bit multiplier is an arithmetic unit which is often used in digital electronic systems and digital signal processors. There are two kinds of algorithm for performing multi-bit multiplication. According to the algorithm given in the paper, two kinds of simple multi-bit multiplier are introduced. Dealing with the structure of the combinational multiplier and sequential multiplier, the pape... View full abstract»

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  • An SDH STM-1 termination IC

    Publication Year: 1996, Page(s):179 - 182
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    The STM-1 termination IC receives and transmits Synchronous Digital Hierarchy (SDH) STM-1 signals. In addition to STM-1 frame generation and frame alignment, the chip parallelly scrambles and descrambles the STM-1 signal, provides pointer generation and interpretation, and performs payload insertion and recovery. Section and path overheads are extracted and inserted, alarm signals are detected and... View full abstract»

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  • A novel VLSI design for survivor memory unit in Viterbi decoder

    Publication Year: 1996, Page(s):127 - 130
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    Since Viterbi Decoder (VD) plays an important role in the realization of HDTV and other digital systems, many efforts have been made on the research and development of the integration of VDs. Survivor Memory Unit (SMU) is one of the three major units which consist of a Viterbi decoder. A novel VLSI approach for realizing SMU differing from the traditional technique is proposed in this paper. A rat... View full abstract»

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  • Fast and robust CMOS double pipeline using new TSPC multiplexer and demultiplexer

    Publication Year: 1996, Page(s):271 - 274
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    New multiplexer and demultiplexer are proposed for a fast and robust CMOS double pipeline, based on new TSPC latches. The speed bottlenecks of the CMOS double pipeline are consequently removed and the critical delays are reduced by a factor of two approximately. The input latching window is widened significantly by reducing the input hold times. The robustness of the double pipeline is thus improv... View full abstract»

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  • Designing a Twinax communication circuit

    Publication Year: 1996, Page(s):175 - 178
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    This paper describes the design and FPGA implementation of a Twinax communication circuit. It is designed to interface with IBM's local Twinax protocol, and is hardware compatible with IBM Enhanced 5250 Emulation Adapter Card. This circuit is composed of a processor interface unit and two Channel Control Modules (CCM). This paper presents an implementation of a Twinax Communication Adapter Chip wi... View full abstract»

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  • Single chip Chinese teletext decoder

    Publication Year: 1996, Page(s):107 - 110
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    A single chip teletext decoder (Chinatext) for Chinese language is introduced. It is designed using advanced CMOS 4 Megabit DRAM technology. With 4.2 million transistor-count integrated into a single chip, it combines all analog and digital functions required for high quality teletext processing. An on-chip 3.1 Megabit custom designed ROM contains compressed information of more than 7000 GB5007 ch... View full abstract»

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  • P+P: parallel pattern and parallel fault simulator for synchronous sequential circuit

    Publication Year: 1996, Page(s):380 - 383
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    This paper describes P+P, a fast fault simulator for synchronous sequential circuits. P+P uses parallel patterns in good machine simulation (GMS) and parallel faults in faulty machine simulation (FMS). In addition, P+P features several new techniques, such as global circuit levelization, cone operation, global fault grouping, levelized events and improved ID etc., in order to increase performance.... View full abstract»

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  • High speed SDRAM interface circuit

    Publication Year: 1996, Page(s):123 - 126
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    SDRAM is a kind of DRAM with synchronous clock. It has wide applications in the field of image processing. In this paper, we introduce an interface circuit of high speed SDRAM. The speed of the circuit can be 50 MHz. We have verified the circuit by FPGA (Xilinx 3195A-2 PQ208) View full abstract»

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  • Design for testability, placement and routing of a new oversampled Σ-Δ modulator

    Publication Year: 1996, Page(s):267 - 270
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    A new top-down design method is proposed in this paper including Verilog hardware description, synthesis, design for testability, library preparation, automatic placement and routing with some artificial interference using a new oversampled Σ-Δ modulator as an example. A theorem is also introduced for DFT consideration View full abstract»

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  • A systolic linear array for modular multiplication

    Publication Year: 1996, Page(s):171 - 174
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    In this paper, a novel systolic, linear-array modular multiplier is presented which ideally performs the algorithm of P.L. Montgomery (1985). The total execution time for an n-bit modular multiplication is 4n+1 cycles. With only one full adding in one pipeline stage and the purely nearest neighbor communication, it can operate at a high clock frequency. On the other hand, every processing element ... View full abstract»

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  • Top-down design for 32-bit RISC core

    Publication Year: 1996, Page(s):104 - 106
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    This paper is to introduce the 32-bit RISC IU chip LC47811. It was designed and fabricated in China last year. It is designed as the core of embedded microcontrollers for future applications. The design of RISC chip started at RTL level with Top-Down methodology in June 1995, we generated the gate-level net-list by logic synthesis and complete the layout by automatic place and route on COMPASS in ... View full abstract»

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  • Testing techniques for embedded memories in ASIC

    Publication Year: 1996, Page(s):376 - 379
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    This paper provides a survey of four practical testing techniques for embedded memories in ASIC in industry. The pros and cons of these techniques are studied in terms of area, timing, power, pin count, automation, test speed, test quality and chip testing View full abstract»

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  • Low-power consumption architecture for embedded processor

    Publication Year: 1996, Page(s):77 - 80
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    A low-power processor architecture is described dedicatedly for embedded application programs by means of an object code compression approach. This approach unifies duplicated instructions existing in the embedded program and assigns a simple number to each distinct instruction. An instruction decompressor is constructed in an embedded processor, which is to generate an object code from a compress... View full abstract»

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  • Power consumption of static and dynamic CMOS circuits: a comparative study

    Publication Year: 1996, Page(s):425 - 427
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The choice of technology to be used for the implementation of a given specification is usually dependent on the optimization and the performance constraints that the finished chip is required to meet. When the target is low-power dissipation, one of the decisions that the designer has to take concerns the use of static versus dynamic CMOS transistors. Although, from the theoretical stand-point, th... View full abstract»

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  • SimP: a core for FPLD-based custom-configurable processors

    Publication Year: 1996, Page(s):197 - 201
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Standard building blocks play a very important role in the use of new semiconductor technologies such as field programmable logic devices (FPLDs). New design methodologies, that will increase designer productivity and the general quality of design, are necessary in order to use the power of FPLDs especially in embedded applications. One of the promising methods is the merging of the hardware and s... View full abstract»

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  • VLSI design for a new adaptive image compress coding

    Publication Year: 1996, Page(s):119 - 122
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    This paper presents a new adaptive classified image coding which combine the high-compression ratio of vector quantization and edge-preserving ability of BTC. The VLSI design for this algorithm is described too. In our design, the parallel-pipeline architecture is adopted for closest codeword searching, and mean absolute error scheme is used as distortion measure in order to reduce the scale of ci... View full abstract»

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  • New efficient design of digital comparator

    Publication Year: 1996, Page(s):263 - 266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    The digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs Manchester chain to fulfil the compare operation. Compared with the static implementations, MCP's highest operating frequency (125 MHz) is much higher. At the same operating frequency, MCP's power dissipation is... View full abstract»

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  • A 500 MS/s 10-bit CMOS D/A converter

    Publication Year: 1996, Page(s):252 - 255
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    This paper presents a low-power high-speed 10-bit D/A converter. The chip is implemented in a 0.45-μm ASIC CMOS technology and active chip area is 0.8 mm by 0.4 mm. Its dc DNL (differential nonlinearity) is within 0.53 LSB. The chip dissipates 60 mW at 500 MS/s with 57 dB spur-free dynamic range. The normalized power consumption is only 120 μW/MHz, while achieving the highest sampling rate e... View full abstract»

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  • Design of a digital speech processor

    Publication Year: 1996, Page(s):147 - 150
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    This paper describes the design of a flexible hardware structure called Digital Speech Processor (DSP), which is the core module of implementing several code-excited linear prediction (CELP) algorithms such as IS-96, IS-54, RCR-27, G.728, etc. In China, there are a lot of communication systems being used, therefore, it is very difficult to determine a common speech coding algorithm, instead, many ... View full abstract»

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  • A dual token ring and Ethernet LAN interface chip

    Publication Year: 1996, Page(s):167 - 170
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A CMOS LAN interface chip that combines the physical layer functions for both the token ring and Ethernet networks is described. The 4/16 mbps Token Ring interface exceeds the jitter tolerance (0.5 ns/UI) and accumulated phase slope (0.25 ns/UI) requirements at 16 Mbps of the IEEE 802.5 draft standard for STP/UTP transmission media. The 10 Mbps Ethernet interface supports both the AUI and 10BaseT ... View full abstract»

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