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Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Date 10-13 Dec. 2006

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Displaying Results 1 - 25 of 354
  • [Front cover]

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  • Copyright page

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  • General and Technical Program Chairs' Message

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  • TPC list

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  • Reviewers list

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  • Track Chair list

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  • Local Organizing Committees

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  • Table of contents

    Page(s): nil12 - nil48
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  • Distributed RLC Interconnect: Analytical Modelling Expressions for Crosstalk Noise Estimation

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (286 KB) |  | HTML iconHTML  

    As the chip dimensions increase with chip complexity, interconnects tend to get longer. With the longer on-chip interconnects coupled with a decrease in wire width and wire separation, inductive coupling effects have become non-negligible. Analytical modelling expressions for the estimation of the noise peak voltage of the victim line under worst-case crosstalk noise effect are presented. View full abstract»

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  • A New RF SiCMOS SDD Model for Quantifying Individual Contribution to Distortion from Transistor's Nonlinear Parameters

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (457 KB) |  | HTML iconHTML  

    This work reports a new implementation of a transistor model aiming to facilitate a closer understanding of nonlinear elements in silicon CMOS transistors operating at high frequencies. Using this model, the contribution of each non linear element to the total distortion of the transistor can be individually quantified using a superposition method. The new model is implemented entirely using symbolically defined devices (SDD) for each nonlinear parameter individually. The transistor used is a foundry 180 nm RF SiCMOS capable of operating up to 10 GHz. The SDD model is validated by examining the behavior of the table-based model against the behavior of the modeled transistor in a single tone sweep test from very small input powers up to deep in compression. This work was carried out using Agilent advanced design systems tool (ADS). View full abstract»

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  • Noise Modeling For Charge Amplification and Sampling

    Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (315 KB) |  | HTML iconHTML  

    A new cyclostationarity-based analytical model for noise analysis of a charge amplifier followed by a correlated double sampling (CDS) circuit is proposed. It determines output noise (power spectral density and squared voltage) resulting from input noise voltages and currents. Model validation is performed by comparing the obtained results with those of temporal noise simulations. This model allows analysis of consequences of CDS and integration duration on noise contributions. It predicts that CDS does not suppress or attenuate effect of input current sources. In the case of 1/f input noise current, the SNR can not be improved by increasing the integration duration. View full abstract»

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  • General Model for the Deployment of Time-Delay Elements in Transistorized Electronic Circuits

    Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (787 KB) |  | HTML iconHTML  

    This paper presents a general model for the analysis of time-delay contributions due to right half plane (RHP) zeros in circuit's transfer functions. The presence of these RHP zeros is in general associated to Miller capacitances. These can be explored as a means of implementation of delay elements. A general discussion on the usage of these RHP zeros as means of designing usable delay cells is addressed, including several parasitic effects that may arise in practical implementations. The model is then verified recurring to simulation experiments. View full abstract»

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  • Multiconductor Transmission Lines Sensitivity via Two-Dimensional Laplace Transform

    Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7275 KB) |  | HTML iconHTML  

    The paper deals with a non-traditional method for determination of sensitivities of voltage and/or current waves propagating down multiconductor transmission lines (MTLs). The main idea is to use a two-dimensional Laplace transform (2D-LT) to replace the originally partial differential equations describing the uniform MTLs in the (x, t)-domain with those of algebraic type in the (q, s)-domain. The 2D Laplace transform can be much easily treated as for the sensitivity with respect to the MTLs' per-unit-length matrix parameters. After the (q, s)-domain sensitivity assessment the two-dimensional numerical inversion of Laplace transforms (2D-NILT) method is applied to get the sensitivities in the (x, t)-domain. Boundary conditions incorporation is performed by using modified nodal analysis (MNA) method in the s-domain when one-dimensional Laplace transform (1D-LT) is applied. All the computations have been programmed in the Matlab language. View full abstract»

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  • Design and Analysis of A Class-E Frequency-Controlled Transcutaneous Energy Transfer System

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (237 KB) |  | HTML iconHTML  

    This article introduces a frequency-controlled transcutaneous energy transfer system as well as a particular circuit structure for it. The analysis method, design and realization of this system are studied and its performance evaluation based on the simulations and experimental results of a prototype circuit is carried out. The simplicity of the required hardware as well as the high performance and reliability are among the attractive features of the proposed system. View full abstract»

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  • Multiparameters monitoring for long term in-vivo characterization of electrode-tissues contacts

    Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2218 KB) |  | HTML iconHTML  

    This paper concerns the design of an integrated circuit (IC) dedicated to monitor electrode-tissues contact (ETC). It is the main module of an implantable telemetry device. This device allows one to apply various principles of electrochemical system's studies, such as cyclic voltammetry, electrochemical impedance spectroscopy, galvanostatic double pulse method, and thus, to measure the evolution of various parameters surrarounding the ETC: complex impedance, faradic resistance, double layer capacity, rheobase current and chronaxy time. The circuit has been designed and implemented with the CMOS 0.18 mum technology with an area of 2mm2. The proposed technique and the IC functionalities were validated in our laboratory during in-vitro experimentations. View full abstract»

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  • An Efficient Micro-Stimulator Array Using Unitary-Size DAC With Adiabatic Baseband Scheme

    Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1956 KB) |  | HTML iconHTML  

    This paper presents novel approaches for higher-resolution, higher output gain, better-linearity, and less-power-consumption micro-stimulator array. To achieve higher output gain for more ideal stimulus current without extra cascode stage, a gain-boosting design is adopted. To achieve higher-resolution and better linearity, a continuous pulse-width modulation-based conversion architecture has been proposed. To overcome extra power consumption of the baseband control logic, the energy recovery scheme is also applied. A monolithic circuitry of this efficient stimulator array has been realized by using TSMC 0.18-mum 1P6M standard CMOS technology and the experimental results show improvement over the prior approaches. View full abstract»

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  • Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem

    Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1989 KB) |  | HTML iconHTML  

    In most of bioimplantable or wireless sensor network systems, ASK is one of the most commonly used schemes to modulate the baseband signal with reference to the intermediate or even the carrier frequency. In this study, a novel demodulator architecture is proposed. It is based on a simple self-sampling scheme which is a truly low-cost high-efficiency implementation and has excellent ability to work on a very small difference (0.15 V) between the two modulated levels, which represent the binary '0' and '1' separately. The results show the presented type can be designed to fit the operation carrier for the special need and has a quite area efficiency than the ever published similar works due to its existent digital benefit. In addition, a comforting robustness is also demonstrated under different process variations. According to the merits mentioned above, both the chip cost and the complexity in the design of on-chip voltage regulator for stable DC extraction are greatly reduced. This design has been verified and realized by using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-mum 1P6M standard CMOS technology. View full abstract»

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  • Comparison of Transconductance Reduction Techniques for the Design of a Very Large Time-Constant CMOS Integrator

    Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (944 KB) |  | HTML iconHTML  

    This paper compares three transconductance (gm) reduction techniques in terms of analog mismatch and total achievable amount of gm reduction. The techniques investigated are current division, current cancellation, and cascade of gm-1/gm stages. Each of these is applied to the design of a very long time-constant integrator for use in a neural recording bladder control implant. Extensive Monte-Carlo simulations in a 0.35mum CMOS process showed that for the target gm of about 50 pA/V, the current division technique is the best option as it is insensitive to analog mismatch when used in closed-loop configuration. The achievable gm with the current cancellation technique is limited to about 65 nA/V, whereas the cascade of gm-1/gm stages is extremely sensitive to DC offsets. View full abstract»

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  • Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers

    Page(s): 41 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2444 KB) |  | HTML iconHTML  

    This paper presents an overview of recent developments in continuous-time sigma-delta modulator design. Traditionally, sigma-delta modulators have been used for audio applications with low bandwidth and high-resolution requirements. Nowadays, the area of sigma-delta modulation has extended and sigma-delta modulators are widely used in multi-mode communication receivers with different bandwidth and resolution specifications. Thanks to new architectures and the integration of extra functionality, the excellent power efficiency, as well as good scalability, continuous-time sigma-delta modulators are key in enabling highly digitized receivers. View full abstract»

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  • Quadrature Mismatch Shaping with a Complex, Data Directed Swapper

    Page(s): 46 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (406 KB) |  | HTML iconHTML  

    Quadrature bandpass (QBP) SigmaDelta ADCs require a feedback path for both the I and the Q part of the complex feedback signal. A complex DAC could give this feedback with near-perfect I/Q balance. Still, the mismatch between the unit elements of the complex DAC introduces mismatch noise that should be shaped out of the signal band with dynamic element-matching (DEM) techniques. To select the unit DAC elements of the complex multibit DAC, the well-known data directed swapper is generalized towards a complex structure and the necessary constraints for its correct functioning are derived. Additionally, a hardware efficient structure is presented: the reduced butterfly shuffler. Here, some of the QBP swapper cells are replaced by bandpass (BP) swapper cells. Also, great attention is paid to the interconnection pattern of the data directed swapper to prevent instability. View full abstract»

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  • Design of Cascaded Continuous-Time Sigma-Delta Modulators

    Page(s): 50 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1386 KB) |  | HTML iconHTML  

    Cascaded sigma-delta modulators implemented with continuous-time circuits are becoming popular due to its high potential to build high resolution, high bandwidth A/D converters. This paper shows a survey of the recent advances in this field. Architecture selection together with some design aspects are discussed for low oversampling ratio applications. The design of noise cancellation logic and the influence of integrator gain errors are also discussed. Finally some new challenges are proposed for next designs. View full abstract»

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  • Use of the Step Invariant Transform to Design a 2nd Order Continuous Time Complex Sigma-Delta ADC

    Page(s): 54 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1672 KB) |  | HTML iconHTML  

    To reduce simulation times, continuous time (CT) sigma-delta modulators can be modeled as equivalent discrete time (DT) systems so that DT simulators can be used. This method reviews two popular methods of converting from CT to DT and applies them to a second order CT complex ADC. The ADC being designed is for use with a low IF receiver and achieves 80dB SNDR in simulation. View full abstract»

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  • Sigma-Delta Solutions for Future Wireless Handields

    Page(s): 58 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2284 KB) |  | HTML iconHTML  

    This paper addresses the different issues in the design of ADCs for future wireless handhelds. It reviews the constraints imposed on the receiver design by the low-power specifications in handhelds. The sigma-delta ADC architectures that can potentially be used for implementing future wireless handhelds are discussed in the perspective of a CMOS implementation. Finally, a 4th order 4bit continuous-time bandpass sigma-delta modulator capable of digitizing a WiMAX (20 MHz) signal band centered at an IF of 75 MHz is presented. The simulation results shown that the proposed sigma-delta modulator can provide a SNDR of 50.1 dB and a DR of 56 dB at a sampling frequency of 500 MHz. View full abstract»

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