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Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date 27-30 May 2007

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Displaying Results 1 - 25 of 1029
  • It's really a Lagniappe!!

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  • Technical Program Co-Chairs' message

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  • Conference Committee

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  • Technical Program Committee

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  • Review Committee Members

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  • list-reviewer

    Page(s): nil10 - nil23
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  • ISCAS 2007 Keynote Speakers

    Page(s): nil24 - nil26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (170 KB)  

    First Page of the Article
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  • Tutorial 1: Integrated Biosensors

    Page(s): nil27
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    We will present the design and implementation of monolithic and hybrid sensors using integrated circuits, particularly in CMOS. We will begin by providing the definitions and performance metrics of sensors and a brief overview of various noise processes. Subsequently, we will discuss the advantages and shortcomings of sensors built in silicon-based fabrication processes and examine, in detail, their integrated circuit topologies. Next, we will provide a comprehensive study of the design and analysis of CMOS integrated image sensors, integrated biosensors, and electronic backbone of MEMS hybrid sensors. Topics include: silicon photodetectors; CCD and CMOS sensor architectures and circuits; Affinity-based detection and biochemical transduction; optical, electrochemical, and mechanical transducer design; integrated microarrays, biochips, and sensor SoCs. We will conclude with a survey of advanced research topics in the area of integrated sensors such as smart sensors, RF-IDs, and nanosensors. View full abstract»

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  • Tutorial 2: Satellite Navigation Receiver Design: GPS and Beyond

    Page(s): nil27
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    Introduction to the GPS L1 signal: spectrum, modulation and data. How does CDMA work? What are the strengths and weaknesses of the selected satellite codes? - How a position can be calculated using GPS. A brief discussion of the least-squares solution. - Where errors in position come from. What are the six main sources of error and how can they be dealt with? - How a receiver processes the signal to make measurements. Breaks the receiver into subsystems: antenna, RF front end, digital baseband and processor. What activities happen where? - New GPS signals: L2C and L5 - how they differ from L1 and what advantages they bring. The new codes and data have been designed to achieve certain advantages over L1 - how good are they? - New Galileo signals: why are they better? Some elements of the Galileo design are quite radical - what is achieved for instance by the new MBOC modulation? - Challenges for future satellite navigation receiver design. What can be achieved with the new systems and signals? View full abstract»

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  • Tutorial 3: Design of Programmable Wireless Networks aka Cognitive Radios

    Page(s): nil27 - nil28
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    The wide proliferation of wireless services and applications with increasing bandwidth needs is rapidly creating a spectrum shortage. However, the problem is caused primarily by inefficient legacy spectrum allocation policies, so that even when some applications suffer from lack of bandwidth, there is idle capacity in other bands. To deal with this challenge, the FCC, ITU and other regulatory organizations have begun to explore an open spectrum policy implemented by programmable wireless networks. Such wireless networks use cognitive, software reconfigurable radios to increase the efficiency of spectrum access. In particular such programmable wireless networks maximize the availability and enhance the quality of service of diverse applications using the most appropriate access network, or an aggregation of such networks, for any given local conditions. A software defined radio (SDR) terminal is essentially a reconfigurable system that can be dynamically programmed in software to reconfigure the characteristics of the hardware through the use of clearly defined APIs residing on top of a flexible hardware layer. The SDRs use different types of hardware to accomplish various communication tasks. In addition to the programmability and flexibility provided by the DSPs and software-driven communication parameters such as modulation, medium access, cryptography, etc, software defined radios also provide field service capability. So, when requirements change, code downloads, upgrades and modifications are relatively easy to execute. Ultimately, the success of the programmable wireless network vision will hinge on its ability to meet the high level needs of users, service providers, network operators and hardware and software developers. View full abstract»

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  • Tutorial 4: Circuit Techniques for Operational Amplifier Speed and Accuracy Improvement: Analog Circuit Design with Structural Methodology

    Page(s): nil28
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    OpAmp is the main analog building block for both the systems on discrete elements and systems on silicon. The parameters of OpAmp often define and limit the overall system performance. CMOS technology provides an opportunity to use more complex structural solutions and circuit techniques to improve OpAmp accuracy, power/speed ratio, to add new functional advantages, like low voltage supply operation capability or rail to rail input without the switching point, everything for negligible additional component cost. The circuit techniques that will be demonstrated during this course were proven in design of leading industrial OpAmps. These techniques are unified by a common structural design approach, based on the following principles: - system analysis at the high level of abstraction using the graphic tools like signal flow graphs, and generation of the set of equivalent graph modifications, - equivalent graph transformations to the form when every important parameter in the system or the amplifier is controlled by a dedicated feedback loop; - stability of these loops is achieved without compensation capacitors, by using one-stage (preferably current) amplifiers, - system synthesis consists of implementation of the set of the gain structure modifications followed by simulations based on available library of cells, and final selection of the best circuit solutions. View full abstract»

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  • Tutorial 6: Design Challenges and Solutions for Nanoscale Memories

    Page(s): nil28 - nil29
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    Static Random-Access Memory (SRAM) is a dominant memory technology for embedded CMOS-memory applications. As device channel lengths shrink down to tens of nanometers, SRAM designs meet new issues and challenges that require changes in the way designs are done. The goal of the tutorial is threefold: 1. Present the design challenges and summarize various circuit-design techniques for low leakage and high performance memory design; 2. A detailed discussion on SRAM failure mechanisms to understand the impact of process variations, soft errors, leakage and noise on different memory operations; the speakers will reexamine these scaling issues, their impact on cell operation and stability, and design for manufacturability within these constraints; and 3. Discuss future and emerging memory technology trends and what they may mean for low power and robustness concerns - with an emphasis on those aspects that are relevant to SRAM designers. View full abstract»

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  • Tutorial 8: Wireless Sensor Networks: From Theory to Practice

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    Wireless sensor networks combine distributed sensing, computing, and wireless communications into a Powerful technology that offers unprecedented resolution, unobtrusiveness, and autonomous operation for countless applications. At the same time, they offer numerous challenges, in particular the strict energy constraints, the distributed operation, and the scalability. This tutorial provides a comprehensive and self-contained introduction to wireless sensor networks, covering all the relevant aspects from the basic theory to real-world applications. It consists of four parts: 1. Introduction: Motivation, relevance, and important applications 2. Challenges and solutions: Difference to other wireless networks; modelling issues; energy-efficient network protocols; performance limits and quality-of-service issues 3. Practical aspects: Hardware overview; experimental results and measurements. 4. Conclusions and outlook. View full abstract»

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  • Tutorial 12: Challenges and Opportunities of Digital Design in Nanoscale CMOS

    Page(s): nil29
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    This tutorial reviews the challenges and opportunities of high-performance digital design in nanoscale CMOS technologies. The device structure evolution, material enhancement, and major design challenges are discussed. Examples of logic circuit and SRAM design techniques to overcome the challenges and to mitigate various performance/reliability constraints in conventional planar CMOS technology are given. Scaled/emerging technologies such as scaled PD/SOI, UT/SOI, strained-Si channel device, hybrid orientation technology, and multi-gate FinFET are addressed with particular emphases on the implications and impacts on circuit design. Finally, novel logic circuit, SRAM, and power-gating schemes exploiting unique structures and properties of emerging devices are discussed. View full abstract»

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  • Tutorial 13: Analog Circuit Design on Digital CMOS : Why it is difficult, and which ideas help?

    Page(s): nil29
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    This tutorial covers a wide range of small things an analog-IC designer should know to find a path through all the challenges of designing analog circuits on standard digital CMOS processes. The three main topics are: signal integrity (handling noise, treating signal ground, dealing with parasitic modulated feedback in switched circuits) unconventional use of standard parts (exploiting weak inversion, exploiting small dimension effects, unconventional uses of switched-capacitor techniques), and the question whether to feed back or not to feed back (self-biased and regulated current mirrors for gain enhancement, reduction of power consumption with low-feedback circuits.) Most examples come from low-voltage and low-noise broad-band applications, but RF is not covered. Many of the tricks were proven in industrial chips by the author or by people he knows, and will therefore need to be presented without explicit references. View full abstract»

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  • Tutorial 14: Design of Digital Filters Satisfying Prescribed Specifications

    Page(s): nil29
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    In a typical digital filter or digital signal processing class, students are asked to design a digital filter of a specified type and fixed order. The design may or may not be satisfactory for any application but almost always in industry, the best design is required that would satisfy certain desired specifications which are usually predefined on the basis of system considerations. Unfortunately, more often than not the topic of designing the best filter for the application is not treated in the classroom. In this tutorial, design methodologies will be described that would yield FIR as well as IIR filters that would satisfy prescribed specifications. Two types of designs will be explored. Closed-form methods based on some classical techniques and iterative methods based on optimization. The tutorial will draw heavily from the proposer's past teaching experience and research results such as the design of elliptic IIR digital filters, optimization-based techniques such as the design of equalized IIR filters using quasi-Newton methods, and the use of enhanced Remez methods for the design of FIR filters that would satisfy precise predefined specifications. Participants will receive a free license of Dr. Antoniou's DSP software D-Filter (see http://www.d-filter.ece.uvic.ca for details.) View full abstract»

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  • ISCAS 2007 Special Sessions

    Page(s): nil30 - nil31
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    First Page of the Article
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  • Table of contents

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  • Author index

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  • [Copyright notice]

    Page(s): nil205
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  • A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

    Page(s): 1 - 4
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    This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade SigmaDeltamodulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth. View full abstract»

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  • An I/Q Channel Time-Interleaved Band-Pass Sigma-Delta Modulator for a Low-IF Receiver

    Page(s): 5 - 8
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    This paper proposes a multiplexing scheme to realize an I/Q channel time-interleaved (TI) band-pass sigma-delta modulator (BPSDM) that shares OTAs to minimize power consumption and silicon area for a low-IF wireless receiver. The test chip was fabricated for a 10.7-MHz IF system with a 0.35-mum CMOS process. The measured peak SNDR for a 200-kHz bandwidth is approximately 73 dB. The power consumption of the fabricated chip is 61 mW with a 3.3-V supply and the silicon area is 1.78 mm2. View full abstract»

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  • On the modeling and the stability of continuous-time ΣΔ-Modulators

    Page(s): 9 - 12
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    In this paper an exact state equivalency including the input signal between continuous-time (CT) ΣΔ modulators and their discrete-time (DT) counterparts is derived. The equivalency is then generalized to include the very important non-ideal effect of excess loop-delay, that plays a crucial role in continuous-time modulators. With this new state-space equivalency, an efficient tool for stability analysis based on continuous-time describing functions is introduced. In the end, it is explained how these findings can be used for a MATLAB toolbox for continuous-time modulators that complements the well-known Schreier-toolbox for discrete-time modulators. View full abstract»

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  • Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing

    Page(s): 13 - 16
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    A new architecture and signal processing methodology is proposed to implement a first-order single-bit delta-sigma (DeltaSigma) analog-to-digital converter (ADC). The proposed design converts an analog input voltage into a time-difference variable and performs the DeltaSigma signal processing in the time-mode. This offers an incredibly compact and low-power ADC solution while thriving in a low-voltage CMOS environment. The proposed design was fabricated in a standard 0.18-mum CMOS process occupying a silicon area of 15-mum times 25-mum and consumes 475-muW of power. Experimental results reveal that the design can provide a 7-bit resolution at a sampling rate of 140-MHz and input bandwidth of 400-kHz. View full abstract»

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  • A 1.2V 130μA 10-bit MOS-Only Log-Domain ΣΔ Modulator

    Page(s): 17 - 20
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    This paper presents a new low-voltage MOS-only circuit technique to implement oversampling ΣΔ modulators in purely digital CMOS technologies. The basis of the proposed design strategy is a combination of log domain processing and the MOSFET operating in subthreshold. In this sense, compact circuit implementations are given for all the required basic building blocks, such as compressors, integrators, quantizers and DACs. Finally, experimental results are presented for a complete 4th-order 64-oversampling 1-bit ΣΔ modulator integrated using a standard 0.35μm 1-polySi 3-metal digital CMOS technology. View full abstract»

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