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Microelectronics, 2006. ICM '06. International Conference on

Date 16-19 Dec. 2006

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Displaying Results 1 - 25 of 69
  • A 3 to 5 GHz UWB SiGe HBT Low Noise Amplifier

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3612 KB) |  | HTML iconHTML  

    Ultra-wideband low-noise amplifiers (UWB LNA) operating in the low-frequency band (3.1-5 GHz) of UWB spectrum are presented. The designs consist of a cascode amplifier with wideband input matching techniques based on LC-ladder filters or shunt-feedback both combined with inductive peaking. Implemented with a SiGe HBT process, the LNAs give 18.0 dB gain, better than -20 dB input matching, and a return loss less than -34 dB, while consuming 11 mW under 1.5 V supply. The feedback LNA gives a better flat noise figure of 2.5 dB and an input IP3 of -6 dB at 5 GHz. View full abstract»

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  • Adaptive Neural Network Model for SOI-MOSFET I-V Characteristic Including Self-Heating Effect

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3765 KB) |  | HTML iconHTML  

    In this paper, a model for SOI MOSFETs which considers the self-heating effect is proposed. The model which is based on a multi layer perceptron (MLP) neural network, generates the drain current as a function of the gate-source voltage, drain-source voltage, and the device temperature. Based on the current, the temperature of the device channel is calculated. The neural network adapts itself with the channel temperature which can be calculated by an equivalent thermal model for the SOI device. View full abstract»

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  • A 4×4 Tin Oxide Gas Sensor Array with On-chip Signal Pre-processing

    Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3201 KB) |  | HTML iconHTML  

    This paper presents a monolithic 4times4 tin oxide gas sensor array together with on-chip multiplexing and differential read-out circuitry. In contrast to the conventional voltage divider read-out technique, a novel differential read-out circuit (DRC) for tin oxide gas sensors is proposed. The output of the DRC is simply proportional to the difference between the voltage on the two electrodes of the sensor but not to the transistor parameters such as mobility and threshold voltage, neither to the supply voltage. A robust fabrication process focusing on the integration of the CMOS circuitry and the MEMS structures is described. The monolithic sensor array and its processing circuitry have been implemented in our in-house 5 mum process. Experimental results showed good linearity at the output of the DRC for a wide range of sensor resistance variation (over 20 MOmega). Results also show good thermal characteristic leading to only 15.5 mW power consumption for 300 degC operating temperature. View full abstract»

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  • A High Compliance Input and Output Regulated Body-Driven Current Mirror for Deep-Submicron CMOS

    Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2063 KB) |  | HTML iconHTML  

    A current mirror circuit that uses body-driven MOSFETs to achieve an ultra-low input and output voltage is presented. High-gain amplifiers, suitable for a deep submicron process, are used to provide matching as well as input and output regulation. Simulation results were verified with measurements performed on a fabricated chip using the 90-nm CMOS process from ST-Microelectronics. View full abstract»

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  • A Simple Model for the Kink Effect for the Intrinsic p-channel Polysilicon thin film transistors

    Page(s): 17 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2681 KB) |  | HTML iconHTML  

    In order to improve the modeling of polysilicon thin film transistors (Poly-Si-TFTs) a precise evaluation of the excess current due to impact ionization is needed. In this paper, we have proposed a simple model for the excess current resulting from the impact ionization occurring at high drain biases. Model is based on the estimation of the electric field in the saturated part of the channel. The electric field in the saturated region is obtained by the solution of the two-dimensional Poisson's equation. The model is semi-analytical and uses only one fitting parameter which is desirable for circuit simulation. The simulation results with the developed impact ionization current model are in excellent agreement with the available experimental output characteristics of the intrinsic p-channel Poly-Si-TFTs. View full abstract»

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  • An Ultra-Wideband Low-Noise Amplifier for 3-5-GHz Wireless Systems

    Page(s): 20 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2055 KB) |  | HTML iconHTML  

    In this paper, an ultra-wideband low-noise amplifier is designed and simulated in a 0.13-mum CMOS technology for a 3-5-GHz UWB system. For ultra-wideband operation, shunt-series feedback topology is used. To improve noise performance, the amplifier employs inductive load. Biasing point variation which occurs due to the resistive feedback is fixed by adding a capacitor in series with feedback. Thus, the desirable gain is achieved with a lower power consumption. Simulations show a -3-dB gain bandwidth of 6 GHz between 2 GHz and 8 GHz, a minimum noise figure of 1.9 dB in the 3-5-GHz band, a power gain of 11.5 dB while consuming 13.9 mW. View full abstract»

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  • A Fully Integrated Range-Finder Based on the Line-Stripe Method

    Page(s): 24 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (479 KB) |  | HTML iconHTML  

    In this paper, an imaging chip for acquiring range information with 0.35 mum CMOS technology and 5 V power supply has been described. The system can extract range information without any mechanical movement and all the signal processing is done on the chip. All of the image sensors and mixed-signal processors are integrated in the chip. The design range is 1.5 m-10 m with 18 scales. View full abstract»

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  • An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology

    Page(s): 28 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3252 KB) |  | HTML iconHTML  

    A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90% is achieved way above the 40-50% usually seen in other networks on chips. View full abstract»

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  • A Mesochronous Technique for Communication in Network on Chips

    Page(s): 32 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3746 KB) |  | HTML iconHTML  

    In this paper, we propose a mesochronous scheme for communication over serial buses in network on chips (NoC). The technique, which removes metastability errors in mesochronous communications, makes use of only one strobe line with the bus. The strobe line toggles once with every frame of the data. In the suggested method, the frequencies of the transmitter and the receiver are independent with some tolerable difference. The results of HSPICE simulations in a 0.13 mum standard CMOS technology show a 3.65 Gbps as the maximum transmission bandwidth of the technique. The idea can be applied to parallel buses without any change in the control circuit. View full abstract»

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  • Low-latency Multi-Level Mesh Topology for NoCs

    Page(s): 36 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3325 KB) |  | HTML iconHTML  

    In this paper, we introduce a new topology for network on chips which is named multi-level mesh topology. The multi-level mesh topology is basically similar to the 2D-mesh with this difference that we have several meshes that have some common routers. This architecture reduces the latency and the dynamic power consumption in NoCs and can improve the communication throughput in high traffic applications. This architecture reduces the latency of 3 x 3, 5 x 5, and 7 x 7 2-level mesh architectures about 12.5%, 21.4%, and 18.5% related to mesh architecture, respectively. The results are expected to improve further if a better adaptive routing algorithm is utilized. View full abstract»

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  • Electronic conception of a programmable hearing aid

    Page(s): 40 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3710 KB) |  | HTML iconHTML  

    Hearing is the feeling thanks to which, the external world is perceived by the intermediary of specialized sensors, sensitive to the sound vibrations of the air (sound waves). These waves must pass by a whole perception and transmission chain including the outer ear, the middle ear and the inner ear, to arrive finally at the auditive nerve. At each level of this chain, an embarrassment or a rupture generating a situation whose severity can go from light auditive deficiency to major deficiency can be produced. So in the most cases, the port of a hearing aid becomes required. In this paper we are interested in the electronic design of a programmable hearing aid in 0.35 mum MOS technology. View full abstract»

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  • Double-edge Triggered Level Converter Flip-Flop with Feedback

    Page(s): 44 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2972 KB) |  | HTML iconHTML  

    In this paper, a double-edge triggered level converter flip-flop (DE-LCFFF) is proposed. The flip-flop makes use of the conditional discharging technique which effectively suppress the dynamic power consumption during transition time and the self-precharging technique to automatically precharge its dynamic node after enough time. An explicit double-edge pulse generator is used to further decrease the power consumption in the proposed LCFF. In addition, the use of pass gate transistors and more simplified structure in the main block of DELCFFF leads to a less leakage power consumption. The increase in the speed is achieved by reducing the number of the stack transistors in the discharge path and using less complicated circuit structure. When compared to the previous level converter flip-flops, the proposed LCFF shows considerable reductions in the power consumption, the delay, and the area. View full abstract»

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  • Improved Assertion Lifetime via Assertion-Based Testing Methodology

    Page(s): 48 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1435 KB) |  | HTML iconHTML  

    Assertions-based verification (ABV) has been widely used in digital design validation. Assertions are HDL-syntaxed representation of design specification and used as a functional error detection mechanism. During the process of designing with HDLs, assertions are imported which could fire in case of violation during testbench run. Although these assertions are mostly used during simulation and for verifying the functional correctness of the design, but as they illustrate the specifications of a design, it is likely that their lifetime could be extended by embedding them in the chip to detect low level faults like stuck-at faults. In this paper, we introduce a new automatable assertion-based on-line testing methodology. Experimental results show that the synthesis of assertions into a chip, and then using them for online testing, can provide an acceptable coverage for stuck-at faults. View full abstract»

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  • Finding low activity op-code sets using genetic computing

    Page(s): 52 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2987 KB)  

    In this paper, we propose a genetic algorithm for finding the optimum op-code sequence for instruction set of a given processor. The sequence, which we look for, raises the least possible average signal transitions on the address bus of the given processor. The algorithm takes the probability of each instruction pair. Then randomly generates some op-code sequence as the initial population. Afterwards it iteratively uses some problem specific heuristics to generate a better population based upon the existing population and the table of pair probabilities, in this manner better and better populations are generated until (after about 200000 iterations) no better op-code sequence can be generated at which time the algorithm stops. Results, for MIPS-R4000, show that the proposed algorithm reduces the average switching activity of the address bus by 44%. View full abstract»

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  • Hot Block Ring Counter: A Low Power Synchronous Ring Counter

    Page(s): 58 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3367 KB) |  | HTML iconHTML  

    In this paper, we propose a new and low-power architecture for synchronous ring counters which can noticeably reduce the switching activity of the conventional ring counters. To achieve the goal we partition the ring counter into some blocks for each of which we use a special clock gator. The Hot block (the block in which the '1' exists) is the only block the flip-flops of which are clocked. The delay and area overhead of the proposed clock gator is independent of the block size; this enables designer to freely resize the blocks and compromise with area and power overheads. The latency increase in the proposed architecture is independent of the counter width and depends only on the technology. For 90 nm technology it increases the latency by 5%. The architecture noticeably (about 85%) reduces the total switching activity of the counter especially for wide counters. View full abstract»

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  • Efficient Algorithm for Positive-polarity Reed-muller Expansions of reversible circuits

    Page(s): 63 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2558 KB) |  | HTML iconHTML  

    In this paper, we build mathematical modeling for reversible circuits and derive required parameters of cost function from this modeling. The heuristic algorithm plots out reversible circuit into some partitions, uses a priority queue based on search tree and explores candidate components at each partition in order of utilization ratio. We demonstrate that using this heuristic, path delay can be reduced by 8% compared to existing synthesis method. The improvements increase for strict delay constraints making synthesis especially important for high performance and a large number of inputs and outputs designs. View full abstract»

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  • Experimental Evaluation of Three Concurrent Error Detection Mechanisms

    Page(s): 67 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2630 KB) |  | HTML iconHTML  

    This paper presents an experimental evaluation of the effectiveness of three hardware-based control flow checking mechanisms, using software-implemented fault injection (SWIFI) method. The fault detection technique uses reconfigurable of the shelf FPGAs to concurrently check the execution flow of the target program. The technique assigns signatures to the target program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. A total of 3000 faults were injected in the experimental embedded system, which is based on an 8051 microcontroller, to measure the error detection coverage. The experimental results show that these mechanisms detect about 90% of transient errors, injected by software implemented method. View full abstract»

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  • Accelerated Multi-Grid Scheme for Substrate Coupling Modeling and Analysis

    Page(s): 71 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2259 KB) |  | HTML iconHTML  

    This paper proposes a novel method for substrate coupling modeling and analysis. This method is based on accelerated multi-grid, finite difference simulation. In this method the final value of impedance in each stage of modeling is calculated by considering the results of both two previous stage grids. This calculation performed with different weighting factors for two previous stages. This method, with best weighting factors result in 75% decrease in simulation time for low frequency substrate modeling compare with simple multi-grid method. The time saving will improve with increasing the accuracy and number of points for simulation. View full abstract»

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  • A MEMS Disk Resonator-Based Oscillator

    Page(s): 75 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3605 KB) |  | HTML iconHTML  

    A fully integrated MEMS based oscillator using a MEMS disk resonator is presented. Parameter extraction for a circuit model of the disk resonator using ANSYS is carried out at 60.6 MHz. A PIERCE oscillator using the disk resonator is designed. The circuit simulations are presented. The different specs of the oscillator like frequency, phase noise and frequency stability are investigated. The effect of the presence of the disk resonator on the performance of the oscillator is demonstrated. View full abstract»

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  • Translinear-C Function Generator

    Page(s): 79 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2538 KB) |  | HTML iconHTML  

    A novel function generator is realized using a multi output current controlled current conveyors (MOCCCIIs) based current mode band-pass filter, which can simultaneously provide four phase sinusoidal quadrature current outputs, square and triangular voltage outputs. The circuit basically uses only four MOCCCIIs and four grounded capacitors. The function generator enjoys attractive features such as use of grounded capacitors, wide range electronic tunability, low sensitivity figures and load insensitive current outputs. Moreover due to the absence of external resistors the circuit is very much suitable for monolithic implementation. The proposed function generator is designed and verified with excellent results. View full abstract»

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  • Design of FIR Filters Using Identical Subfilters of Even Length

    Page(s): 83 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1803 KB) |  | HTML iconHTML  

    This article presents an analytic development for the design of linear-phase FIR digital filters with reduced computational and hardware complexity. The proposed approach is based on a frequency transformation implemented by replacing a subfilter in a prototype filter. The previous approach forced subfilters and prototype filters to be of odd length, while this approach supports subfilters and prototype filters of even length. Depending on the specifications of the filter, either the previous method or our proposed method can give the optimal solution for the design of the required filter. It has been shown by means of an example that the overall composite FIR filter with the proposed approach contributes to a saving of 22%, 22% and 22% in the number of adders, delays and multipliers respectively compared to the previous approach. View full abstract»

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  • Reconfigurable Low Power FIR Filter based on Partitioned Multipliers

    Page(s): 87 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2367 KB) |  | HTML iconHTML  

    This paper presents a low power programmable FIR filter based on partitioned multipliers. Architecture chosen for implementation is conventional direct form. Power efficient techniques like unsigned multiplication and reduction of switching activity are used. Paper presents power, area and speed analysis of the proposed design. FIR Filter is fully parameterized, dynamically programmable and technology independent. Results are presented for 20-tap FIR filter implemented on Xilinx Vertex-II FPGA 2s200fg256-6. Maximum power saving of 48.2% is achieved with an area overhead of 2.08 % only. View full abstract»

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  • A Very Fast and Low Power Pseudo-Incrementer for Address Bus Encoder/Decoder

    Page(s): 91 - 94
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2053 KB) |  | HTML iconHTML  

    This paper presents a very fast yet low power pseudo incrementer structure which may be used in address bus encoders/decoders. This structure, which is based on the ripple carry incrementer, is much faster than the incrementer. Using this structure, the delay and the power of address bus encoders/decoders may be reduced considerably. Analytical and synthesis results show that the structure is faster than current incrementer circuits while its circuit area and power are much smaller than those of current fast incrementers. View full abstract»

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  • An Optimal Structure for Implementation of Digital Filters

    Page(s): 95 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2374 KB)  

    In this paper, different structures for an elliptic filter with fixed point arithmetic are implemented and compared. The filter must be quantized for hardware implementation. This quantization is done in two steps. First the coefficients of filter are quantized and then the accuracy of internal nodes are limited. According to the simulation results, lattice and DF2- parallel structures have minimal sensitivity to coefficient quantization. Also, the area (gate count) that each of the structures occupy on the chip are computed. We show that overall, the DFl-parallel structure is the optimal structure for hardware implementation that requires minimal chip area at a reasonable precision. View full abstract»

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  • Exponentially Tapering Ground Wires for Elmore Delay Reduction in On Chip Interconnects

    Page(s): 99 - 102
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3295 KB) |  | HTML iconHTML  

    In this paper inter metal capacitors of ground wires are considered, for the first time in Elmore delay calculations of clock distribution interconnect networks. Analytical models for capacitance calculation of inter metal wires which are exponentially tapered are presented. In addition, the tapering of the ground wire for reducing this delay is proposed. The results show that by a exponentially tapering of the ground wires in the clock distribution networks , a 17% reduction in the Elmore delay of interconnects is achieved in compare with not tapering ground wires. View full abstract»

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