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VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on

Date 25-27 April 2007

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Displaying Results 1 - 25 of 73
  • [Front cover]

    Publication Year: 2007 , Page(s): C1
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    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 2007 , Page(s): 1
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  • Native-Mode Self Test for Embedded Systems on a Chip

    Publication Year: 2007 , Page(s): 1
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    Advances in semiconductor technology have enabled the integration of digital, mixed-signal, and RF systems on a single chip. While systems on a chip (SoCs) offer many benefits in cost and performance, they pose significant challenges for testing after manufacture. Trends in technology as well as applications which pose problems for conventional test will be described. A novel approach which uses the computational resources of an SoC to test itself will be described as a way to deal with emerging test problems. Techniques to test the embedded digital, analog and RF modules in the SoC will be discussed. Results of simulations and measurements on prototype hardware show that the approach can predict the specifications of the modules with high accuracy, pointing towards a new direction for low-cost manufacturing test of future products. View full abstract»

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  • Nanoelectronics: challenges and opportunities

    Publication Year: 2007 , Page(s): 1
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    Summary form only given. The scaling of CMOS technology is coming soon to an end, and yet it is unclear whether CMOS devices in the 10-20 nanometer range will find a useful place in semiconductor products. At the same time, new silicon-based technologies (e.g., silicon nanowires) and non-silicon based (e.g., carbon nanotubes) show the promise of replacing traditional transistors. In this scenario, there are multiple challenges to face, like the production of nanoscale CMOS with reasonable yield and reliability, the creation of newer circuit structures with novel materials as well as the mixing and matching of older and newer technologies in search of a good balance of costs and benefits. View full abstract»

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  • Challenges of Digital Consumer and Mobile SoC's: More Moore Possible?

    Publication Year: 2007 , Page(s): 1
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    Summary form only given. Digital consumer and mobile products have continuously accommodated more features and functions. For example, recent high-end cellular phones work as multi-modal wireless communicators that handle various formats; GSM, 3G, BT, WiFi and so on. In addition, they also operate as terrestrial digital TV viewers, MP3 music players, digital cameras, substitutes for credit cards, GPS locators and many more. These products require to best combine highly integrated SoC's and sophisticated software stacks in a timely manner. It is essential to establish a hardware/software co-design/verification environment with an ESL design methodologies. Another key is an IP reuse platform where various functions can be implemented on an SoC by legacy sub-systems with a low-power multi-processor architecture. These challenges are getting more complicated in deep sub-100 nm technology nodes. View full abstract»

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  • Microprocessor Modeling and Simulation with SystemC

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB) |  | HTML iconHTML  

    Complexity of advanced chip designs is driving the progress of ESL methodology. SystemC, with its mature C++ language environment and the availability of public tools, is quickly becoming the de facto ESL language. In this paper, we demonstrate the methodology by microprocessor modeling with systemC. Various abstraction levels and the corresponding purposes are addressed. The advantage of ESL methodology is shown by the experimental results of simulation speed. With a 18 times to over 500 times simulation speed-up, the methodology has proved useful in modeling, verification, and software development. View full abstract»

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  • A Memory-Efficient Progressive JPEG Decoder

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2997 KB) |  | HTML iconHTML  

    Image formats specified by the joint photographic expert group (JPEG) are preferred in many applications, including Internet and digital cameras. Baseline and progressive JPEG are the two of the most popular formats. While the challenge to design a baseline JPEG decoder is mainly the computation complexity, the challenge to design a progressive JPEG decoder imposes on the size of the available working memory and the rate of data transfer between the decoder and the storage. This paper presents a memory-efficient progressive JPEG decoder for embedded systems with limited working memory. Two progressive JPEG rendering flows, one-pass and multi-pass flows, are proposed to improve the most time-consuming data transfer and arithmetic operations during the rendering procedure. The using of dynamically adaptive rendering flow makes proposed progressive JPEG decoder well suited to a wide range of image processing applications in consumer products. View full abstract»

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  • An LLC-OCV Methodology for Statistic Timing Analysis

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2508 KB) |  | HTML iconHTML  

    With further increase in chip size and shrink in device dimension, the influence of on chip semiconductor process variation can no longer be ignored in design phase such as STA sign-off. This paper presents the LLC-OCV methodology, which adopts the Monte Carlo analysis to enhance the location-based OCV (LOCV) with gate-level and cell-based perspectives, to be used as a reasonable and complete intra-die process model for STA (statistic timing analysis) sign-off. This new approach shows good prediction for STA sign-off. With LLC-OCV methodology, this paper has correctly identified timing problems in real silicon projects of 0.13 mum process in STA sign-off stage. Comparing the STA results of LOCV and LLC-OCV methodology, our experiment shows that LLC-OCV approach can avoid pessimistic analysis and save chip area. View full abstract»

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  • A Matching-based Placement and Routing System for Analog Design

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4820 KB) |  | HTML iconHTML  

    Matching placement and routing is very important in layout design of high performance analog circuits. This paper presents a matching-based placement and routing system for custom layout design automation especially for analog or mixed-signal designs. The system explores various device-level matching-placement and matching-routing patterns to generate the most compact and high-quality layouts. Inputting a circuit netlist, the system automatically analyzes the circuit and extracts matching devices to form several matching device groups. Then, it selects the best matching placement and routing pattern for each device or device group to optimize and to meet the overall placement objectives and constraints. All patterns are user-configurable, stored in the pattern database, and portable from design to design. After the layout of each device and device group is generated and placed, the constraint-driven shape-based router is invoked to complete the layout. The overall system can easily generate high-quality layouts and greatly reduce the layout design time. View full abstract»

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  • Test Power IR Drop Closure Flow for NetComposer-I Platform Design

    Publication Year: 2007 , Page(s): 1 - 4
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    Power noise has become one of the main culprits in failing chips in SoC designs. As power consumption during scan test can be several times higher than during normal operation, it must be dealt with properly during implementation and testing stages. In this paper, we share some of the test power related experiences we gained through the development of NetComposer platform design. We demonstrate how good power analysis and DFT can help avoid potential power noise issue during test. View full abstract»

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  • 4-Mb SPI Flash Compatible Phase-Change Memory

    Publication Year: 2007 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4455 KB) |  | HTML iconHTML  

    A 4-Mb with SPI serial interface phase-change memory which is completely compatible with the traditional SPI flash memory is implemented in this study. The peripheral circuit is much simpler than flash memory. The 512 Kb sector erase time is less than 7 ms while the 4 Mb bulk erase time is 80 ms only. View full abstract»

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  • A Low-Power Low-Swing Single-Ended Multi-Port SRAM

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4899 KB) |  | HTML iconHTML  

    In this paper, a new single-ended 6-T SRAM cell is proposed. It has a very strong static noise margin (SNM) during read cycles. Meanwhile, data can be easily written because of floating virtual ground and 1-T equalizer insertion within cell. Low-swing writing ability is achieved by these two approaches. A single-ended current-mode sensing amplifier is also presented. This amplifier can sense a very small swing of bitline, equipping with a high noise-rejection and high PVT-tolerance ability. A low-swing 3-port 64times32-bit SRAM macro is simulated in TSMC 130 nm CMOS technology. It consumes a minimum of 725 muW and 658 muW per-port at 1 GHz with 1.2 V supply voltage for read and write power, respectively. View full abstract»

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  • A 256×128 Energy-Efficient TCAM with Novel Low Power Schemes

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4507 KB) |  | HTML iconHTML  

    Novel low power schemes for energy-efficient ternary content-addressable memory (TCAM) are presented in this paper. The butterfly match-line scheme is based on the pseudo-footless clock-data pre-charged architecture. It connects each pipelined stage in a butterfly style which significantly decreases both search time and power consumption. For applications like IP-address forwarding in a network router, a new don't-care based power gating and don't-care based hierarchical (DCBH) search-line scheme are proposed. The search-line is divided into global search-line (GSL) and local search-line (LSL) which is controlled by don't-care state in DCBH search-line scheme. Therefore, the power consumption on search line is reduced without any search time overhead. Besides, the power saving of the standby power is achieved by power gating technique. The proposed 256 times 128 bit TCAM has been implemented with TSMC 0.13 um CMOS technology. It shows 0.55 ns of match evaluation time on search operation with 0.29 fJ/bit/search of energy efficiency. View full abstract»

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  • Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4194 KB) |  | HTML iconHTML  

    A new circuit design for mixed-voltage I/O buffers to prevent hot-carrier degradation is proposed. The mixed-voltage (2timesVDD tolerant) I/O buffer is designed with hot-carrier-prevented circuits in a 0.18-mum CMOS process to receive 3.3-V (2timesVDD tolerant) input signals without suffering gate-oxide reliability, circuit leakage issues, and hot-carrier degradation. In the experimental chip, the proposed mixed-voltage I/O buffer can be operated with signal speed of up to 266 MHz, which can fully meet the applications of PCI-X 2.0. View full abstract»

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  • Minimizing Energy Consumption with Variable Forward Body Bias for Ultra-Low Energy LSIs

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3983 KB) |  | HTML iconHTML  

    Ultra-low energy LSI becomes primary concern in today's battery driven ubiquitous computing portable applications. To reduce energy per transition and to enhance performance in the ultra-low voltage region, we review the variable forward body bias scheme to make either faster pull-up or pull-down transition in the sub-threshold, near-threshold and above-threshold regimes. We begin our study for minimizing energy per transition by applying variable forward body bias asymmetrically and propose novel approaches to energy efficient design with performance advantages. To analyze and discuss, the fan-out of 3 (FO3) inverter based 51-stage delay chain is simulated in an industrial 130 nm triple well process technology. View full abstract»

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  • Maximizing Full-Chip Simulation Signal Visibility for Efficient Debug

    Publication Year: 2007 , Page(s): 1 - 5
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (918 KB) |  | HTML iconHTML  

    The most expensive parts of today's system-on-chip (SoC) design flow are where engineers must engage in direct manual effort. Unfortunately, far too much time and money are wasted on tasks that don't add value -such as trying to figure out how supposedly-correct IP is actually working, debugging "dumb" errors, or deciding what signals to record in any given simulation run. With small block-level simulation, it is practical to record every value change on every signal. This produces a rich database of time-ordered event data that can be used for understanding the block's behavior and debugging errors. However, for large subsystem or full-chip level simulation, the overhead required to record all the events on all the signals overwhelms the run-time and fills the available disk space. Run times can explode by a factor of five. Disk requirements can run to the 100 s of gigabytes. The emergence of visibility enhancement technologies enables engineers to make intelligent tradeoffs between impact (simulation performance and file size) and visibility. View full abstract»

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  • Reducing Transaction-Level Modeling Effort while Retaining Low Communication Overhead for HW/SW Co-Emulation System

    Publication Year: 2007 , Page(s): 1 - 4
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    This paper presents a new scheme that reduces the modeling efforts of a transactor while retaining the performance of transaction-based verification for hardware/software co-emulation system. The conventional transaction-based verification requires the designer to develop a synthesizable transactor which interfaces with unfamiliar emulation-system-dependent protocol. The proposed method locates the transactor in the software side instead of in the hardware emulator. This allows easy-to-develop transactor described in high-level language. To reduce the communication time between testbench and DUT, we make the signal flow uni-directional by exploiting existing HDL testbench. The experimental results show that the proposed method is applicable to real-world test environment. View full abstract»

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  • Designing Globally Optimal Delta-Sigma Modulator Topologies via Signomial Programming

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (1)
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    We present design methodologies for globally optimizing the topologies of delta-sigma modulators. The design task is cast into a generally nonconvex signomial programming problem. Convexification strategies are presented for transforming the nonconvex signomial programming problems into their equivalent convex counterparts, thereby enabling the solution of globally optimal design parameters. Numerical examples verify the effectiveness and superiority of the proposed approach over conventional nonlinear programming techniques. View full abstract»

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  • On-Chip Bus Encoding for Power Minimization Under Delay Constraint

    Publication Year: 2007 , Page(s): 1 - 4
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    As technology advances, the global interconnect delay and the power consumption of long wires become crucial issues in nanometer technologies. In particular, both inductive and capacitive coupling effects between wires result in serious problems such as crosstalk delay, coupling noise, and power consumption. In this paper, we propose a new bus encoding scheme for global bus design in nanometer technologies. With the user-given bus parameters, the working frequency, and the delay constraint, the scheme can minimize the bus power consumption subject to the delay constraint by effectively reducing the LC coupling effects. View full abstract»

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  • A 4-Channel Poly-Phase Filter for Cognitive Radio Systems

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1832 KB) |  | HTML iconHTML  

    A 4-channel poly-phase filter is proposed for cognitive radio systems. The cognitive radio system can sense the spectrum utilization and achieve higher transmission efficiency. To maximize the dynamic range of the receiver, the multi-channel poly-phase filter is required in the cognitive radio receiver to suppress the interference that is typically generated by legacy users. The filter is able to select different channels according to the demand of the system. A chip is fabricated in 0.18-mum CMOS technology. It dissipates 13.4 mW and achieves 35-dB adjacent channel rejection. View full abstract»

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  • Analysis and Design of a 1V Charge Sampling Readout Amplifier in 90nm CMOS for Medical Imaging

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB) |  | HTML iconHTML  

    In this paper, we present the analysis and design of a charge sampling amplifier (CSA) in 90 nm CMOS for medical imaging applications. The CSA is designed based on a 1 V CMOS folded cascode operational transconductance amplifier (OTA) with lead compensation. The OTA achieves a DC gain of 45-dB and a unity gain frequency of 1.3 GHz at a power consumption of 200 muW. Performance of the charge sampling amplifier is investigated when it is connected to a single capacitive micro machined ultrasound transducer (CMUT). The proposed CSA front end architecture for ultrasound imaging achieves a transfer gain of 19 dB from CMUT signal source to the output of the CSA (across feedback capacitor) with sampling simultaneously. View full abstract»

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  • A 6Gbps Serial Link Transmitter with Pre-emphasis

    Publication Year: 2007 , Page(s): 1 - 2
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2402 KB) |  | HTML iconHTML  

    In this paper, we propose a novel 6Gbps SATA transmitter. The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1-5 meter cable. A test chip of transmitter with PLL and on-chip termination is implemented to verify the design methodology. The overall circuit is implemented in TSMC 0.18 mum 1P6M 1.8 V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68 mW for 6Gbps case. View full abstract»

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  • Challenges for Low-power Embedded SOC's

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4030 KB) |  | HTML iconHTML  

    Low power is one of the most important metrics in the embedded SOC's design. Many techniques and technologies for low-power design are developed and applied in the practical design projects. One of the difficulties in low-power design is the definition of power consumption. The power consumption of the LSI varies according to the operating function and data values. Current low-power techniques are focusing to reduce the power consumption using the characteristics of LSI behaviors. Some low-power techniques only supply the hardware features of low power and require the software control using these low-power features. This means that the system level approach including hardware features and software control is very important in low-power design. The final goal of low-power LSI is not the smallest power consumption of LSI but the long battery life, the low-cost cooling equipment, the small body, etc. of the embedded systems. Many low-power techniques, which are used in the practical SOC's like SH-mobile application processors for mobile phones will be discussed. And new challenges for low-power solution in system level will be also discussed. View full abstract»

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  • Mixed Hardware Software Multilevel Modeling and Simulation for Multithreaded Heterogeneous MPSoC

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (2)
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    In this paper, we introduce a mixed hardware -software architecture model to abstract hardware-software interfaces of multithreaded heterogeneous multiprocessor architecture with specific hardware I/O. We use Simulink environment as modeling language to capture this representation. We generate two intermediate simulation models called Virtual Architecture and Transaction Accurate to validate the software during the different design steps. The software refinement is performed by automatic software code generation for parallel application from Simulink model, and automatic low level software customization for specific architecture. Through experiments we show the efficiency of the proposed design flow that decreases design time without affecting design quality. View full abstract»

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  • Low-Power Instruction Cache Architecture Using Pre-Tag Checking

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (1)
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    In this paper, we propose a low-power instruction cache architecture utilizing three techniques - two-phased cache, sequential access indicator for tag-memory access skipping, and a new proposed technique named pre-tag checking. By these techniques, significant portion of tag-memory and data-memory accesses can be eliminated to reduce the power consumption. The experimental results show that the proposed instruction cache architecture can reduce about 54% power consumption compared to the conventional one for an 8 KB two-way set associative cache. View full abstract»

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