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18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07)

Date 28-30 May 2007

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Displaying Results 1 - 25 of 39
  • 18th IEEE/IFIP International Workshop on Rapid System Prototyping - Cover

    Publication Year: 2007, Page(s): c1
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  • 18th IEEE/IFIP International Workshop on Rapid System Prototyping - Title page

    Publication Year: 2007, Page(s):i - iii
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  • 18th IEEE/IFIP International Workshop on Rapid System Prototyping - Copyright

    Publication Year: 2007, Page(s): iv
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  • 18th IEEE/IFIP International Workshop on Rapid System Prototyping - Table of contents

    Publication Year: 2007, Page(s):v - vii
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  • Message from the General Chairs

    Publication Year: 2007, Page(s): viii
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  • Message from the Program Chairs

    Publication Year: 2007, Page(s): ix
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  • Acknowledgments

    Publication Year: 2007, Page(s): x
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  • Conference Committees

    Publication Year: 2007, Page(s): xi
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  • Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass

    Publication Year: 2007, Page(s):3 - 9
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    Today's digital systems design requires extensive system- level simulation to ensure that the right architectural trade-offs are made. In platform based designs a large number of platforms models must be executed for tuning the platform for the application. In order to run these simulations with adequate performance, design architects have increasingly employed abstract transaction-level models in... View full abstract»

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  • Codesign of a Computationally Intensive Problem in GF(3)

    Publication Year: 2007, Page(s):10 - 16
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    A reprogrammable hardware platform is used for the co-design and implementation of a computational intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)), The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software co-design methodologies and techniques, and it is co... View full abstract»

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  • Unified Inter-Communication Architecture for Systems-on-Chip

    Publication Year: 2007, Page(s):17 - 26
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    System-on-chip (SoC) architectures are called to be the platform for an ever increasing number of interactive applications. One of the most time- consuming tasks is to define communication interfaces between the different components through a number of scattered heterogeneous processing nodes. That is not only a complex task, but also very specific to a certain implementation, which may limit the ... View full abstract»

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  • SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems

    Publication Year: 2007, Page(s):27 - 33
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB) | HTML iconHTML

    A widely used approach to avoid network intrusion is SNORT, an open source network intrusion detection system (NIDS). This work describes SPP- NIDS, a architecture for intrusion detection supporting SNORT rules. SPP-NIDS is attractive to real-world network intrusion detection, due to its scalability, flexibility and performance features. A parameterizable cluster of simple processors provides syst... View full abstract»

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  • Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

    Publication Year: 2007, Page(s):34 - 40
    Cited by:  Papers (48)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (503 KB) | HTML iconHTML

    Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the "design crisis " (gap between silicon technology and actual SoC design capacity) and reduce the time to market. Important issues in MPSoC design are the communication infrastructure and task mapping. MPSoCs may employ NoCs to integrate multiple programmable processor cores, specialized memories, and other IP... View full abstract»

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  • Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem

    Publication Year: 2007, Page(s):41 - 47
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    In this paper we discuss how one of the most famous local optimization algorithms for the Traveling Salesman Problem, the 2-Opt, can be efficiently implemented in hardware for Euclidean TSP instances up to a few hundred cities. We introduce the notion of "symmetrical 2-Opt moves" which allows us to uncover fine-grain parallelism when executing the specified algorithm. We propose a novel architectu... View full abstract»

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  • Hardware/Firmware Verification of Graphic IP

    Publication Year: 2007, Page(s):48 - 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (131 KB) | HTML iconHTML

    This paper describes methods and simulation techniques used to verify the functional correctness of a flexible video processing engine IP. The verification environment relies on co-simulation of the RTL IP under-design with functional building blocks, developed using SystemC constructs. We try here to assess a number of problems encountered during the verification of complex IPs such as flexibilit... View full abstract»

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  • Communication Models in Networks-on-Chip

    Publication Year: 2007, Page(s):57 - 60
    Cited by:  Papers (3)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (227 KB) | HTML iconHTML

    Networks-on-chip, or NoCs, are one communication architecture candidate to be used in present and future SoCs, due to its scalability, reusability and performance. The focus of this paper is the analysis of IP communication models in NoCs. Employing standard external interfaces, as OCP, is recommended to enable the use of NoCs by different IP core providers. The second point related to reusability... View full abstract»

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  • A Lightweight Framework for Runtime Reconfigurable System Prototyping

    Publication Year: 2007, Page(s):61 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    This paper describes a lightweight framework for prototyping runtime reconfigurable systems in a Xilinx Virtex-II Pro FPGA. The framework provides a reconfiguration and control infrastructure that allows components of the prototype system to be modified or exchanged at runtime by means of partial reconfiguration of the FPGA. The system state may be monitored and influenced by a programmable contro... View full abstract»

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  • Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System

    Publication Year: 2007, Page(s):65 - 68
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (238 KB) | HTML iconHTML

    This paper presents the design and implementation of a real time face detection system on an embedded reconfigurable platform. Our approach to face detection is based on a skin-segmentation algorithm followed by feature extraction and face verification. Our implementation is done on DMV, a reconfigurable platform with novel features targeting real time computer vision applications. DMV is a system... View full abstract»

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  • Object-Oriented Reconfiguration

    Publication Year: 2007, Page(s):69 - 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (125 KB) | HTML iconHTML

    As embedded systems are getting more complex, they are also presenting more stringent constraints like performance, power consumption, memory footprint and so on. At the same time, because of market pressures, their development time must be constantly reduced. The employment of object orientation would solve the design cycle problem. However, OO languages like Java or C+ + are not targeted to any ... View full abstract»

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  • A Semantics for UML-RT using n-calculus

    Publication Year: 2007, Page(s):75 - 82
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (277 KB) | HTML iconHTML

    UML-RT is a UML real-time profile that allows event-driven and distributed systems. UML-RT is not a formal specification language, therefore it is not possible to do formal verification of UML-RT models. This article proposes formal semantics for UML-RT via mapping of UML-RT communicating elements into pi-calculus. The pi-calculus is a process algebra to model concurrent systems. A prototype was a... View full abstract»

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  • Verifying Distributed Protocols using MSC-Assertions, Run-time Monitoring, and Automatic Test Generation

    Publication Year: 2007, Page(s):82 - 88
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB) | HTML iconHTML

    This paper addresses the need for formal specification and runtime verification of system-level requirements of distributed reactive systems. It describes a formalism for specifying global system behaviors in terms of message sequence chart assertions and a technique for the evaluation of the likelihood of success of a distributed protocol under non-trivial communication conditions via discrete ev... View full abstract»

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  • Rapid Prototyping of Intrusion Detection Systems

    Publication Year: 2007, Page(s):89 - 98
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB) | HTML iconHTML

    Designing security softwares that evolve as quickly as threats is a truthful challenge. In addition, current software becomes increasingly more complex and difficult to handle even for security experts. Intrusion Detection Softwares (IDS) represent a solution that can alleviate these concerns. This paper proposes a framework to automatically build an effective online IDS which can check if the pro... View full abstract»

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  • A Tailored Design Partitioning Method for Hardware Emulation

    Publication Year: 2007, Page(s):99 - 105
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (759 KB) | HTML iconHTML

    Partial run time reconfiguration (pRTR) enables a dynamic replacement of design modules to optimize the resource utilization of FPGA-based hardware emulation. This requires an appropriate partitioning of the entire design into particular hardware modules. There exist various methods to partition a design at functional as well as at structural level. In this paper, an adapted functional method to p... View full abstract»

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  • Rapid Prototyping of Intrusion Detection Systems

    Publication Year: 2007, Page(s):106 - 112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    Designing security softwares that evolve as quickly as threats is a truthful challenge. In addition, current software becomes increasingly more complex and difficult to handle even for security experts. Intrusion Detection Softwares (IDS) represent a solution that can alleviate these concerns. This paper proposes a framework to automatically build an effective online IDS which can check if the pro... View full abstract»

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  • Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels

    Publication Year: 2007, Page(s):113 - 122
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (331 KB) | HTML iconHTML

    Multimedia applications require heterogeneous multiprocessor architectures with specific I/O components in order to achieve computation and communication performances. The different processors run different software stacks made of the application code and the hardware dependent software layer. Developing this software usually makes use of a high level programming environment that does not handle s... View full abstract»

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