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Rapid System Prototyping, 2007. RSP 2007. 18th IEEE/IFIP International Workshop on

Date 28-30 May 2007

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Displaying Results 1 - 25 of 39
  • 18th IEEE/IFIP International Workshop on Rapid System Prototyping - Cover

    Page(s): c1
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  • 18th IEEE/IFIP International Workshop on Rapid System Prototyping - Title page

    Page(s): i - iii
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  • 18th IEEE/IFIP International Workshop on Rapid System Prototyping - Copyright

    Page(s): iv
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  • 18th IEEE/IFIP International Workshop on Rapid System Prototyping - Table of contents

    Page(s): v - vii
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  • Message from the General Chairs

    Page(s): viii
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  • Message from the Program Chairs

    Page(s): ix
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  • Acknowledgments

    Page(s): x
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  • Conference Committees

    Page(s): xi
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  • Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass

    Page(s): 3 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (209 KB) |  | HTML iconHTML  

    Today's digital systems design requires extensive system- level simulation to ensure that the right architectural trade-offs are made. In platform based designs a large number of platforms models must be executed for tuning the platform for the application. In order to run these simulations with adequate performance, design architects have increasingly employed abstract transaction-level models instead of RTL models to perform such analysis. Memory hierarchy is a major bottleneck for performance and energy consumption. Trying out every supported cache configuration to evaluate a given platform may become a very time consuming task. This paper proposes an approach for memory cache tuning, which is based on single-pass simulation. The proposed single-pass cache evaluation mechanism is 70 times faster than a simulation-based mechanism for the ADPCM application from Mediabench. View full abstract»

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  • Codesign of a Computationally Intensive Problem in GF(3)

    Page(s): 10 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (373 KB) |  | HTML iconHTML  

    A reprogrammable hardware platform is used for the co-design and implementation of a computational intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)), The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software co-design methodologies and techniques, and it is completely designed, implemented and evaluated on two distinct platforms, not simply by simulations. FPGAs are used as part of the reconfigurable hardware in both a PCI-based environment and in a more successful System-on-Chip (SOC) platform, which takes advantage of the closely-coupled interconnection between the hardware and software, thus minimizing the communication overhead. The case study, findings and general analysis lead to a possible ideal architecture for future approaches. Moreover, a more general detailed strategy can be seen for the transformation from software to a co-design paradigm, maximizing parallelism. View full abstract»

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  • Unified Inter-Communication Architecture for Systems-on-Chip

    Page(s): 17 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    System-on-chip (SoC) architectures are called to be the platform for an ever increasing number of interactive applications. One of the most time- consuming tasks is to define communication interfaces between the different components through a number of scattered heterogeneous processing nodes. That is not only a complex task, but also very specific to a certain implementation, which may limit the flexibility of the system, and makes the solutions difficult to reuse. In this paper, we describe how the distributed systems paradigm can be extended to provide a unified abstraction for both hardware and software components. Moreover, based on that abstraction, we define a low-overhead system-wide communication architecture that offers communication transparency between all kinds of components. Since the architecture is highly compatible with standard distributed object software systems, it also allows seamless interaction with any other kind of external network. View full abstract»

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  • SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems

    Page(s): 27 - 33
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    A widely used approach to avoid network intrusion is SNORT, an open source network intrusion detection system (NIDS). This work describes SPP- NIDS, a architecture for intrusion detection supporting SNORT rules. SPP-NIDS is attractive to real-world network intrusion detection, due to its scalability, flexibility and performance features. A parameterizable cluster of simple processors provides system scalability. Hardware NIDSs described in the literature often employ hardwired comparators to verify if the incoming network traffic has data potentially containing intrusion attacks. Such NIDSs must be re-synthesized when a new set of rules is available, which happens frequently. In SPP-NIDS, the rule set defining network intrusion patterns is stored in RAM, enabling its straightforward upgrade. The proposed system, when implemented in a 2-million gate FPGA is able to work at a 100 Mbps network data rate, using the complete set of SNORT rules. If more performance is required, it suffices to scale the system, by adding extra processors. View full abstract»

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  • Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

    Page(s): 34 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (503 KB) |  | HTML iconHTML  

    Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the "design crisis " (gap between silicon technology and actual SoC design capacity) and reduce the time to market. Important issues in MPSoC design are the communication infrastructure and task mapping. MPSoCs may employ NoCs to integrate multiple programmable processor cores, specialized memories, and other IPs in a scalable way. Applications running in MPSoCs execute a varying number of tasks simultaneously, and their number may exceed the available resources, requiring task mapping to be executed at runtime to meet real-time constraints. Most works in the literature present static MPSoC mapping solutions. Static mapping defines a fixed placement and scheduling, not appropriate for dynamic workloads. Task migration has also been proposed for use in MPSoCs, with the goal to relocate tasks when performance bottlenecks are identified. This work investigates the performance of mapping heuristics in NoC-based MPSoCs with dynamic workloads, targeting NoC congestion minimization, a key cost function to optimize the NoC performance. Here, tasks are mapped on the fly, according to communication requests and the load in the NoC links. Results show execution time and congestion reduction when congestion-aware mapping heuristics are employed. View full abstract»

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  • Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem

    Page(s): 41 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    In this paper we discuss how one of the most famous local optimization algorithms for the Traveling Salesman Problem, the 2-Opt, can be efficiently implemented in hardware for Euclidean TSP instances up to a few hundred cities. We introduce the notion of "symmetrical 2-Opt moves" which allows us to uncover fine-grain parallelism when executing the specified algorithm. We propose a novel architecture that exploits this parallelism. A subset of the TSPLIB benchmark is used to evaluate the proposed architecture and its ASIC implementation, which exhibits better final results and an average speedup of 20 when compared with the state-of-the-art software implementation. Our approach produces, to the best of our knowledge, the fastest to date TSP 2-Opt solver for small-scale Euclidean TSP instances. View full abstract»

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  • Hardware/Firmware Verification of Graphic IP

    Page(s): 48 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (131 KB) |  | HTML iconHTML  

    This paper describes methods and simulation techniques used to verify the functional correctness of a flexible video processing engine IP. The verification environment relies on co-simulation of the RTL IP under-design with functional building blocks, developed using SystemC constructs. We try here to assess a number of problems encountered during the verification of complex IPs such as flexibility of functions, simulation speed and performance. View full abstract»

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  • Communication Models in Networks-on-Chip

    Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    Networks-on-chip, or NoCs, are one communication architecture candidate to be used in present and future SoCs, due to its scalability, reusability and performance. The focus of this paper is the analysis of IP communication models in NoCs. Employing standard external interfaces, as OCP, is recommended to enable the use of NoCs by different IP core providers. The second point related to reusability is the IP cores communication model. Two basic communication models are considered in this work: NUMA and NORMA. The goal of this work is to evaluate the pros and cons of each communication model, in terms of network interface complexity, area and performance. View full abstract»

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  • A Lightweight Framework for Runtime Reconfigurable System Prototyping

    Page(s): 61 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (194 KB) |  | HTML iconHTML  

    This paper describes a lightweight framework for prototyping runtime reconfigurable systems in a Xilinx Virtex-II Pro FPGA. The framework provides a reconfiguration and control infrastructure that allows components of the prototype system to be modified or exchanged at runtime by means of partial reconfiguration of the FPGA. The system state may be monitored and influenced by a programmable controller which is part of the framework. The area overhead of the framework is kept low by efficiently utilising the two hard-wired PowerPC processor cores inside the FPGA while avoiding the use of resource-intense bus structures. Specific lean input/output modules are used with the one processor core while the other implements a Xilinx UltraController-II based design. View full abstract»

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  • Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System

    Page(s): 65 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    This paper presents the design and implementation of a real time face detection system on an embedded reconfigurable platform. Our approach to face detection is based on a skin-segmentation algorithm followed by feature extraction and face verification. Our implementation is done on DMV, a reconfigurable platform with novel features targeting real time computer vision applications. DMV is a system on chip based on the combination of a high performance 32-bit SPARC-compliant processor with data-flow processing blocks. View full abstract»

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  • Object-Oriented Reconfiguration

    Page(s): 69 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (125 KB) |  | HTML iconHTML  

    As embedded systems are getting more complex, they are also presenting more stringent constraints like performance, power consumption, memory footprint and so on. At the same time, because of market pressures, their development time must be constantly reduced. The employment of object orientation would solve the design cycle problem. However, OO languages like Java or C+ + are not targeted to any of the embedded systems constraints stated before. Based on all these facts, this work focuses on providing the high OO abstraction, while maintaining embedded systems perspective. The methodology consists in the execution of selected objects in a reconfigurable hardware, which solves the overhead problems. This way, with efficient execution of certain intensively used objects in the reconfigurable array, we show performance improvements of up to 47% and savings of 37% in energy consumption, still taking advantage of the well known benefits of an object-oriented language. For our experiments we used a native Java processor, together with a complete MP3 player, representing a complex embedded system benchmark. View full abstract»

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  • A Semantics for UML-RT using n-calculus

    Page(s): 75 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (277 KB) |  | HTML iconHTML  

    UML-RT is a UML real-time profile that allows event-driven and distributed systems. UML-RT is not a formal specification language, therefore it is not possible to do formal verification of UML-RT models. This article proposes formal semantics for UML-RT via mapping of UML-RT communicating elements into pi-calculus. The pi-calculus is a process algebra to model concurrent systems. A prototype was also developed; it captures information of UML-RT model from RoseRT and generates pi-calculus definitions according to the proposed mapping rules. The generated pi- calculus definitions use the syntax of HAL-JACK, that is an integrated tool set for the specification, verification and analysis of systems expressed by pi-calculus. In the article, we describe the UML-RT to pi-calculus mapping, we explain the prototype and we present an example of the mapping. View full abstract»

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  • Verifying Distributed Protocols using MSC-Assertions, Run-time Monitoring, and Automatic Test Generation

    Page(s): 82 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    This paper addresses the need for formal specification and runtime verification of system-level requirements of distributed reactive systems. It describes a formalism for specifying global system behaviors in terms of message sequence chart assertions and a technique for the evaluation of the likelihood of success of a distributed protocol under non-trivial communication conditions via discrete event simulation and runtime execution monitoring. We constructed a proof-of-concept prototype for the leader-election algorithm within a 4-node ring network. The prototype consists of the following components: (i) an OMNeT++ model of the network using non-trivial communication conditions, (ii) C+ + code for the network agents, (Hi) a system-level assertion stipulating the formal requirement for a correct, time- bound, leader election, (iv) simulation of the formal assertion, (v) automatic scenario generation, and (vi) run-time monitoring of the formal assertion and stochastic-based estimation of the likelihood of success of this assertion under the specified communication conditions. View full abstract»

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  • Rapid Prototyping of Intrusion Detection Systems

    Page(s): 89 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    Designing security softwares that evolve as quickly as threats is a truthful challenge. In addition, current software becomes increasingly more complex and difficult to handle even for security experts. Intrusion Detection Softwares (IDS) represent a solution that can alleviate these concerns. This paper proposes a framework to automatically build an effective online IDS which can check if the program's expected behavior is respected during the execution. The proposed framework extracts relevant information from the program's source code to build a dedicated IDS. We use the GCC compiler to produce the structure of our behavior's model and ensure the IDS is correct. Thanks to Petri nets, our framework allows program offline monitoring and simplifies the online monitoring development. View full abstract»

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  • A Tailored Design Partitioning Method for Hardware Emulation

    Page(s): 99 - 105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (759 KB) |  | HTML iconHTML  

    Partial run time reconfiguration (pRTR) enables a dynamic replacement of design modules to optimize the resource utilization of FPGA-based hardware emulation. This requires an appropriate partitioning of the entire design into particular hardware modules. There exist various methods to partition a design at functional as well as at structural level. In this paper, an adapted functional method to partition the design into independent modules is proposed. In consideration of typical functional modules (e.g. controller, DSP parts, memory) of a system-on-chip (SoC), the design is partitioned. The method is especially suited if the design consists of regular structures (multiprocessor design, vector-DSP). The results of the design partitioning are used to determine significant parameters of a generic emulator environment implemented on a state-of- the-art FPGA platform. The benefits are a decreasing number of run time reconfigurations and an improved utilization of the FPGA resources. View full abstract»

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  • Rapid Prototyping of Intrusion Detection Systems

    Page(s): 106 - 112
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    Designing security softwares that evolve as quickly as threats is a truthful challenge. In addition, current software becomes increasingly more complex and difficult to handle even for security experts. Intrusion Detection Softwares (IDS) represent a solution that can alleviate these concerns. This paper proposes a framework to automatically build an effective online IDS which can check if the program's expected behavior is respected during the execution. The proposed framework extracts relevant information from the program's source code to build a dedicated IDS. We use the GCC compiler to produce the structure of our behavior's model and ensure the IDS is correct. Thanks to Petri nets, our framework allows program offline monitoring and simplifies the online monitoring development. View full abstract»

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  • Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels

    Page(s): 113 - 122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (331 KB) |  | HTML iconHTML  

    Multimedia applications require heterogeneous multiprocessor architectures with specific I/O components in order to achieve computation and communication performances. The different processors run different software stacks made of the application code and the hardware dependent software layer. Developing this software usually makes use of a high level programming environment that does not handle specific architecture capabilities. We propose abstract software development platforms allowing to debug incrementally the different software layers and able to accurately estimate the use of the resources of the architecture. The software development platform is an abstract model of the architecture allowing to execute the software with detailed hardware-software interaction, performance measurement and software debug. Different software development platforms are generated automatically from an initial Simulink model and are used to debug the different software components and to easily experiment with several mappings of the application onto the platform resources. In this paper we apply the proposed approach on a multimedia platform, involving a high performance DSP and a RISC processor, to validate the executable code for a MJPEG decoder application. View full abstract»

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