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12th IEEE European Test Symposium (ETS'07)

Date 20-24 May 2007

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Displaying Results 1 - 25 of 45
  • 12th IEEE European Test Symposium - Cover

    Publication Year: 2007, Page(s): c1
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  • 12th IEEE European Test Symposium - Title page

    Publication Year: 2007, Page(s):i - iii
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  • 12th IEEE European Test Symposium - Copyright notice

    Publication Year: 2007, Page(s): iv
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  • 12th IEEE European Test Symposium - TOC

    Publication Year: 2007, Page(s):v - viii
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  • Foreword

    Publication Year: 2007, Page(s): ix
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  • Organizing Committee

    Publication Year: 2007, Page(s):x - xi
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  • Steering Committee

    Publication Year: 2007, Page(s): xii
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  • Program Committee

    Publication Year: 2007, Page(s): xii
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  • ETS 2006 Paper Award

    Publication Year: 2007, Page(s): xiii
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  • Test Technology Technical Council

    Publication Year: 2007, Page(s): xiv
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  • If It's All about Yield, Why Talk about Testing?

    Publication Year: 2007, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (170 KB)

    This talk will discuss the evolution of test and diagnosis, in the broad sense, over the recent years as well as the outlook into the future. Test, as it was only recently a pure discriminator between good and bad, has gained significant more added value by acting also a feedback loop towards the manufacturing process of integrated circuits. Of course, this feedback loop was already there, but was... View full abstract»

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  • Electronics Design-for-Test: Past, Present and Future

    Publication Year: 2007, Page(s): 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (166 KB)

    Summary form only given. Do you know how many ENIAC vacuum tubes were replaced every day during its heyday? What did it teach us about Test, or design-for-test? did Eldred really invent the stuck-at fault model in 1959? Is 99.999% fault cover all it's cracked up to be or are we fooling ourselves? Are we better off with 115% or even 80%? Where did Design-For-Test come from? Where is it now? Where's... View full abstract»

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  • Adaptive Debug and Diagnosis without Fault Dictionaries

    Publication Year: 2007, Page(s):7 - 12
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (242 KB) | HTML iconHTML

    Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are ... View full abstract»

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  • DERRIC: A Tool for Unified Logic Diagnosis

    Publication Year: 2007, Page(s):13 - 20
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (270 KB) | HTML iconHTML

    This paper presents DERRIC (Diagnosis of logic ERRors in VLSI Integrated Circuits), a diagnostic tool targeting most of the fault models used in practice today. This tool is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The underlying method of DERRIC is based on the Effect-Cause appr... View full abstract»

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  • A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter

    Publication Year: 2007, Page(s):21 - 28
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    One of the main problems when developing analog filters in VLSI is to achieve high accuracy regarding the cutoff frequency. This is mainly due to the difficulty in obtaining accurate time constants. Testing of such filters is also challenging, in the sense that special equipment is required. Small deviations in the resistor or capacitor values may lead to a very high mismatch between the expected ... View full abstract»

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  • Test Configurations for Diagnosing Faulty Links in NoC Switches

    Publication Year: 2007, Page(s):29 - 34
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (242 KB) | HTML iconHTML

    The paper proposes a new concept of diagnosing faulty links in network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The main novel contribution of this paper is to... View full abstract»

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  • Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints

    Publication Year: 2007, Page(s):35 - 42
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (295 KB) | HTML iconHTML

    In this paper, two wrapper designs are proposed for core- based test application based on Networks-on-Chip (NoC) reuse. It will be shown that the previously proposed NoC wrapper does not efficiently utilize the NoC bandwidth, which may result in poor test schedules. Our wrappers (Type 1 and Type 2) complement each other to overcome this inefficiency while minimizing the overhead. The Type 2 wrappe... View full abstract»

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  • FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests

    Publication Year: 2007, Page(s):43 - 48
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (827 KB) | HTML iconHTML

    Standard automated test equipment (ATE) for radio frequency (RF) transceiver production testing of today is limited by digital signal processing and data transfer. These constraints can be considerably relaxed by the application of new technology based on field programmable gate array (FPGA). The methods proposed are capable of handling all tasks flexibly and at-speed. FPGA hardware resources are ... View full abstract»

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  • Digital Generation of Signals for Low Cost RF BIST

    Publication Year: 2007, Page(s):49 - 54
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB) | HTML iconHTML

    RF test signals are a requirement for the implementation of effective BIST techniques in transceivers. In this work a method to encode a binary signal with the desired RF frequency is presented. The approach employs high-pass sigma delta modulators, in contrast to conventional low- pass or band-pass approaches, allowing signal generation close to the Nyquist limit of FS/2 (FS=sampling frequency). ... View full abstract»

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  • Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives

    Publication Year: 2007, Page(s):55 - 62
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (458 KB) | HTML iconHTML

    This paper describes a variance reduction technique for supply ramp test method. The technique makes use of multiple current measurements from a single device under similar test conditions to generate robust test limits with lower variance. The necessary conditions that guarantee variance reduction under these circumstances have also been described. We demonstrate that variance reduction has an ad... View full abstract»

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  • Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips

    Publication Year: 2007, Page(s):63 - 68
    Cited by:  Papers (5)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    Dependability is an important attribute for microfluidic biochips that are used for safety-critical applications such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore, these devices must be adequately tested after manufacture and during bioassay operations. Moreover, since disposable biochips are being targeted for a highly competitive and low-cost mar... View full abstract»

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  • Communication-Centric SoC Debug Using Transactions

    Publication Year: 2007, Page(s):69 - 76
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (555 KB) | HTML iconHTML

    The growth in system-on-chip complexity puts pressure on system verification. Due to limitations in the pre-silicon verification process, errors in hardware and software slip through to the stage when silicon and the complete software stack are first brought together. Finding the remaining errors at this stage is becoming increasing difficult. We propose that debugging should be communication-cent... View full abstract»

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  • Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

    Publication Year: 2007, Page(s):77 - 84
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB) | HTML iconHTML

    The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.1... View full abstract»

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  • PPM Reduction on Embedded Memories in System on Chip

    Publication Year: 2007, Page(s):85 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB) | HTML iconHTML

    This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together with the traditional tests at "Design of Systems on Silicon (DS2)" in Spain in order to (a) validate the used fault models and (b) investigate the added value of the new tests and their ... View full abstract»

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  • An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy

    Publication Year: 2007, Page(s):91 - 96
    Cited by:  Papers (37)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (709 KB) | HTML iconHTML

    An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare rows and columns (2D redundancy). To avoid the storage of large failure bitmaps needed by classical algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either follow very simple ... View full abstract»

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