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# Electrical Performance of Electronic Packaging, 1996., IEEE 5th Topical Meeting

## Filter Results

Displaying Results 1 - 25 of 71
• ### Analysis and results of net coupling within a high performance microprocessor

Publication Year: 1996, Page(s):36 - 38
Cited by:  Papers (1)
| | PDF (272 KB)

The trends in CMOS chip design have all been converging to worsen coupling between horizontally and vertically adjacent wires. The coupling between on chip wires can cause two different types of problems, namely, functional fails due to the induced coupled noise voltage, and changes in delay due to the changes in load capacitance caused by switching the activity of adjacent wires. A methodology ba... View full abstract»

• ### High speed bus design using HSPICE optimization techniques based on the worst case design approach

Publication Year: 1996, Page(s):93 - 96
Cited by:  Papers (1)
| | PDF (252 KB)

In this paper, a deterministic “worst case” design approach based on the HSPICE technique for the interconnect and package optimization of high speed digital circuits is presented. The HSPICE technique is based on using user-defined parameters to central component values and trace dimensions and specifying optimization parameters. To demonstrate the technique, an example of a high spee... View full abstract»

• ### Wiring rule methodology for on-chip interconnects

Publication Year: 1996, Page(s):33 - 35
Cited by:  Papers (2)
| | PDF (256 KB)

A wiring rule methodology which controls line to line signal coupling and transition rate degradations is described Technology trends are discussed and parametric curves presented which illuminate optimized wire geometries that are used to satisfy these electrical constraints for high wire density CMOS chips View full abstract»

• ### Reduction of power and ground noise coupling in mixed signal modules

Publication Year: 1996, Page(s):90 - 92
Cited by:  Papers (4)
| | PDF (260 KB)

By the full-wave electromagnetic field simulation, the effectiveness of certain measures to reduce the power and ground noise coupling in mixed signal modules is investigated. Segmentation of power and ground planes and proper placement of decoupling capacitors for the reduction of noise coupling are evaluated View full abstract»

• ### Wideband 2N-port S-parameter extraction from N-port S-parameter data

Publication Year: 1996, Page(s):150 - 152
Cited by:  Papers (2)
| | PDF (164 KB)

A complete characterization of an N-lead package, like a QFP, is a 2N×2N matrix of parameters, but measurements on all 2N ports can be difficult. The paper presents a technique for extracting the 2N×2N matrix from multiple N-port data sets View full abstract»

• ### Electrical characterization of multi-layer BGA packages for high speed, high switching activity applications

Publication Year: 1996, Page(s):114 - 116
| | PDF (220 KB)

With ever-increasing requirement for package performance, multi-layer BGA packages are gradually moving into mainstream. This trend represents a major challenge in package characterization because of the difficulty in modeling the complex interaction between signal traces and power/ground planes in a multi-layer package. An accurate package model encompassing both signal and power/ground is especi... View full abstract»

• ### Applications of the Taguchi method for optimized package design

Publication Year: 1996, Page(s):14 - 17
Cited by:  Papers (2)
| | PDF (308 KB)

A robust technique for noise and sensitivity analysis for packages in the system environment using the design of experiment (DOE) and orthogonal matrix array is presented. The use of DOE allows full factorial parametric analysis and the use of an orthogonal array significantly reduces the number of simulations. The results of noise and sensitivity analysis can be used to predict the noise and sens... View full abstract»

• ### Isolator-free DFB-LD module with TEC control using silicon waferboard

Publication Year: 1996, Page(s):71 - 73
Cited by:  Papers (1)
| | PDF (248 KB)

We realized an isolator-free DFB-LD module with thermo-electric cooler in aim of stabilizing the emission wavelength for WDM system. It demonstrated low noise response and stable emission wavelength characteristics under 156 Mbit/s pseudo-random modulation experiment View full abstract»

• ### Design guidelines for short, medium, and long on-chip interconnections

Publication Year: 1996, Page(s):30 - 32
Cited by:  Papers (10)
| | PDF (284 KB)

Short, medium and long on-chip interconnections having line widths of 0.7-52 μm are being analyzed in five-metal-layer structures. Design guidelines are formulated for local and global wiring in order to achieve minimum delay and contain crosstalk. The regime when inductive effects are significant is explained and the importance of resistive losses in the power buses is highlighted. The trend i... View full abstract»

• ### Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multi-layer ceramic BGA

Publication Year: 1996, Page(s):120 - 122
| | PDF (224 KB)

This paper presents the simultaneous switching noise measurements, modeling, and simulation of a flip-chip CMOS ASIC test chip on a multi-layer Ceramic Ball Grid Array (CBGA) package. The modeling technique is validated by strong correlation between measurement and simulation results View full abstract»

• ### Capacitance calculations of conical vias with thick conductors

Publication Year: 1996, Page(s):80 - 82
| | PDF (196 KB)

The capacitance of circulary symmetric vias constructed from conical shaped cylinders and thick conductors are studied. Results are compared with capacitance of vias with straight cylinders and infinitely thin conductors View full abstract»

• ### Effects of on-package decoupling on microprocessor power delivery design

Publication Year: 1996, Page(s):86 - 89
Cited by:  Papers (7)
| | PDF (316 KB)

On-package decoupling is evaluated for microprocessor power delivery on package and on core. Full-chip system modeling mechanics are introduced. On-die noise sensitivity to parameters associated with package design is analyzed View full abstract»

• ### Delta-I modeling approximation for single chip modules

Publication Year: 1996, Page(s):111 - 113
Cited by:  Papers (6)
| | PDF (232 KB)

In this paper the impact of the inductance path on the power plane of a representative single chip module for cost performance machines is quantified via loop inductance comparison and Delta-I noise simulations. In addition the impact of the inclusion of the via to pin mutual is investigated. Finally, a simplified model based on two dimensional analysis of the via and pin structure is compared wit... View full abstract»

• ### Impedance mismatch effects on propagation constant measurements

Publication Year: 1996, Page(s):141 - 143
Cited by:  Papers (10)
| | PDF (272 KB)

By measuring propagation constants of coplanar waveguide transmission lines, we show the significant systematic errors of common measurement techniques when the characteristic impedance of the lines does not match the reference impedance of the instrument View full abstract»

• ### Low-profile integrated antennas for mobile radio communications

Publication Year: 1996, Page(s):176 - 178
Cited by:  Papers (1)
| | PDF (288 KB)

This paper focuses on the development and characterization of low-profile and integrated antennas with enhanced bandwidth for mobile communications applications. Novel radiator configurations are studied by adding parasitic or tuning elements to some well-characterized integrated antennas View full abstract»

• ### High-frequency measurement based characterisation of the transmission line parameters of packages and interconnection structures

Publication Year: 1996, Page(s):67 - 70
Cited by:  Papers (2)
| | PDF (228 KB)

In this paper a technique is presented for high-frequency circuit modeling of coupled interconnection structures such as high-density connectors and large pin count electronic packages. The generated circuit model consists out of basic cells the number of which is function of the length and the bandwidth of the model. The problems associated with the modeling of a high number of coupled conductors... View full abstract»

• ### Microprocessor clock distribution

Publication Year: 1996
Cited by:  Papers (2)
| | PDF (84 KB)

Summary form only given. A microprocessor's clock distribution network provides a spine around which the performance is built. Clock skew penalizes the overall performance by adding to the maximum delay path. In addition it subtracts from minimum delay paths increasing the risk of a hold time failure. Uncompensated delay in the clock distribution shifts I/O timings, increasing output delays and ho... View full abstract»

• ### Authorindex

Publication Year: 1996, Page(s):241 - 242
| | PDF (80 KB)

First Page of the Article
View full abstract»

• ### Advanced hardware technologies for high speed switching and access applications in telecom

Publication Year: 1996, Page(s):41 - 42
| | PDF (164 KB)

The rapid evolution of broadband switching and access applications in telecom requires high density interconnection (HDI) and packaging technologies for product and system development in a cost-effective way with a short time to market, high performance, reliability and integration density. In order to keep technology evolution and product evolution in line, a Product and Technology' roadmap (PT... View full abstract»

• ### Attenuation in ribbon microstrip with and without dielectric cover

Publication Year: 1996, Page(s):97 - 99
| | PDF (176 KB)

Losses in a microstrip on polyimide with finite metal thickness with and without dielectric cover has been modelled using variational analysis in the FTD and the data has been compared with the measurements on crosstalk View full abstract»

• ### Transient analysis of single interconnects characterized with measured S-parameter data

Publication Year: 1996, Page(s):159 - 161
Cited by:  Papers (1)
| | PDF (252 KB)

The correct modeling of the transmission lines requires accurate modeling of both the frequency-dependent conductor (skin effect) and the dielectric losses. The measured S-parameter data can easily capture the behavior of these losses. The discontinuities in interconnects are difficult to describe with closed form equations. They are better characterized with the measured S-parameter data. The int... View full abstract»

• ### Improving the accuracy of thin film dielectric characterization using the Kalman filter

Publication Year: 1996, Page(s):77 - 79
| | PDF (224 KB)

Using an inverse method known as the Kalman filter on microstrip resonance measurements, calculations of dielectric constant and loss tangent can be improved compared to other methods and error bars better constrained View full abstract»

• ### Electrical performance of integrated decoupling capacitor arrays

Publication Year: 1996, Page(s):83 - 85
| | PDF (284 KB)

This paper deals with assessing the electrical performance of integrated decoupling capacitor arrays, which belong to a new generation of integrated passive components (IPCs). Quasi-static numerical analysis is carried out to obtain the effective lumped capacitance and inductance values for various combinations of excitation voltages applied to the multiterminal device. Complete capacitance matric... View full abstract»

• ### Development of a surface mountable plastic package characterization technique

Publication Year: 1996, Page(s):147 - 149
Cited by:  Papers (1)
| | PDF (204 KB)

We present a method to characterize surface mountable plastic packages and packaged chips. A novel thin-film alumina substrate has been developed to mount plastic packages. The substrate establishes RF interconnections from plastic packages to coplanar waveguide (CPW) microprobes via CPW to package adapters (CPA). CPA calibration standards were fabricated based on the LRM error correction techniqu... View full abstract»

• ### Numerical modeling of a clock distribution network for a superconducting multichip module

Publication Year: 1996, Page(s):43 - 45
| | PDF (284 KB)

As supercomputers continue to move towards more powerful processors and parallelization, fast switching structures to route data signals between processors and shared memory become essential, and in fact, may be a primary limiting factor in overall computational throughput. The fast switching network under consideration in this paper is a “crossbar” switch employing superconducting Jos... View full abstract»