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2007 Design, Automation & Test in Europe Conference & Exhibition

Date 16-20 April 2007

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Displaying Results 1 - 25 of 305
  • [Front cover]

    Publication Year: 2007, Page(s): C1
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  • [Breaker page]

    Publication Year: 2007, Page(s): 1
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  • [Breaker page]

    Publication Year: 2007, Page(s): 1
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  • Table of contents

    Publication Year: 2007, Page(s):1 - 24
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  • Contributor listings

    Publication Year: 2007, Page(s):1 - 8
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  • Reviewer listings

    Publication Year: 2007, Page(s):1 - 4
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  • [Opinion]

    Publication Year: 2007, Page(s):1 - 3
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  • Awards

    Publication Year: 2007, Page(s): 1
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  • Tutorial

    Publication Year: 2007, Page(s):1 - 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    Provides an abstract of the tutorial presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • [Society related material]

    Publication Year: 2007, Page(s):1 - 2
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  • Call for papers

    Publication Year: 2007, Page(s): 1
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  • Challenges of Digital Consumer and Mobile SoC's: More Moore Possible?

    Publication Year: 2007, Page(s): 1
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (34 KB)

    Digital consumer and mobile products have continuously accommodated more features and functions. For example, the recent high-end cellular phones can operate as terrestrial digital TV viewers, MP3 music players, digital cameras, substitutes of credit cards and many more in addition to multi-modal wireless communication terminals that handle various formats; GSM, 3G, BT, WiFi and so on. These produ... View full abstract»

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  • Was Darwin Wrong? Has Design Evolution Stopped at the RTL Level... or Will Software and Custom Processors (or System-Level Design) Extend Moore's Law?

    Publication Year: 2007, Page(s): 2
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (34 KB)

    The challenges of electronic design are escalating as software and embedded processors are fast becoming a more dominant component of electronic products. Software is now acknowledged as the most effective way for electronics companies to differentiate their products. But what if the processors running the software aren't up to the task? Electronics companies are increasingly adopting a new system... View full abstract»

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  • ATLAS: A Chip-Multiprocessor with Transactional Memory Support

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (13)  |  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (8051 KB) | HTML iconHTML

    Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded application development for such systems. Transactional memory (TM) promises to simplify concurrency management in multithreaded applications by allowing programmers to specify coarse-grain parallel tasks, while achieving perfo... View full abstract»

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  • A dynamically adaptive DSP for heterogeneous reconfigurable platforms

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (17)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (124 KB) | HTML iconHTML

    This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero overhead for switching between successive configurations, relevant... View full abstract»

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  • An 0.9 x 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (6997 KB) | HTML iconHTML

    Presented is a self-powered computing system, sunflower, that uses a novel combination of a PIN photodiode array, switching regulators, and a supercapacitor, to provide a small footprint renewable energy source. The design provides software-controlled power-adaptation facilities, for both the main processor and its peripherals. The system's power consumption is characterized, and its energy-scaven... View full abstract»

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  • An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (16)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (316 KB) | HTML iconHTML

    This paper presents the architecture and implementation of an all-digital transmitter with radio frequency output targeting an FPGA device. FPGA devices have been widely adopted in the applications of digital signal processing (DSP) and digital communication. They are typically well suited for the evolving technology of software defined radios (SDR) due to their reconfigurability and programmabili... View full abstract»

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  • A Non-Intrusive Isolation Approach for Soft Cores

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (262 KB) | HTML iconHTML

    Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed coverage on the core inte... View full abstract»

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  • Unknown Blocking Scheme for Low Control Data Volume and High Observability

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (7)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (159 KB) | HTML iconHTML

    This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and also increase the number of scan cells that are observed by the temporal compactors. Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. In this ... View full abstract»

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  • Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (202 KB) | HTML iconHTML

    A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed in this paper. A broadcast scan based test compression algorithm for parallel testing of cores with multiple scan chains is used to reduce the test data of the SoC. Unlike other test compression schemes, the proposed algorithm doesn't require specialized test generation ... View full abstract»

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  • High-Level Test Synthesis for Delay Fault Testability

    Publication Year: 2007, Page(s):1 - 6
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (222 KB) | HTML iconHTML

    A high-level test synthesis (HUTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embedded modules, guarantees 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay fault coverage is usually attributed to the fact that two-... View full abstract»

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  • Bus Access Optimisation for FlexRay-based Distributed Embedded Systems

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (12)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (166 KB) | HTML iconHTML

    FlexRay will very likely become the de-facto standard for in-vehicle communications. Its main advantage is the combination of high speed static and dynamic transmission of messages. In the previous work the authors have shown that not only the static but also the dynamic segment can be used for hard-real time communication in a deterministic manner. This paper proposed techniques for optimising th... View full abstract»

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  • A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (135 KB) | HTML iconHTML

    The paper presents a decomposition strategy to speed up constraint optimization for a representative multiprocessor scheduling problem. In the manner of Benders decomposition, our technique solves relaxed versions of the problem and iteratively learns constraints to prune the solution space. Typical formulations suffer prohibitive run times even on medium-sized problems with less than 30 tasks. Ou... View full abstract»

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  • Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (233 KB) | HTML iconHTML

    Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in high level synthesis. Delay relaxation that assigns extra clock latencies to functional resources at RTL (register transfer level) can be leveraged. This paper proposed a general formulation for design closure driven delay ... View full abstract»

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  • Simulation-based reusable posynomial models for MOS transistor parameters

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1696 KB) | HTML iconHTML

    The paper presents an algorithm to automatically design posynomial models for parameters of the MOS transistors using simulation data. These models improve the accuracy of the geometric programming flow for automatic circuit sizing. The models are reusable for multiple circuits on a given silicon technology and hence don't adversely affect the scalability of the geometric programming approach. The... View full abstract»

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