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Reliability Physics Symposium, 1975. 13th Annual

Date 1-3 April 1975

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Displaying Results 1 - 25 of 44
  • [Covers]

    Page(s): C1
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    Freely Available from IEEE
  • Management Committee

    Page(s): ii
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    Freely Available from IEEE
  • Copyright page

    Page(s): ii
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    Freely Available from IEEE
  • Table of contents

    Page(s): iii - vii
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    Freely Available from IEEE
  • P-Channel Rewritable Avalanche Injection Device (RAID) Operation and Degradation Mechanisms

    Page(s): 1 - 5
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    To implement an electrically rewritable device for Read Mostly Memory applications, the structure of the FAMOS device is modified by incorporating an additional metal gate on top of the floating polysilicon gate and separated from it by a specially grown thermal oxide. Electrical erasure is accomplished by applying a positive voltage pulse to the metal gate. The "write" voltage has been lowered by using ion implantation. Reliability and charge retention are discussed and their impact on the design of the device is assessed. An empirical model for the conduction of oxide between the floating gate and the metal gate is developed and results are projected and compared with data obtained on the device. View full abstract»

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  • Degradation Mechanisms in Rewritable N-Channel FAMOS Devices

    Page(s): 6 - 9
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    Electrically rewritable n-channel FAMOS devices were fabricated with a floating polycrystalline silicon gate and an Al control gate. The Al gate is used to control injection of holes or electrons from the avalanching drain diffusion onto the floating gate. Charge retention by the floating gate and device degradation due to multiple write/erase cycling is discussed. View full abstract»

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  • A Study of the Dielectric Breakdown of Thermally Grown SiO2 by the Self-Quenching Technique

    Page(s): 10 - 14
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    The dielectric breakdown of SiO2 films thermally grown on (100) silicon substrates was studied by the self-quenching technique, using thin aluminum field plates. The breakdown regions show distinct differences among the four possible combinations of substrate type and polarity of applied voltage. With p-type substrate and positive field-plate polarity, an anisotropy is observed which reflects the crystallo-graphic structure of the substrate. A pre-breakdown instability, which is enhanced at lowered temperatures, is ascribed to hole-electron pair production in the oxide followed by hole trapping at or near the negative electrode. View full abstract»

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  • Sodium Ions at Defect Sites at SiO2/Si Interfaces as Determined by X-Ray Photoelectron Spectroscopy

    Page(s): 15 - 25
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    X-ray photoelectron spectroscopy (XPS) is described in its application as a probe for studying defects such as sodium in SiO2 films. A general description is given of key experimental methods in XPS. New techniques are described for applying and monitoring a fixed bias at the surface of the oxide during the XPS measurement. These methods are shown capable of detecting extremely small Na and Cu concentrations in undoped samples (< 1011 cm¿2). In deliberately Na-doped samples, five spectral peaks are distinctly observed and related to different defect states at the vacuum/SiO2 and SiO2/Si interfaces. By applying a bias-temperature stress during the XPS measurements, these peaks change in relative intensity and can be related to the motion of the Na+ ions between different states occurring at the two interfaces. An attempt is made to correlate the observations with previously reported models. View full abstract»

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  • Tunnel Injection into Gate Oxide Traps

    Page(s): 26 - 33
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    An experimental method is described for measuring the density of oxide traps in the gate oxide of an MOS transistor as a function of energy and position near the silicon interface. Measurements are obtained from different oxide growth processes and after Co60 irradiation. The results are related to long-term drift of threshold voltage. View full abstract»

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  • SOS Island Edge Profiles Following Oxidation

    Page(s): 34 - 37
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    A study of silicon and oxide profiles at the edges of silicon islands etched in silicon-on-sapphire (SOS) has shown that, following thermal oxidation of the silicon, a " V"- shaped groove forms between the silicon dioxide grown on the island edge and the sapphire substrate. This groove can cause etching and metal coverage anomalies at the island edges resulting in poor circuit yield and reliability. View full abstract»

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  • Rectangular Flat-Pack Lids Under External Pressure: Formulas for Screening and Design

    Page(s): 38 - 47
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    Formulas are presented for the maximum tensile stresses in the lid seal and the maximum lid deflections of a rectangular flat-pack under external pressure. These formulas can facilitate (a) the proper design of the package so that it will retain its hermeticity under a given screening pressure and (b) the selection of a proper pressure to use in the hermeticity screening of an already designed package. Information is also given on the approximate equivalence of external pressure and centrifuge acceleration in regard to the seal stresses and lid deflections of a rectangular flat-pack. View full abstract»

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  • A Test of Parylene as a Protective System for Microcircuitry

    Page(s): 53 - 57
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    Parylene has been suggested for use and, in some cases, is used as a protective system for electronic components and assemblies, such as microcircuits. unfortunately, the amount of environmental test data for such parylene-protected components is quite limited and, to the authors' knowledge, almost no long-term test data exists. The principal objective of the test program reported in this paper was to determine whether it is at all reasonable to use parylene as a protective system for microcircuits in place of a hermetic seal in high-reliability equipment. A radiation-hardened circuit containing nichrome resistors was selected as a test specimen because of its considerable sensitivity to humidity-induced failure. The ceramic encased circuits were mounted on carrier cards, delidded, and coated with parylene C at three different facilities (Vendors A, B, and C). The cleaning cycle, the adhesion promotor, and the thickness of the parylene coating appifed differed from vendor to vendor, depending on the practices considered appropriate by the particular coating facili-ty at the time. The circuits were operated in a ring-counter configuration during humidity tests. Nonparylened units both with and without lids were also tested as controls, and other parylene-coated control units were kept in a dessicator. Units which had been coated by Vendor C had a hifgher failure rate than even the unprotected units. This is attributed to the adhesion promoter used. The failure modes exhibited by Vendor-C parts were: (1) Nichrome voiding at the nichrome/aluminum interface. (2) Nichrome voiding in the bulk of the nichrome resistors. View full abstract»

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  • The Degradation of Bonding Wires and Sealing Glasses with Extended Thermal Cycling

    Page(s): 58 - 69
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    The purpose of this investigation was to determine if there was a detrimental effect on internal bonded wires of ceramic dual-in-line and ceramic flat packages, which had been subjected to thermal cycling for up to 1000 cycles. Several manufacturers' parts were used - three ceramic dual-in-line packages (CDIP) and two flat packages. All parts were stressed to MIL-STD-883, Method 1010, Condition C (¿65°C. to +150°C) or Method 1011, Condition C. Samples were removed at various steps throughout the cycling program. All parts were decapped and wires pulled. Pull strength and failure locations were recorded. This investigation indicated that end-of-life due to temperature cycling, can be observed to start within 1000 cycles, but due to the slow mean degradation rate, the calculated mean cycles to failure is very large (>1018 cycles). Thermal shock cause much less degradation of the wire bond strengths than did temperature cycling at this condition C level. The results show that Method 1010-C does cause slight degradation in mean pull strength, almost no degradation in maximum value observed, and extensive degradation to lowest values observed. Zero wirepull strengths were obtained after 240 temperature cycles and "percent fail less than 0.5 gram-force" increases significantly with increasing cycles from 240 to 1000. The purpose of the second part of this investigation was to determine if there was a degradation in CERDIP sealing glass strength of parts subjected to 1000 cycles of MIL-STD-883, Method 1011, Condition A (0 - 100°C) Thermal Shock. View full abstract»

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  • Susceptibility of Microweids in Hybrid Microcincuits to Corrosion Degradation

    Page(s): 70 - 79
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    Analysis of broken ultrasonic Al-Ag bonds involving SEM electron microprobe, ion microprobe, and Auger electron spectroscopy indicated that failure was due to corrosion. Subsequent environmental tests demonstrated that Al-Ag bonds are highly susceptible to corrosion, but Al-Au and Au-Al bonds are less so. No evidence of corrosion of Au-Ag bonds was found. View full abstract»

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  • Effects of Intermetallics on the Reliability of Tin Coated Cu, Ag, and Ni Parts

    Page(s): 80 - 86
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    The temperature dependence of the growth rates of intermetallic compounds in the Cu-Sn, Ag-Sn and Ni-Sn systems was determined between 100°C and 213°C for Sn-dipped and Sn-plated samples. Below 175°C the fastest growing intermetallic compound was Ag3Sn. The Ni-Sn compoknd, Ni3Sn, was the slowest growing phase below 150°C, but the fastest growing phase above 175°C. The two Cu-Sn intermetallic phases, Cu3Sn and Cu6Sn5, had a combined growth rate which increases more slowly with temperature than the single intermetallic phases observed in the Ni-Snand Ag-Sn systems. The growth rate data plotted against reciprocal temperature satisfies the Arrhenius relationship and yields a range of apparent activation energies between 14.8 Kcal/mole for Ag3Sn and 37.6 Kcal/mole for Ni3Sn4. The growth of intermetallic compounds can affect the reliability of electronic parts through a reduction in lead solderability or a decrease in the mechanical strength of soldered connections. Lap shear testing of metal strips bonded with Sn demonstrated that strengths of both bonded Ni and Cu strips decrease as the thickness of the intermetallic compounds increase during annealing at 213°C. In the case of Ni-Sn, a 50% reduction in joint strength occurred after only one day-at temperature. For Cu-Sn, the reduction in joint strength occurred at a slower rate, and only a slight decrease was observed in the Ag-Sn lap shear samples. The degradation observed in the Ni-Sn and Cu-Sn systems is related to the growth rate of brittle intermetallics forming at the interface (i.e. Ni3Sn4 and Cu3Sn). View full abstract»

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  • Reliability Evaluation of Hermetic Integrated Circuit Chips in Plastic Packages

    Page(s): 87 - 92
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    Previous studies of the basic failure mechanisms of conventional plastic-encapsulated integrated circuits have led to improvements in materials and processes which have yielded two orders of magnitude improvement in reliability. Additionally, it has been demonstrated that, where severe environmental conditions are encountered, enhanced reliability is provided by device surfaces passivated with a silicon nitride dielectric and metallized with a titanium, platinum, gold interconnecting system. Failures associated witlh gold electro-plating under severe humidity-bias conditions are avoided by the deposition of a dielectric layer over tlle metallizationi pattern. Subsequent thermal, electrical, and moisture stress testinig his confirmed earlier indications that predicted lifetimes greater than 107 hours can be anticipated for these types of initegrated circuits when they are operated at a maximuim rated temperature of 125°C. An automated duial-in-linle-package assembly system has been evaluated that provides plastic packages in which the convenitional wire bonds have been eliminated and replaced with thermocom-pression bonds of metal beams to both the device and the lead-frame bond sites. The advantages gained from this type of assembly system are discussed. View full abstract»

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  • Migrated-Gold Resistive Shorts in Microcircuits

    Page(s): 93 - 98
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    Failures, failure modes and failure mechanisms related to the formation of migrated-gold resistive shorts (MGRS) in gold-metallized microcircuits will be described. Also, three different methods of screening devices for MGRS will be presented and the impact MGRS can have on device reliability will be discussed. View full abstract»

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  • Migratory Gold Resistive Shorts: Chemical Aspects of a Failure Mechanism

    Page(s): 99 - 106
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    Integrated-circuit devices using the Ti/W/Au metal system are subject to failure mechanisms based on electrolytic corrosion. The migratory gold resistive short (MGRS) failure mode is one example of this mechanism and results in the formation of filamentary or dendritic deposits of gold between adjacent stripes. on the IC chip. This reaction requires the presence of a sufficient amount of water, a bias voltage between adjacent stripes, and the activation of the cathodic (-) stripe. Gold ions are transported from anode to cathode through a film of moisture adsorbed on the surface of the chip; halide ions are probably involved in the transfer. Their presence is verified experimentally by x-ray photoelectron spectroscopy. Some of the chemical and electrostatic factors involved in the MGRS mechanism are discussed in this paper, including the questions of a threshold level of moisture and contamination. View full abstract»

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  • Electromigration Failure in Au Thin-Film Conductors

    Page(s): 107 - 112
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    Experiments are carried out to understand the electromigration-induced failure mechanism in thin-film Au conductors. The activation energy for the atom transport and the magnitude of the current exponent In the failure equation are obtained. The role of surface coverage on the reliability of AU stripes is studied. The underlying mode of atom transport and the possible sources of flux divergences are discussed in terms of these results. View full abstract»

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  • Effects of Fast Temperature Cycling on Aluminum and Gold Metal Systems

    Page(s): 113 - 120
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    Microwave power transistors in a radar-system may undergo ~ 1011 fast heating and cooling cycles during lifetime. Controlled temperature cycling tests have been carried out on Al, passivated Al, and gold metallization systems using both a special test pattern and commercially available transistors. Significant visible and electrical changes were observed for Al, glassed Al and a laboratory Ta-Pt-Ta-Au system, but not for a commercial gold transistor. View full abstract»

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  • Induced Passivation Defect Study

    Page(s): 121 - 127
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    An n-channel FET memory array chip whose quartz passivation layer is purposely disrupted in specific-nonrandom locations is used to study the propensity of these induced defects to fail due to localized inversion of the silicon surface stemming from positive ions contained within the defect which are residual from processing. Two distinct sizes of induced defects are considered; three and seven micron diamters; 800 of the larger size and 100 of the smaller. Vertical structures range from shallow indentations to holes completely-through the passivation layer thus exposing the underlying silicon. Positive ionic contamination is introduced into the defects via an overcoat of photoresist whose positive ionic species and levels are known. Accelerated temperature and voltage life stresses are performed. Temperatures employed are 85 and 150°C, while voltage levels (and E field) across the defect are nominal and twice nominal. Data obtained from these temperature/voltage accelerated stresses is presented which shows time-to-fail is related to the ionic (mostly sodium) levels contained within the defects. Voltage acceleration was found to be a nonlinear function while temperature follows the standard Arrhenius model with an activation energy of 1.1 eV. Hole size was found to be at best a second order effect on time-to-fail. High temperature no bias bake-out at 150°C for 48 hours was performed. Percent inversion is seen to decrease by approximately an order of magnitude in all cases. View full abstract»

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  • Analysis of Deposited Glass Layer Defects

    Page(s): 128 - 135
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    This paper reviews the results of deposited glass layer analysis carried out during device failure analysis and characterization studies performed at the Rome Air Development Center. The Scanning Electron Microscope (SEM) was used as the principal analysis technique for this study. The variables under consideration were glass deposition method, device interconnect metallurgy, package type and device stress conditions. The effects of glass layer defects on device reliability are discussed along with qualification and screen tests aimed at eliminating batch-related problems. View full abstract»

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  • Failure Mechanism of Metal-Polysilicon-Doped Silicon Butting Contacts

    Page(s): 136 - 141
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    The metal-polysilicon-doped silicon butting contact is presently widely used in MOS silicon gate integrated circuits because it occupies minimum area on the chip and does not require additional photolithography. A possible failure mechanism of this contact with self-aligned, ion-implanted sources and drains has been observed. Recent data obtained on processes used to fabricate two-phase, two-level polysilicon CCDs are presented. Results show that oxide etching under the edges of the polysilicon gate during contact window definition can lead to excessive leakage due to metal-to-substrate shorts at the metal-polysilicon-doped silicon butting contact. View full abstract»

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  • An Electrical Technique for the Measurement of the Peak Junction Temperature of Power Transistors

    Page(s): 142 - 150
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    A technique is described which uses straightforward electrical measurement procedures to determine the peak junction temperature of power transistors. To determine the peak temperature, standard electrical measurement techniques are altered to account for the difference between the distributions of the calibration and measurement currents in the active area of the device. For relatively uniform temperature distributions, the electrically determined peak junction temperature is only about 6% or less below the infrared measured peak temperature whereas the standard electrically measured temperature is about 10 to 25% below the infrared measured peak temperature. For severely non-uniform temperature distributions, when only about 20% of the total active area of the device is dissipating power at steady state, the electrically determined peak temperature is within 11% of the infrared measured peak temperature while the standard electrically measured temperature is more than 40% below the infrared measured peak temperature. Device operating conditions for which the junction temperature as determined by standard electrical methods, infrared techniques, and the electrical peak temperature technique equals the manufacturer's specified maximum safe operating temperature are compared with one another and with the manufacturer's specified safe operating limits. It is suggested that the electrical peak temperature technique can be used to generate more realistic safe operating area limits and to determine the validity of specified safe operating limits of power transistors. View full abstract»

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