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2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors

Date 10-13 Oct. 2006

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  • [Front cover]

    Publication Year: 2006, Page(s): C1
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  • 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors RTP 2006

    Publication Year: 2006, Page(s): nil1
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  • [Copyright notice]

    Publication Year: 2006, Page(s): nil2
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  • Conference Chair

    Publication Year: 2006, Page(s): nil3
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  • IEEE RTP 2006

    Publication Year: 2006, Page(s):nil5 - nil9
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  • Call for papers

    Publication Year: 2006, Page(s): nil10
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  • 15th IEEE International Conference on Advanced Thermal Processing of Semiconductors RTP 2007

    Publication Year: 2006, Page(s): nil11
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  • RTP Conference Achievement Awards

    Publication Year: 2006, Page(s):nil12 - nil13
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  • [Commentary]

    Publication Year: 2006, Page(s): nil14
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  • Awards

    Publication Year: 2006, Page(s): nil15
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  • [Breaker page]

    Publication Year: 2006, Page(s): nil17
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  • Process-Integration Challenges with Up-To-Date Modulation of Scaling Laws

    Publication Year: 2006, Page(s):1 - 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (954 KB) | HTML iconHTML

    CMOS scaling laws have already lost the physical bases, and the merest results induced by scaling laws are still utilized for requirements from technology users. In this paper, the actual situation of CMOS shrinkage and a forecast are discussed View full abstract»

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  • Growing Importance of Fundamental Understanding of the Source of Process Variations

    Publication Year: 2006, Page(s):5 - 9
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB) | HTML iconHTML

    Statistical process control (SPC) has been widely practiced as a quality control method in the semiconductor industry. SPC is a system for monitoring, controlling, and improving a process through statistical analysis of monitored data. Control charts are widely used for process monitoring, but they are often misinterpreted. To improve process capability, the source of process variations must be pr... View full abstract»

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  • Laser Annealing Technology and Device Integration Challenges

    Publication Year: 2006, Page(s):11 - 14
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1836 KB) | HTML iconHTML

    We have shown impacts of halo and deep source/drain (S/D) junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance and reduced hot carrier degradation compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. Gate pre-annealing by laser thermal proces... View full abstract»

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  • Influence of the Atmosphere on Ultra - Thin Oxynitride Film for Precisely Controled Plasma Nitridation Process

    Publication Year: 2006, Page(s):15 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1219 KB) | HTML iconHTML

    Influence of the atmosphere on ultra-thin oxynitride film was investigated for the precisely controlled plasma nitridation process. Some organic contaminant adsorb on the wafer before plasma nitridation process in clean room atmosphere. The adsorbed organic contaminant reduces the efficiency of plasma nitridation and increases the electrical thickness. The TDDB characteristic of ultra-thin oxynitr... View full abstract»

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  • Double-Pulsed Laser Annealing Technologies and Related Applications

    Publication Year: 2006, Page(s):21 - 29
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4288 KB) | HTML iconHTML

    New applications of the double-pulsed laser annealing (DPLA) technologies were opened up in the coming-generation high-performance devices: insulated gate bipolar transistors (IGBTs) and low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). The DPLA system was equipped with two solid-state lasers of a green wavelength as pulse laser sources. The line-beam irradiation was done ... View full abstract»

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  • Ni-Silicide/Si and SiGe(C) Contact Technology for ULSI Applications

    Publication Year: 2006, Page(s):31 - 37
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2273 KB) | HTML iconHTML

    We have investigated the crystalline and electrical properties of Ni silicide/Si and SiGeC contacts for ULSI applications. NiSi/Si contacts promises the contact resistivity as low as 10-8 Omegacm2 for both n+- and p+-Si. Degradation of the sheet resistance of NiSi layers critically depends on the annealing time particularly at temperatures ranging from 650degC to 750degC. The... View full abstract»

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  • Ultra-Shallow Junction Formation by Plasma Doping and Flash Lamp Annealing

    Publication Year: 2006, Page(s):39 - 46
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3013 KB) | HTML iconHTML

    Ultra-shallow P+/N junctions were formed by boron doping using plasma doping method combined with activation annealing using spike-RTA, flash lamp annealing or laser annealing. The junctions formed with flash lamp annealing or laser annealing were promising and superior to those formed by conventional low energy ion implantation method from the viewpoints of shallowness, abruptness and ... View full abstract»

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  • Millisecond Annealing with Flashlamps: Tool and Process Challenges

    Publication Year: 2006, Page(s):47 - 55
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1632 KB) | HTML iconHTML

    Sub-second annealing is one of the key issues to meet the requirements of the 45 nm technology node according to the ITRS roadmap. Therefore, over the past decade there has been great interest in techniques such as laser and flash lamp annealing (FLA). In addition, advanced ultra-fast annealing shows promise for technologies that are not directly related to Si device processing. The main reason fo... View full abstract»

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  • The Progress in Ultra Thin Gate Dielecgtric for System LSI Application

    Publication Year: 2006, Page(s):57 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1791 KB) | HTML iconHTML

    EOT reduction is a key challenge to keep the Moore's law, especially in low power LSIs. Nice candidates of gate dielectric as alternative to conventional SiO2 are N-rich SiON and high-K. However, in each case, we truly need tuning tools of Vth in the system LSI applications. F incorporation technique should be effective in Vth tuning with both N-rich SiON and high-K. Moreover, F incorpo... View full abstract»

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  • Flash Lamp Annealing Latest Technology for 45nm device and Future devices

    Publication Year: 2006, Page(s):65 - 71
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2637 KB) | HTML iconHTML

    FLA (flash lamp annealing) is used in 65nm generation devices manufacturing. For next 45nm and future generation devices, we have picked up 3 key subjects related to milli-second annealing: process controllability, S/D (source drain) activation, silicidation. No need to say, process controllability is very important for device manufacturing. And process requirement for S/D activation and silicidat... View full abstract»

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  • Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies

    Publication Year: 2006, Page(s):73 - 78
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2452 KB) | HTML iconHTML

    With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced gate poly depletion for a process that is essentially free of additional diffusion. This paper will focus on process integration issues during implemen... View full abstract»

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  • Ultra-shallow Junction Formed by Plasma Doping and Laser Annealing

    Publication Year: 2006, Page(s):79 - 83
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1581 KB) | HTML iconHTML

    We investigated ultra-shallow junction prepared by plasma doping (PLAD) and laser annealing (LA). Although PLAD is promising doping technology for the sub-45nm technology node due to the high dose rate at low energy, it has problems which is related with hydrogen or fluorine. The implanted hydrogen generally increases damage in the Si substrate. The fluorine also retards dopant activation and incr... View full abstract»

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  • Kinetics of Shallow Junction Activation: Physical Mechanisms

    Publication Year: 2006, Page(s):85 - 91
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4065 KB) | HTML iconHTML

    Forming highly active shallow junctions is a key component enabling low external resistance and high transistor performance. Millisecond flash or scanning laser anneals can be used to contain diffusion and optimize activation, either directly by leveraging temperatures exceeding 1200C, or in combination with non-equilibrium processes such as amorphization plus solid phase epitaxy or liquid phase e... View full abstract»

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  • Mechanical Stress in Silicon Based Materials: Evolution Upon Annealing and Impact on Devices Performances

    Publication Year: 2006, Page(s):93 - 102
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1952 KB) | HTML iconHTML

    An overview of the mechanical stress mechanisms observed within as deposited silicon oxide and nitride films deposited by the different techniques used for the CMOS transistors integration is presented in this paper. The evolution of the stress along the integration flow is described, with emphasize in the annealing steps. The impact of the film stress on the device is finally discussed especially... View full abstract»

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