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Advanced Thermal Processing of Semiconductors, 2006. RTP '06. 14th IEEE International Conference on

Date 10-13 Oct. 2006

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  • [Front cover]

    Publication Year: 2006 , Page(s): C1
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  • 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors RTP 2006

    Publication Year: 2006 , Page(s): nil1
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  • [Copyright notice]

    Publication Year: 2006 , Page(s): nil2
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  • Conference Chair

    Publication Year: 2006 , Page(s): nil3
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  • IEEE RTP 2006

    Publication Year: 2006 , Page(s): nil5 - nil9
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  • Call for papers

    Publication Year: 2006 , Page(s): nil10
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  • 15th IEEE International Conference on Advanced Thermal Processing of Semiconductors RTP 2007

    Publication Year: 2006 , Page(s): nil11
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  • RTP Conference Achievement Awards

    Publication Year: 2006 , Page(s): nil12 - nil13
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  • [Commentary]

    Publication Year: 2006 , Page(s): nil14
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  • Awards

    Publication Year: 2006 , Page(s): nil15
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  • [Breaker page]

    Publication Year: 2006 , Page(s): nil17
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  • Process-Integration Challenges with Up-To-Date Modulation of Scaling Laws

    Publication Year: 2006 , Page(s): 1 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (954 KB) |  | HTML iconHTML  

    CMOS scaling laws have already lost the physical bases, and the merest results induced by scaling laws are still utilized for requirements from technology users. In this paper, the actual situation of CMOS shrinkage and a forecast are discussed View full abstract»

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  • Growing Importance of Fundamental Understanding of the Source of Process Variations

    Publication Year: 2006 , Page(s): 5 - 9
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1104 KB) |  | HTML iconHTML  

    Statistical process control (SPC) has been widely practiced as a quality control method in the semiconductor industry. SPC is a system for monitoring, controlling, and improving a process through statistical analysis of monitored data. Control charts are widely used for process monitoring, but they are often misinterpreted. To improve process capability, the source of process variations must be properly identified from the control charts for proper feedback. Since the process tolerance is getting increasingly narrow, the importance of fundamental understanding of the source of process variations is an imperative. By eliminating or reducing process variation, a small improvement in process capability, can have a very significant business impact View full abstract»

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  • Laser Annealing Technology and Device Integration Challenges

    Publication Year: 2006 , Page(s): 11 - 14
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1836 KB) |  | HTML iconHTML  

    We have shown impacts of halo and deep source/drain (S/D) junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance and reduced hot carrier degradation compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. Gate pre-annealing by laser thermal process (LTP) was also investigated in conjunction with LSA S/D activation to effectively suppress poly-Si gate depletion while achieving highly activated ultra-shallow junctions in S/D, leading to improved transistor performance. Ioff was reduced more than one order of magnitude compared with conventional spike RTA devices View full abstract»

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  • Influence of the Atmosphere on Ultra - Thin Oxynitride Film for Precisely Controled Plasma Nitridation Process

    Publication Year: 2006 , Page(s): 15 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1219 KB) |  | HTML iconHTML  

    Influence of the atmosphere on ultra-thin oxynitride film was investigated for the precisely controlled plasma nitridation process. Some organic contaminant adsorb on the wafer before plasma nitridation process in clean room atmosphere. The adsorbed organic contaminant reduces the efficiency of plasma nitridation and increases the electrical thickness. The TDDB characteristic of ultra-thin oxynitride film was degraded due to the adsorbed organic contaminant. On the other hand, nitrogen concentration decreases due to exposure to an atmosphere after plasma nitridation process. The drop of nitrogen concentration causes Vth shift and Vth variation in MOSFET. The atmosphere and waiting time for post nitridation anneal affect on the drop of nitrogen concentration. It was demonstrated that the suppression of organic contamination before plasma nitridation and the control of the waiting time and atmosphere before post nitridation are the most important factors for the precise control of ultra-thin oxynitride film View full abstract»

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  • Double-Pulsed Laser Annealing Technologies and Related Applications

    Publication Year: 2006 , Page(s): 21 - 29
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4288 KB) |  | HTML iconHTML  

    New applications of the double-pulsed laser annealing (DPLA) technologies were opened up in the coming-generation high-performance devices: insulated gate bipolar transistors (IGBTs) and low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). The DPLA system was equipped with two solid-state lasers of a green wavelength as pulse laser sources. The line-beam irradiation was done in the same way as conventional excimer laser annealing (ELA) by making a sample stage scan at a constant speed while emitting the double-pulsed laser at 1kHz. The IGBTs demand deep PN junction in high electrical activation, while the LTPS-TFTs do high quality silicon thin films like a single crystal. The low-thermal budget annealing process enabled only the B- and P-implant layers within a depth of about 2mum to be activated without heating the whole wafer. The PN junction consisting of a B-implant layer and a P-implant layer reached more than 80% in activation ratios to adjust a delay time between double laser pulses. The advanced lateral crystal growth (ALCG) process enabled Si grains to be laterally and sequentially grown. The n-channel TFTs (L/W: 5mum/5mum) made of the ALCG-Si thin films reached a level of 600cm2/Vs in average mobility when the drain current flowed along the lateral-growth direction View full abstract»

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  • Ni-Silicide/Si and SiGe(C) Contact Technology for ULSI Applications

    Publication Year: 2006 , Page(s): 31 - 37
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2273 KB) |  | HTML iconHTML  

    We have investigated the crystalline and electrical properties of Ni silicide/Si and SiGeC contacts for ULSI applications. NiSi/Si contacts promises the contact resistivity as low as 10-8 Omegacm2 for both n+- and p+-Si. Degradation of the sheet resistance of NiSi layers critically depends on the annealing time particularly at temperatures ranging from 650degC to 750degC. The enlargement of the Si-exposed region concomitant with the NiSi agglomeration is a dominant factor responsible for the increase in sheet resistance and the activation energy of this process is estimated to be 2.8plusmn0.4 eV. Incorporation of Ge into Ni/Si systems is effective in raising the transformation temperature from NiSi to NiSi2. Incorporation of C into NiSi/Si system effectively suppresses the NiSi agglomeration. C introduction also causes the pile-up of B atoms at the NiSi/Si interface, which promises the reduction of the contact resistivity View full abstract»

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  • Ultra-Shallow Junction Formation by Plasma Doping and Flash Lamp Annealing

    Publication Year: 2006 , Page(s): 39 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3013 KB) |  | HTML iconHTML  

    Ultra-shallow P+/N junctions were formed by boron doping using plasma doping method combined with activation annealing using spike-RTA, flash lamp annealing or laser annealing. The junctions formed with flash lamp annealing or laser annealing were promising and superior to those formed by conventional low energy ion implantation method from the viewpoints of shallowness, abruptness and low sheet resistance. The pre-amorphization by He plasma treatment (He-PA process) played an important role for the successful formation or these junctions. Electrical properties were analyzed by not only sheet resistance but also Hall measurements and junction leakage measurement View full abstract»

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  • Millisecond Annealing with Flashlamps: Tool and Process Challenges

    Publication Year: 2006 , Page(s): 47 - 55
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1632 KB) |  | HTML iconHTML  

    Sub-second annealing is one of the key issues to meet the requirements of the 45 nm technology node according to the ITRS roadmap. Therefore, over the past decade there has been great interest in techniques such as laser and flash lamp annealing (FLA). In addition, advanced ultra-fast annealing shows promise for technologies that are not directly related to Si device processing. The main reason for using FLA in alternative applications is the reduced thermal budget because of the short annealing time, which enables one to achieve high temperatures (> 500degC) in the near-surface region while keeping the substrate bulk relatively cold. This is of particularly high importance for the development of novel polymer-based electronics and flexible solar cell technologies, where the substrates cannot withstand temperatures in excess of 150degC. An overview of theoretical simulations and related results from FLA experiments for a variety of layered systems is given. The influence of the flash duration and intensity on the heat distribution and the resulting physical properties is considered. Design and performance issues of the FLA tools depending on the specific uses and technical requirements are addressed. Furthermore, topics covered include high-throughput applications e.g. for roll-to-roll production of polymer substrates. Results of a prototype tool for multi-flash processing up to a frequency of 1 Hz using a pulse duration of 1 ms are also discussed View full abstract»

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  • The Progress in Ultra Thin Gate Dielecgtric for System LSI Application

    Publication Year: 2006 , Page(s): 57 - 63
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1791 KB) |  | HTML iconHTML  

    EOT reduction is a key challenge to keep the Moore's law, especially in low power LSIs. Nice candidates of gate dielectric as alternative to conventional SiO2 are N-rich SiON and high-K. However, in each case, we truly need tuning tools of Vth in the system LSI applications. F incorporation technique should be effective in Vth tuning with both N-rich SiON and high-K. Moreover, F incorporation is promising from reliability aspect View full abstract»

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  • Flash Lamp Annealing Latest Technology for 45nm device and Future devices

    Publication Year: 2006 , Page(s): 65 - 71
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2637 KB) |  | HTML iconHTML  

    FLA (flash lamp annealing) is used in 65nm generation devices manufacturing. For next 45nm and future generation devices, we have picked up 3 key subjects related to milli-second annealing: process controllability, S/D (source drain) activation, silicidation. No need to say, process controllability is very important for device manufacturing. And process requirement for S/D activation and silicidation controllability is becoming more and more severe. Under evaluation of these subjects, it became clear that FLA technology is still a hopeful candidate for 45nm device and future View full abstract»

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  • Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies

    Publication Year: 2006 , Page(s): 73 - 78
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2452 KB) |  | HTML iconHTML  

    With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced gate poly depletion for a process that is essentially free of additional diffusion. This paper will focus on process integration issues during implementation into 90 and 65 nm SOI logic technologies: Transistor parameter fluctuation and pattern effects, power density limitations and the impact on the reliability of ultra-thin gate oxides, compatibility with new materials such as SiGe, transistor scaling and performance enhancement View full abstract»

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  • Ultra-shallow Junction Formed by Plasma Doping and Laser Annealing

    Publication Year: 2006 , Page(s): 79 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1581 KB) |  | HTML iconHTML  

    We investigated ultra-shallow junction prepared by plasma doping (PLAD) and laser annealing (LA). Although PLAD is promising doping technology for the sub-45nm technology node due to the high dose rate at low energy, it has problems which is related with hydrogen or fluorine. The implanted hydrogen generally increases damage in the Si substrate. The fluorine also retards dopant activation and increases dopant deactivation during post-annealing step. Conventional one step annealing processes such as rapid thermal annealing (RTA) or excimer laser annealing (LA) are not effective method for high dopant activation. To minimize the effect of hydrogen or fluorine, we propose additional pre-annealing followed by conventional laser annealing. By employing low temperature pre-annealing, we can improve electrical characteristics such as low sheet resistance, high activation rates, shallow junction depth and reduced dopant deactivation. The improvement can be explained by reduced defect density and out-diffusion of fluorine or hydrogen which in turn enhances dopant activation during ELA View full abstract»

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  • Kinetics of Shallow Junction Activation: Physical Mechanisms

    Publication Year: 2006 , Page(s): 85 - 91
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4065 KB) |  | HTML iconHTML  

    Forming highly active shallow junctions is a key component enabling low external resistance and high transistor performance. Millisecond flash or scanning laser anneals can be used to contain diffusion and optimize activation, either directly by leveraging temperatures exceeding 1200C, or in combination with non-equilibrium processes such as amorphization plus solid phase epitaxy or liquid phase epitaxy. Diffusionless profiles can be obtained, but may not be optimal for devices. Consideration of deactivation physics is crucial to incorporation of any process leveraging superactive doping, since relaxation of doping is frequently very rapid, and may be crucially influenced by implant damage effects. Developing an understanding of dominant mechanisms is essential for the exploitation of millisecond or faster anneals to form superactive doping View full abstract»

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  • Mechanical Stress in Silicon Based Materials: Evolution Upon Annealing and Impact on Devices Performances

    Publication Year: 2006 , Page(s): 93 - 102
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1952 KB) |  | HTML iconHTML  

    An overview of the mechanical stress mechanisms observed within as deposited silicon oxide and nitride films deposited by the different techniques used for the CMOS transistors integration is presented in this paper. The evolution of the stress along the integration flow is described, with emphasize in the annealing steps. The impact of the film stress on the device is finally discussed especially in the case of integration of the shallow trench insulators and of the stress memorization technique View full abstract»

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