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2007 Asia and South Pacific Design Automation Conference

Date 23-26 Jan. 2007

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Displaying Results 1 - 25 of 191
  • [Front cover]

    Publication Year: 2007, Page(s): C1
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  • Copyright page

    Publication Year: 2007, Page(s): ii
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  • ASP-DAC 2007 General Chair's Message

    Publication Year: 2007, Page(s): iii
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  • Message from Technical Program Committee

    Publication Year: 2007, Page(s): iv
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  • University LSI Design Contest

    Publication Year: 2007, Page(s): v
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  • Designers' Forum

    Publication Year: 2007, Page(s): vi
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  • Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains

    Publication Year: 2007, Page(s): vii
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (602 KB) | HTML iconHTML

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  • Meeting with the Forthcoming IC Design -- The Era of Power, Variability and NRE Explosion and a Bit of the Future --

    Publication Year: 2007, Page(s): viii
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  • How Foundry can Help Improve your Bottom-Line? Accuracy Matters!

    Publication Year: 2007, Page(s): ix
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (487 KB) | HTML iconHTML

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  • ASP-DAC 2007 Best Papers

    Publication Year: 2007, Page(s):x - xi
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  • ASP-DAC 2007 Organizing Committee

    Publication Year: 2007, Page(s):xii - xv
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  • ASP-DAC Steering Committee

    Publication Year: 2007, Page(s):xvi - xix
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  • ASP-DAC 2007 Technical Program Committee

    Publication Year: 2007, Page(s):xx - xxii
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  • University LSI Design Contest Committee

    Publication Year: 2007, Page(s): xxiii
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  • Industry Liaison

    Publication Year: 2007, Page(s): xxiv
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  • List of reviewers

    Publication Year: 2007, Page(s):xxv - xxvi
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  • Contents

    Publication Year: 2007, Page(s):xxvii - xliv
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  • Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (285 KB) | HTML iconHTML

    Thickness range, i.e. the difference between the highest point and the lowest point of the chip surface, is a key indicator of chip yield. This paper presents a novel metal filling algorithm that seeks to minimize the thickness range of the chip surface during the copper damascene process. The proposed solution considers the physical mechanisms in the damascene process, namely ECP (which is the pr... View full abstract»

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  • Fast and Accurate OPC for Standard-Cell Layouts

    Publication Year: 2007, Page(s):7 - 12
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (729 KB) | HTML iconHTML

    Model based optical proximity correction (OPC) has become necessary at 90nm technology node and beyond. Cell-wise OPC is an attractive technique to reduce the mask data size as well as the prohibitive runtime of full-chip OPC. As feature dimensions have gotten smaller, the radius of influence for edge features has extended further into neighboring cells such that it is no longer sufficient to perf... View full abstract»

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  • Coupling-aware Dummy Metal Insertion for Lithography

    Publication Year: 2007, Page(s):13 - 18
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (191 KB) | HTML iconHTML

    As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip design. The widely used RET called off-axis illumination (OAI) introduces forbidden pitches which lead to very complex design rules. It has been observed that imposing uniformity on layout designs can substantially impr... View full abstract»

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  • Fast Buffer Insertion for Yield Optimization Under Process Variations

    Publication Year: 2007, Page(s):19 - 24
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (193 KB) | HTML iconHTML

    With the emerging process variations in fabrication, the traditional corner-based timing optimization techniques become prohibitive. Buffer insertion is a very useful technique for timing optimization. In this paper, we propose a buffer insertion algorithm with the consideration of process variations. We use the solutions from the deterministic buffering that sets all the random variables at their... View full abstract»

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  • A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield

    Publication Year: 2007, Page(s):24 - 31
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (161 KB) | HTML iconHTML

    Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clock distribution network augmentation for guaranteed skew yield. We present theoretical analysis results on an inserted link in a clock network, which scales down local skew and skew variation, but may not guarantee global skew and ... View full abstract»

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  • Control-Flow Aware Communication and Conflict Analysis of Parallel Processes

    Publication Year: 2007, Page(s):32 - 37
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    In this paper, we present an approach for control-flow aware communication and conflict analysis of systems of parallel communicating processes. This approach allows to determine the global timing behavior of such a system and to detect communication that might produce conflicts on shared communication resources. Furthermore, we show the incorporation of temporal environment models in order to ana... View full abstract»

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  • Software Performance Estimation in MPSoC Design

    Publication Year: 2007, Page(s):38 - 43
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-dominated embedded systems. This work proposes an integrated methodology for system design and performance analysis. An analytic approach based on neural networks is used for high-level software performance estimation. At ... View full abstract»

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  • Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS

    Publication Year: 2007, Page(s):44 - 49
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8000 KB) | HTML iconHTML

    It is attractive to use the OpenMP as a parallel programming model on a multiprocessor system-on-chip (MPSoC) because it is easy to write a parallel program in the OpenMP and there is no standard method for parallel programming on an MPSoC. In this paper, we propose an effective OpenMP implementation and translation for major OpenMP directives on an MPSoC with physically shared memories, hardware ... View full abstract»

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