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Semiconductor Thermal Measurement and Management Symposium, 2007. SEMI-THERM 2007. Twenty Third Annual IEEE

Date 18-22 March 2007

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  • [Front cover]

    Publication Year: 2007 , Page(s): C1
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  • Twenty Third Annual IEEE Semiconductor Thermal Measurement and Management Symposium

    Publication Year: 2007 , Page(s): i
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  • 2007 Proceedings, Twenty Third IEEE Semiconductor Thermal Measurement and Management Symposium

    Publication Year: 2007 , Page(s): ii
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  • Welcome

    Publication Year: 2007 , Page(s): iii - iv
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  • SEMI-THERM 23 Steering Committee

    Publication Year: 2007 , Page(s): v
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  • IEEE SEMI-THERM XXIII Short Courses

    Publication Year: 2007 , Page(s): vi
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  • A world of opportunities [advertisement]

    Publication Year: 2007 , Page(s): vii
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  • [Breaker page]

    Publication Year: 2007 , Page(s): viii
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  • Table of contents

    Publication Year: 2007 , Page(s): ix - xii
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  • Extracting Thermal Data from High Power MCM Packages

    Publication Year: 2007 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB) |  | HTML iconHTML  

    An experimental method was presented for characterizing the thermal performance of multi-chip modules (MCMs) using different size heat sinks. A flip chip package, having a total of five active components, was tested at various power level combinations using a flow bench test facility to supply air flow at a controlled velocity. A linear superposition model, developed for each sink, accurately predicted junction temperatures for a range of power combinations and flow velocities. For the specific package and range of power conditions tested, a more general empirically based model predicted junction temperatures as a function of heat sink size, flow velocity and power level combinations. View full abstract»

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  • Thermal Analysis of Memory Module Using Transient Testing Method

    Publication Year: 2007 , Page(s): 7 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    The electrical transient testing method has become popular as a useful thermal analysis tool because of its accuracy, high repeatability and rich information content compared to the use of traditional steady state thermal characterization techniques. This paper presents a thermal study of a 16-chip memory module using transient testing. The two variables in this study are the thermal boundary conditions of and the power distribution within the module. By applying the method of network identification by deconvolution (NID) to a transient temperature measurement, the structure function can be identified, which is the dynamic thermal resistance versus capacitance along a particular heat flow path for a given boundary condition and power distribution. Comparisons of the structure functions reveal differences in the heat flow paths for the cases of one chip and multiple chips dissipating heat. Transient testing have been successfully used on a three-dimensional memory module, and determined the contributions to the overall dynamic thermal resistance by each of the components including the heat spreader (HS), socket and even thermal interface material (TIM). This information about a 3D assembly is often difficult to obtain using steady state techniques. Thermal engineers can use such information to differentiate the relative merit of materials and heat transfer mechanisms in a cooling solution to optimize the overall thermal budget. View full abstract»

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  • Thermal Characteristics of Chip Stack and Package Stack Memory Devices in the Component and Module Level

    Publication Year: 2007 , Page(s): 12 - 17
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1645 KB) |  | HTML iconHTML  

    The demand of the high storage memory is providing a momentum for stacking technology in DRAM industry. As the stack technology is developed, more heat sources are embedded in the same package footprint and increase the device temperature. Therefore, the thermal management is one of most important issues in DRAM stack package. Since the chip stack and package stack technology are competing each other as a solution of DRAM stack, it is necessary to characterize thermal behavior of each package for better thermal management. Hence, in this paper, the authors studied the thermal performance characteristics of chip stack and package stack package in component and module level. The study is focused on the dual stack, which is most demanded stack height in DRAM market. The test package and module was assembled with the thermal test die and the DRAM junction temperature was measured to compare the thermal performance. The package stack package showed better thermal performance in component level because of its larger package size. On the other hand, the chip stack package showed better thermal performance in module level when the heat sink is used. View full abstract»

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  • High-Level Packaging Options for Outdoor Remote Units

    Publication Year: 2007 , Page(s): 18 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5790 KB) |  | HTML iconHTML  

    Thermal performance of three high-level packaging options for natural convection and radiation cooled outdoor remote units was investigated in this work. Analytical correlations were used to determine required number and size of the fins. Then, a computational fluid dynamic simulation tool was used to investigate detailed thermal performance of three packaging options with the limitation that they use same fin and base areas. It was shown that all three designs perform almost the same if solar load is applied on the unit. However, the cube design performs worse than the narrow-deep and wide-slim designs if no solar load is applied. View full abstract»

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  • Investigation of CPU Thermal Solution Designs for BTX Desktop System

    Publication Year: 2007 , Page(s): 24 - 29
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    Along with the ever increasing in CPU performance, the corresponding heat load climbs up significantly. For the personal computer with strict geometric constraints, the thermal management needs to be considered at the system level, instead of the component level. Especially in a system with BTX layout, the CPU and chipsets are aligned with the system fan. The geometry of CPU heat sink is inclined to affect the downstream airflow distribution. The variation in CPU heat sink designs not only changes the CPU operating temperature but also the temperatures of other key semiconductor components downstream, such as chipsets and memory sticks. Currently, based on existing thermal techniques including extrusion, cold forging, folded fin, stacked fin, heat pipe integrated heat sink and liquid cooling, the thermal management solutions could be properly tailored for personal computers with various hardware settings, if a guideline of BTX thermal solution and the ultimate limit of the current cooling methods are available. It is imperative to conduct a detailed study on the thermal performances of existing heat sink designs and their associated airflow distribution in BTX systems. In this investigation, a series of thermal solutions have been investigated through both experiment and CFD simulations for a typical BTX system and a rough roadmap has been figured out. The influence of CPU heat sink designs on system thermal performance is also discussed at the system level. View full abstract»

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  • Red Storm/XT Supercomputers Cooling System Design and Optimization

    Publication Year: 2007 , Page(s): 30 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1076 KB) |  | HTML iconHTML  

    Developing the optimal design for a supercomputer system is a complex and time consuming process. This paper describes a sequential optimization approach that can lead to the most effective computer cooling system design in the shortest time possible. Ways of seeking effective Pareto designs are shown. Cost driven quality engineering was applied to develop cooling solutions for chips, printed circuit boards, cabinets and the computer facility. CFD thermal analysis, small and large scale experiments allowed to maximize supercomputer cooling system performance. View full abstract»

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  • Thermal Considerations for LED Components in an Automotive Lamp

    Publication Year: 2007 , Page(s): 37 - 43
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (419 KB) |  | HTML iconHTML  

    LED's in automotive lamp applications have been utilized effectively for functions with low light output requirements and for styling purposes. In recent years, high to ultra high power LED's are becoming a light source option for virtually every automotive lighting system. For exterior automotive lighting, these light sources have distinct advantages, but also unique thermal issues compared to conventional incandescent light sources. This study describes two methods of determining the junction temperature of an LED or array of LED's, direct and indirect. Both are based on temperature measurements, but the indirect method also requires a thermal resistance specified by the manufacturer. The direct method utilizes the intrinsic behavior of the junction voltage drop at low current (<0.1mA). A computer model for a typical plate finned heat sink design for a high power LED automotive lamp was experimentally calibrated. Design of experiment analysis was performed using a 3 level 3 input factor full factorial test matrix. The factors were defined as an active heat sink surface area, convection coefficient correlated to an airflow, and environment temperature. A quadratic model is generated from the results of the factors and significant interactions to the response. View full abstract»

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  • Thermal Design and Analysis of a Military Aircraft Intercommunications System

    Publication Year: 2007 , Page(s): 44 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (924 KB) |  | HTML iconHTML  

    A new fiber optic/digital intercommunication system (ICS) for the Navy's E-2D advanced Hawkeye aircraft is under development to replace the aging analog system. The unique design of the system required a single chassis, called the Crew Station, to house a single board computer (SBC) and all associated electronics for each of the five operator's stations aboard the aircraft. This paper presents the methods employed to develop a satisfactory thermal design for the crew station without the fabrication of prototypes. A qualification unit was constructed, instrumented and tested, and the empirical results were compared with the simulations to validate the modeling. The agreement of the data was comfortably within acceptable testing and modeling errors and yielded confidence in the design of the ICS. View full abstract»

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  • Extraction of Power Dissipation Profile in an IC Chip from Temperature Map

    Publication Year: 2007 , Page(s): 51 - 56
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    This paper presents a new technique to calculate the power dissipation profile from the IC temperature map using an analogy with image processing and restoration. In this technique, finite element analysis (FEA) is used to find the heat point spread function of the IC chip. Then, the temperature map is used as input for an efficient image restoration algorithm which locates the sources of strong power dissipation non-uniformities. Therefore, for the first time the inverse heat transfer problem was optimally solved, and estimate the IC power map without involving extensive laboratory experiments. This computationally efficient and robust method, unlike some previous techniques in the literature, is applicable to virtually any experimental scenario. Simulation results on a typical commercial IC device confirm the effectiveness of our proposed method. View full abstract»

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  • Non-Contact Surface Temperature Measurements Coupled with Ultrafast Real-Time Computation

    Publication Year: 2007 , Page(s): 57 - 63
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (495 KB) |  | HTML iconHTML  

    This work presents the next step following a previous effort (Raad et al., 2006) toward creating a coupled experimental-computational technique devised for the full characterization of the thermal behavior of complex three-dimensional active submicron electronic devices. A newly developed CCD based thermoreflectance thermography (TRTG) system is used to measure the 2D surface temperature field of an activated device, non-invasively, with submicron spatial resolution. Then, the geometry and material thermal properties of the device are used to construct the corresponding numerical model. The measured temperature distribution field is then used as input for an ultrafast inverse computational technique to fully characterize the thermal behavior of three multilayered devices. For the purposes of this investigation, micro-heater devices were constructed, activated, and measured with the TRTG approach. The coupled system was used to extract key geometric properties of the micro-heaters. In this work, two parameters were chosen for optimization; namely, the thickness of bottom oxide and the length of the heat source of the micro-heaters. The results show that the extracted thickness compares well with the thickness measured by the use of a profiler. However, the extracted heat source length increases with the width of the micro-heater due to end effects. In the second part, the surface temperature results obtained with the coupled method are compared with those obtained from the fully independent electro-resistance thermometry approach. The results of the two methods compare very well, providing validation of the coupled experimental-computational system as well as confidence in its ability to thermally fully characterize complex 3D electronic devices. View full abstract»

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  • Development of Junction Temperature Decision (JTD) Map for Thermal Design of Nano-scale Devices Considering Leakage Power

    Publication Year: 2007 , Page(s): 63 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (394 KB) |  | HTML iconHTML  

    As semiconductor technology keeps scaling down, leakage power grows significantly due to the reduction in threshold voltage, channel length, and gate oxide thickness. As the junction temperature increases in nano-scale devices, leakage power increases drastically. This phenomenon motivates the processor and package designers to take into account thermal effects due to the large leakage power for highly reliable design of high-performance systems. In this paper, an analytical methodology for estimating the junction temperature and initial temperature range was provided to avoid diverging junction temperature status in nano-scale devices. For this purpose, junction temperature decision (JTD) map and initial temperature limit (ITL) map was newly introduced. View full abstract»

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  • On The Correlation Between Multiple Hot Blocks And Package Thermal Resistance

    Publication Year: 2007 , Page(s): 69 - 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    A flip-chip package with square die is considered in this study. Up to four square non-intersecting hot blocks are imposed on the die's otherwise uniform power distribution. Block locations on the die outline are randomly chosen with uniform probability. The power density of a given block is a random parameter, and is permitted to be as high as 10times the baseline uniform bulk power density. Additionally, the size of any block is also treated as a random parameter and is permitted to be as high as 10 % of the die area. A 6000-tuple Monte Carlo study of the packages is conducted, and the package thermal resistance (Rjc) noted in each case. A variety of models are fit to the Rjc using the block characteristics as key variables, and their quality is characterized using the statistical correlation coefficient as a model metric. The results suggest a 96 % correlation between Rjc and the largest product of local power ratio and square of effective local power density ratio among the blocks- providing a simple and useful method to immediately identify blocks with the most impact on Rjc in a die floorplan. View full abstract»

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  • A Junction Temperature Reduction Technique for a Microprocessor Considering Temperature Coupled Leakage Power

    Publication Year: 2007 , Page(s): 74 - 78
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    Leakage power is emerging as a key challenge in IC design. Since leakage power has super-linear dependency on operating temperature, it becomes imperative to consider the thermal effects while optimizing leakage power. In this paper, an inter-simulation technique which accounts for leakage power and temperature variations is present. Integrating leakage model and coupled thermal-leakage simulations, the converged temperature and power distributions are achieved. In order to flatten the on chip temperature gradient, the revised floorplan design of a microprocessor is proposed. The on-chip temperature distributions are verified with measurement results using an infrared thermography method. The analysis results show that the realistic on-chip temperature distribution is a key for a precise estimation of leakage power. In addition, an important design implication is that the leakage power optimization problem has to be considered as a synthetic task considering logic organization, circuit parameters and chip floor plan. View full abstract»

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  • A Statistical Approach For Characterizing The Thermal Impact Of TIM Voids

    Publication Year: 2007 , Page(s): 79 - 82
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB) |  | HTML iconHTML  

    Traditional methods of TIM (thermal interface material) void content specification are often based on a worst case analysis and can often lead to conservative and expensive lid attach design/process development, especially in high performance microprocessor package designs that are the norm today. In a meaningful departure from such methods, we present a practical approach to specify the maximum void content using the methods of statistical analysis. Our approach lends itself to a simple design paradigm where the business side of the package development drives the concept of an acceptable fallout level (AFL) and the technical specifications dictate the acceptable coolable power loss (ACPL). Together, these concepts are tied to a unique void content specification that is significantly less conservative than a worst-case approach, and readily meets the requirements of the design. We illustrate this novel approach for the simple case of TIM voids that have an area-wise uniform probability distribution, and compare the findings with a traditional worst-case void content specification. View full abstract»

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  • Comparison of Test Methods for High Performance Thermal Interface Materials

    Publication Year: 2007 , Page(s): 83 - 86
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    This paper relates the application of two of the methods for testing the thermal interface materials to the development and characterization of high performance materials. Particular strengths of different test methods provide a more complete understanding of TIM performance. In combination the tools provide effective development and improvement metrics. The limitations in resolution and repeatability are discussed. View full abstract»

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  • Hierarchical Nested Surface Channels for Reduced Particle Stacking and Low-Resistance Thermal Interfaces

    Publication Year: 2007 , Page(s): 87 - 94
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (641 KB) |  | HTML iconHTML  

    This paper reports on the improvement of thermal interfaces through the control of particle stacking during bondline formation. Particle stacking occurs in highly filled materials due to pressure gradients developing during squeeze flow over a rectangular surface, resulting in non-uniform interface properties and thick bondlines with a large thermal resistance. Nested surface channel designs are presented to create a uniform pressure drop as interface material flows across a rectangular surface. Reductions in thermal resistance of 2-3times compared with that of flat surfaces are demonstrated with similar reductions in bondline thickness and assembly pressure. We obtained thermal resistances as low as 2 Kmm2/W for thin bondlines (< 5 mum). Comparative power-cycling results also demonstrate improved reliability against paste pump-out with nested channel interfaces. View full abstract»

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