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1-5 June 1992

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Displaying Results 1 - 25 of 84
  • Proceedings. Euro ASIC '92 (Cat. No.92TH0442-4)

    Publication Year: 1992
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    Freely Available from IEEE
  • Context-based ASIC synthesis

    Publication Year: 1992, Page(s):226 - 231
    Cited by:  Papers (1)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    The authors describe methods for architecture-specific mapping of high-level functions ASICs. The techniques are demonstrated on field programmable gate arrays (FPGAs), but are not limited to those architectures. A network of generic modules provides an input specification from which a delay- and area-efficient logic-level design is synthesized. The methods described herein speed up design time si... View full abstract»

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  • Creating a nice-looking schematic from its netlist description

    Publication Year: 1992, Page(s):232 - 235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    The author describes a system that automatically generates digital schematics from a netlist description. A combination of algorithmic and heuristic methods are employed to synthetize a schematic as readable as possible. A very special care is given to aesthetic which is a major constraint of that type of software View full abstract»

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  • Specifying ASICs for complex mechatronic systems

    Publication Year: 1992, Page(s):238 - 243
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Today many industrial products are combinations of electronics, software and mechanics. The design project of such a product is difficult to manage, because the people needed to specify and design the product come from different backgrounds and they are familiar with different design methods and tools. The problems of the design of the interdisciplinary system and the methods and tools for specify... View full abstract»

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  • Quantifying design quality: a model and design experiments

    Publication Year: 1992, Page(s):172 - 177
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A design process model, focusing on design quality, is presented. Design quality is quantified as the probability that a design object satisfies its specification. Simple economic models demonstrate how design quality may impact cost, revenue, and lead time. Finally, design experiments done by several students are reported to exemplify the collection of design process parameters. These experiments... View full abstract»

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  • Ping-pong supervisor for synchronous links

    Publication Year: 1992, Page(s):364 - 367
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    Describes the framework and the design method used for an integrated circuit achieving ping-pong control for digital synchronous links. The principles of time division duplex communications and the different choices required for circuit design are also explained View full abstract»

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  • A high performance systolic chip for spelling correction

    Publication Year: 1992, Page(s):381 - 384
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    The author presents a fully integrated co-processor for accelerating the character string comparison involved in the spelling correction process. The chip is based on a truncated 2-D systolic array of 69 processors and is able to perform up to 1.3 Gops. Real time spelling correction is possible on very large vocabularies since dictionaries of 200000 items can be processed in only 0.1 second. The L... View full abstract»

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  • A transpose-register for a 2D-FFT of 64×64 pixel-blocks

    Publication Year: 1992, Page(s):294 - 297
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    The transpose-register is part of a system for data reduction of digital HDTV-signals. This approach is leading to a single-chip solution for the luminance signal. The algorithm implemented is based on two-dimensional transform coding of large subblocks. Using the two-column approach for two dimensional (2D) FFT, a transpose-register performing a read- and a write-access for 2048 bit in μsec is... View full abstract»

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  • Integrating ASIC and board design-for-testability

    Publication Year: 1992, Page(s):178 - 183
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The author presents the knowledge-based system WAGNER that integrates the application of design-for-test ability methods for boards, ASICs and boards containing ASICs. The system adapts the design to testing by using expert DFT knowledge and heuristics stored in a rule-based called TRISTAN and ISOLDE. TRISTAN (TRI-Stage Testability ANalysis) qualitatively analyzes the testability of a circuit unif... View full abstract»

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  • Automatic synthesis on table lookup-based PGAs

    Publication Year: 1992, Page(s):25 - 31
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Presents a synthesis method for table lookup-based PGAs. It uses three decomposition techniques followed by an area or speed oriented mapping. Among the three available alternatives, the lexicographical factorization is dedicated to cope with severe wiring problems. Results are given for a large set of benchmarks and compared with the best existing results available both in terms of the number of ... View full abstract»

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  • A universal hardware architecture for communication networks

    Publication Year: 1992, Page(s):368 - 371
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    A universal concept for the design of communication components and its architectural aspects is discussed. Some of the underlying research on communication systems is briefly reviewed. The first practical experiences in the ASIC-realization of the lower layers of the PROFIBUS field bus on the basis of this approach are presented View full abstract»

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  • An ASIC design for linear predictive coding of speech signals

    Publication Year: 1992, Page(s):288 - 291
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    In the real-time speech recognition, the predictor coefficients of speech signals are used as the recognizing features and should be computed faster than the sampling rate. Under such performance constraint, the objective is to design this circuit as cheap as possible. Autocorrelation method is adopted for computing the coefficients because of its stability of the results and regular computations.... View full abstract»

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  • Design of a H.261 video codec with 12 Xilinx LCAs

    Publication Year: 1992, Page(s):386 - 389
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    The authors describe the design of a video codec CCITT H.261 on 2 PC/AT boards based on special purpose DSPs, RAMs and Xilinx LCAs. The CCITT H.261 recommendations describes the video coding and decoding methods for the moving picture component of audiovisual services at the rates of p×64 kbit/s, where p is in the range 1 to 30. The codec has been developed jointly with Centre National d'Etu... View full abstract»

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  • Real time TV and HDTV motion estimation chipset

    Publication Year: 1992, Page(s):298 - 300
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    A flexible chipset for TV and HDTV real time motion estimation utilizing the block matching algorithm has been developed. Special emphasis was given to minimize costs and physical volume on board level. The board level design considerations and the resulting chipset, consisting of a 123000 gate CMOS gate array as a controller and a full custom processor array, are described View full abstract»

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  • A modular architecture for BIST of boundary scan boards

    Publication Year: 1992, Page(s):184 - 188
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strat... View full abstract»

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  • A wideband current-mode amplifier implemented from OTAs and its applications

    Publication Year: 1992, Page(s):135 - 138
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    A new concept for a current-mode amplifier (i.e. having input and output signals which are currents) is introduced. The circuit uses two operational transconductance amplifiers. Its gain-magnitude, which is temperature independent, is adjustable from one of the control-currents of the OTAs. Various applications of the circuit are also suggested, among which are a decoder and current-mode multiplex... View full abstract»

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  • ASIC integration of bus protocol for distributed industrial electromechanical system

    Publication Year: 1992, Page(s):396 - 399
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    In this paper an ASIC implementation of a novel bus protocol is presented. This bus is designed to transmit data inside the lowest level of hierarchy of an industrial automation system. Messages consist of control and measurement information between separate modules of a distributed actuator. The bus protocol circuit is designed to form a macrocell which can be used alone as a simple ASIC or as a ... View full abstract»

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  • An application specific microprocessor with two-level built-in control flow checking capabilities

    Publication Year: 1992, Page(s):310 - 313
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Concurrent checking consists of permanently verifying the behavior of a system by checking significant invariant properties to detect with a short latency either permanent or transient faults. Several types of methods have been proposed. The authors consider here control flow checking applied to microprocessor-based systems. Control flow invariant properties can be defined to verify the sequencing... View full abstract»

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  • Sequential synthesis for table look up PGAs

    Publication Year: 1992, Page(s):32 - 37
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The algorithms for synthesis onto programmable gate arrays (PGAs) have so far addressed only the combinational logic problem. The authors present two algorithms for mapping a sequential circuit onto a specific table look up architecture, namely the Xilinx 3090 architecture. The first algorithm maps combinational and sequential elements simultaneously. In the second, combinational elements are mapp... View full abstract»

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  • SETIPIC: electrothermal simulator for power integrated circuits in EDGE environment

    Publication Year: 1992, Page(s):214 - 219
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    The authors present SETIPIC, a software to simulate the electrothermal interactions in the first design steps of power integrated circuits. To give a well-consistent interface to the designer, SETIPIC has been integrated in the EDGE CAD system. The software aspect of this integration is explained. SETIPIC works around SPICE3 (electric simulation) and PICMOST (thermal simulation). This thermal simu... View full abstract»

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  • `SUPERCRYPT' ASIC technology facilitates a new device family for data encryption

    Publication Year: 1992, Page(s):356 - 359
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    SUPERCRYPT, a new hardware implementation of the DES Data Encryption Standard by means of a semi-custom cell-based ASIC technology is described. An encryption speed of 100 Mbits/s has been achieved on silicon applying 1 micron design rules, whereas a scaled 0.8 micron version will be operating faster than 140 Mbit/s. The semi-custom design methodology is briefly outlined and practical experiences ... View full abstract»

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  • COSIMA: a self-testable simulated annealing processor for universal cost functions

    Publication Year: 1992, Page(s):374 - 377
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Presents a chip forming the heart of a special purpose coprocessing unit, which accelerates simulated annealing algorithms to solve combinatorial optimization problems. The chip includes about 26000 transistors and runs at an expected clock frequency of 20 MHz. Compared with a software solution it leads to a speedup of about 500 View full abstract»

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  • FDD based technology mapping for FPGA

    Publication Year: 1992, Page(s):14 - 18
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    Functional decision diagrams (FDD) are shown to be a very efficient alternative to binary decision diagrams (BDD). FDDs are a representation in the functional domain, since they are based on the Reed-Muller Expansion and not on the sum-of-products form, which is suited to the operational domain. This paper introduces a technology mapping algorithm based on the FDDs and performing a direct mapping ... View full abstract»

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  • Design of an image processing integrated circuit for real time edge detection

    Publication Year: 1992, Page(s):280 - 283
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Presents the design of a real time image processing micro-system to detect defects on manufacturing products. The analysis method is based on an edge detection algorithm (differential operators) to select the information related to the structure of the objects present in the image. The edge calculation function has been integrated in a standard cell circuit using a CMOS 1.5 μm process. The ASIC... View full abstract»

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  • Insensitive current-mode biquad implementation based on translinear current conveyors

    Publication Year: 1992, Page(s):126 - 130
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    An insensitive current-mode filter, implemented from two second generation current conveyors is introduced. The circuit uses four passive components and exhibits simultaneously two 2nd order transfer functions: highpass and bandpass. A versatile ASIC implementation is proposed for the circuit. It includes the filter core and three supplementary followers in order that the lowpass, bandreject and a... View full abstract»

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