1-5 June 1992

Filter Results

Displaying Results 1 - 25 of 84
  • Proceedings. Euro ASIC '92 (Cat. No.92TH0442-4)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (80 KB)
    Freely Available from IEEE
  • Mobile communication ASICs

    Publication Year: 1992, Page(s):119 - 124
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    Mobile cellular radio systems built for the new GSM digital specification, or for the lower cost analogue networks, rely heavily on advanced semiconductor technologies for realisation of the complex VLSI digital and low-power analogue integrated circuits used within them. Mixed signal ASICs using 3-micron and 1.2-micron analogue CMOS processes have been designed for mobile telephone control functi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ASIC and board design of a high performance parallel architecture

    Publication Year: 1992, Page(s):244 - 249
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The integrated design of ASIC and board is a key approach for high performance parallel architectures. This paper describes the solutions adopted in the design of a parallel architecture for research purposes. The heart of the architecture is an ASIC processor (100 K transistors, 180 pin PGA, 30 MHz) with RISC features and instruction-level parallelism capabilities. The whole system design has bee... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A speller board for personal computer

    Publication Year: 1992, Page(s):250 - 255
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Cost effective ASICs should be designed for easy integration at system level, and with the possibility of being part of a range of products, targeted at different markets. In this contribution, a personal computer (PC) extension board that implements, in hardware, a spell environment for any natural language is presented. The PC board design is based upon the use of an ASIC, a searching processor ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reduction of the number of symbolic outputs of finite state machines

    Publication Year: 1992, Page(s):40 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    An algorithm is presented which works on the symbolic level, prior to the code assignment phase. Under certain conditions it is possible to implement several symbolic outputs by one single symbolic output. By that, the number of symbolic outputs, and therefore, the number of binary output functions which have to be implemented is reduced. This is in particularly useful if the number of output func... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A single ASIC device completely implements control in an 80486-based personal computer system

    Publication Year: 1992, Page(s):258 - 261
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    The goal of this ASIC design was to produce a single-chip PC/AT-compatible controller optimized to perform in 80486SX- and 80486DX-based computer systems running at speeds of up to 33 MHz. Since VLSI has had five years experience with preceding designs for controllers for earlier microprocessors, a library of very large, high-performance `standard cells' performing as functional system blocks (FSB... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • `SUPERCRYPT' ASIC technology facilitates a new device family for data encryption

    Publication Year: 1992, Page(s):356 - 359
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    SUPERCRYPT, a new hardware implementation of the DES Data Encryption Standard by means of a semi-custom cell-based ASIC technology is described. An encryption speed of 100 Mbits/s has been achieved on silicon applying 1 micron design rules, whereas a scaled 0.8 micron version will be operating faster than 140 Mbit/s. The semi-custom design methodology is briefly outlined and practical experiences ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrating ASIC and board design-for-testability

    Publication Year: 1992, Page(s):178 - 183
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The author presents the knowledge-based system WAGNER that integrates the application of design-for-test ability methods for boards, ASICs and boards containing ASICs. The system adapts the design to testing by using expert DFT knowledge and heuristics stored in a rule-based called TRISTAN and ISOLDE. TRISTAN (TRI-Stage Testability ANalysis) qualitatively analyzes the testability of a circuit unif... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ASIC library qualification: criteria and procedure

    Publication Year: 1992, Page(s):66 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    Library accuracy is a vital concern for library builders and library users. As complexity of ASICs increases, more accurate logic simulation is required to get a functional silicon chip. Usually ASIC vendors provide many libraries on third party simulators, as well as Golden Simulator. Assuming a master library for the Golden Simulator is well correlated with silicon performance, libraries on othe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Logic decomposition for programmable gate arrays

    Publication Year: 1992, Page(s):19 - 24
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    In this paper an effective decomposition algorithm for mapping of logic functions onto FPGAs is proposed. The algorithm exploits the symbolic decomposition concept to find FPGA based implementation with a minimal number of CLBs. Experimental results of the presented method are provided and compared to other similar tools View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Width minimization of field encoded outputs

    Publication Year: 1992, Page(s):46 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    A new technique for minimizing the width of programmable logic devices (PLDs) is introduced. A weighting technique is introduced, which assigns a weight to each micro-order equal to the size of the largest reserved class containing it. The micro-orders with the largest weights are tripped from each class to form a stripped set. The stripped microorders are tested for compatibility, and a new set o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ITEM: an if-then-else minimizer for logic synthesis

    Publication Year: 1992, Page(s):2 - 7
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Introduces ITEM, the combinational logic minimization program developed at the University of California, Santa Cruz. ITEM is useful for generating highly testable circuits, because canonical if-then-else DAGs are robustly path-delay-fault testable, and often produce small, fast circuits. Several of the transformations preserve testability, including the Xmap and Amap technology mappers for field-p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a H.261 video codec with 12 Xilinx LCAs

    Publication Year: 1992, Page(s):386 - 389
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    The authors describe the design of a video codec CCITT H.261 on 2 PC/AT boards based on special purpose DSPs, RAMs and Xilinx LCAs. The CCITT H.261 recommendations describes the video coding and decoding methods for the moving picture component of audiovisual services at the rates of p×64 kbit/s, where p is in the range 1 to 30. The codec has been developed jointly with Centre National d'Etu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A design exercise of a micropower analog digital ASIC chip

    Publication Year: 1992, Page(s):340 - 342
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    A micropower heart rate detector chip integrated with CMOS technology has been developed. The chip uses analog SC and digital techniques. A mathematics program was used for system level optimization and analysis, whereas in circuit level verification a mixed mode and transistor level simulators were used. The layout was done in full custom style in order to minimize silicon area. This paper gives ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ASIC design of a high performance RISC

    Publication Year: 1992, Page(s):262 - 265
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Describes the VLSI implementation of a 32-bit central processing unit (CPU) chip based on reduced instruction set computer (RISC) principles and its testing methodology based on functional fault model. The processor which adopts 4-stage instruction execution pipeline has achieved the goal of single cycle execution using a 2-phase 16.7 MHz clock. The cell-based approach was chosen as VLSI implement... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • MDRX: an ATM building block for subscribers' premises networks

    Publication Year: 1992, Page(s):360 - 363
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    Describes the design of the MDRX (multiplexing demultiplexing replicas and switching) device. The chip is a building block for asynchronous transfer mode (ATM) switching in the subscribers' premises networks (SPN) of the broadband integrated services digital network (B-ISDN). The circuit was fabricated in a 160 K gates 0.8 micron CMOS sea-of-gates gate array View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A modular architecture for BIST of boundary scan boards

    Publication Year: 1992, Page(s):184 - 188
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ASIC integration of bus protocol for distributed industrial electromechanical system

    Publication Year: 1992, Page(s):396 - 399
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    In this paper an ASIC implementation of a novel bus protocol is presented. This bus is designed to transmit data inside the lowest level of hierarchy of an industrial automation system. Messages consist of control and measurement information between separate modules of a distributed actuator. The bus protocol circuit is designed to form a macrocell which can be used alone as a simple ASIC or as a ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An open environment for standard cell and gate array library development

    Publication Year: 1992, Page(s):72 - 77
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Standard cell and gate array libraries are assembled in this powerful environment, which automates SPICE characterization and datasheet generation while providing simulation models whose accuracy may be verified, for many simulators. Any of several third-party EDA tools may be utilized at each stage in the development cycle View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of an image processing integrated circuit for real time edge detection

    Publication Year: 1992, Page(s):280 - 283
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Presents the design of a real time image processing micro-system to detect defects on manufacturing products. The analysis method is based on an edge detection algorithm (differential operators) to select the information related to the structure of the objects present in the image. The edge calculation function has been integrated in a standard cell circuit using a CMOS 1.5 μm process. The ASIC... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A mixed analog/digital coprocessor for image scanning

    Publication Year: 1992, Page(s):108 - 112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    A new ASIC coprocessor has been designed for image scanning applications. The chip contains a high performance analog part which is based on an original pipelined RSD A/D converter. This paper describes the functions and the architecture of the circuit and will focus on the analog unit description and its implementation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic synthesis on table lookup-based PGAs

    Publication Year: 1992, Page(s):25 - 31
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Presents a synthesis method for table lookup-based PGAs. It uses three decomposition techniques followed by an area or speed oriented mapping. Among the three available alternatives, the lexicographical factorization is dedicated to cope with severe wiring problems. Results are given for a large set of benchmarks and compared with the best existing results available both in terms of the number of ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Floorplanning with power routing

    Publication Year: 1992, Page(s):165 - 168
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Considering power routing during the generation of an initial floorplan minimizes the number of design iterations. However, past power routers only route after hierarchical blocks are synthesized. Floorplanning with power routing involves generating and maintaining symbolic routing before block sizes and pin locations are known. Results considering floorplan level power routing show upto an 11% im... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interactive register transfer level synthesis using library blocks

    Publication Year: 1992, Page(s):53 - 58
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The synthesis system presented here starts from an initial register transfer level description. This description uses operators and registers defined in a block library. The system synthesizes automatically a circuit consisting of a datapath and a controller with several data path and controller style possibilities. Optimization of the design reconsidering the separation between the data path and ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis on multiplexer-based programmable devices using (ordered) binary decision diagrams

    Publication Year: 1992, Page(s):8 - 13
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Presents synthesis techniques on the Actel multiplexer-based programmable gate arrays. The internal structure of these devices is exploited through binary decision diagrams based algorithms. According to the speed/area trade-off, either classical or reduced ordered Binary Decision Diagrams are used. Emphasis is put on the determination of a good ordering for the ROBDD construction. Results on a la... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.