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Real Time and Embedded Technology and Applications Symposium, 2007. RTAS '07. 13th IEEE

Date 3-6 April 2007

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  • 13th IEEE Real Time and Embedded Technology and Applications Symposium - Cover

    Publication Year: 2007 , Page(s): c1
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  • 13th IEEE Real Time and Embedded Technology and Applications Symposium-Title

    Publication Year: 2007 , Page(s): i - iii
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  • 13th IEEE Real Time and Embedded Technology and Applications Symposium-Copyright

    Publication Year: 2007 , Page(s): iv
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  • 13th IEEE Real Time and Embedded Technology and Applications Symposium - TOC

    Publication Year: 2007 , Page(s): v - vii
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  • Message from the Program Chairs

    Publication Year: 2007 , Page(s): viii
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  • Chairs

    Publication Year: 2007 , Page(s): ix
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  • Technical Program Committees

    Publication Year: 2007 , Page(s): x - xi
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  • Reviewers

    Publication Year: 2007 , Page(s): xii
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  • CPU Model-Based Hardware/Software Co-design, Co-simulation and Analysis Technology for Real-Time Embedded Control Systems

    Publication Year: 2007 , Page(s): 3 - 11
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (853 KB) |  | HTML iconHTML  

    This paper proposes a new development method for highly reliable real-time embedded control systems using a CPU model-based hardware/software co-simulation. We take an approach that allows the full simulation of the virtual mechanical control system including the mechatronics plant, microcontroller hardware and object code level software. This full virtual system simulation reveals the control system behavior, especially in microcontroller hardware and software. It enables microarchitecture design space exploration, control design validation, robustness evaluation of the system, software optimization before components design, and prevents potential problems. A novel aspect of this work is that the proposed virtual control system comprises all the components in a typical control system, therefore it enables the analysis of the effects from the different domains, for example the mechanical analysis of behavior due to a control software bug. To help the design, evaluation and analysis, we developed an integrated behavior analyzer into the development environment. This can display the processor behavior graphically during the simulation without affecting the simulation results, such as task level CPU load, interrupt statistics and software variable transition chart. This analyzer provides useful information on the behavior. No software modification is necessary for this virtual system analysis, and this analysis does not change the control timing and does not require any processing power on the target microcontroller. Therefore this method is suitable for real-time embedded control system design, in particular automotive control system design which requires high level reliability, robustness, quality and safety. In this paper, a Renesas SH-2A microcontroller model was developed on a CoMETtrade platform from VaST Systems Technology. An ETC (electronic throttle control) system is chosen as the plant to prove this concept. The ETB (electronic throttle body) model on Saberr- eg simulator from Synopsysreg was co-simulated with the SH-2A model. The SH-2A chip was under development during this project, nevertheless we could complete the OSEK OS development, control software design and verification using the virtual system. We confirmed that such software could run on an actual ETC hardware system without modification after a working sample chip was released at a later stage in the course of this work. This demonstrates that our models and simulation environment are sufficiently credible and trustful View full abstract»

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  • Prioritized SMT Architecture with IPC Control Method for Real-Time Processing

    Publication Year: 2007 , Page(s): 12 - 21
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1027 KB) |  | HTML iconHTML  

    This paper describes a novel processor architecture, the prioritized SMT architecture with the IPC control method, to guarantee the execution time of real-time threads. Based on priority set by a real-time scheduler, all hardware resources including cache systems, fetch, issue, and execution units, are controlled, so that our processor can execute multiple threads in real-time. All runnable threads are simultaneously executed as much as possible in priority order, so that the execution order becomes congruent with the priority order set by a real-time scheduler. If a resource conflict occurs, the lower priority threads are kept waiting until the higher priority thread finishes using the resource. In brief, context switching required for real-time scheduling and execution is converted to the prioritized SMT execution. Here, some triggers including cache misses and branch prediction misses fluctuate the execution speed of a thread. Additionally, in case of an SMT processor, the execution time of each thread may vary according to a combination of simultaneous executing threads. To guarantee the execution time of real-time threads accurately, the IPC control method that monitors and controls each thread IPC in a feedback loop is designed and implemented. Our IPC control method can keep the IPC deviation of the thread within plusmn1% bounds, if the target IPC is less than 80% of the single thread execution IPC. Our processor is implemented as a processing core of a system LSI, which process was TSMC 0.13 mum 8 layered Cu wiring, used for distributed real-time systems including humanoid robots, bilateral robots, embedded control systems, and ubiquitous computing systems View full abstract»

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  • Optimizing the FPGA Implementation of HRT Systems

    Publication Year: 2007 , Page(s): 22 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (527 KB) |  | HTML iconHTML  

    The availability of programmable hardware devices with high density of logic elements and the possibility of implementing CPUs (called softcores) using a fraction of the FPGA area offers additional flexibility for the implementation of embedded applications with real-time constraints. When implementing functions on such devices, designers can choose between hardware and software. Also, the designer can select the number of CPUs that must be created to best support the execution of the real-time software. In this paper, we define a design optimization procedure for hard real-time systems, in which each functional block can be implemented in HW, using the logic elements available on the FPGA, or in SW, by means of a real-time task executed by a softcore. The optimizer allocates the functions and the softcores such that the HW implemented part is mapped within the area constraints and the software part is allocated so that schedulability can be guaranteed. When feasible solutions exist, the minimum utilization solution is computed View full abstract»

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  • Optimal Static Task Scheduling on Reconfigurable Hardware Devices Using Model-Checking

    Publication Year: 2007 , Page(s): 32 - 44
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (319 KB) |  | HTML iconHTML  

    Real-time scheduling for FPGAs presents unique challenges to traditional real-time scheduling theory, since it is similar to, but more general than multi-processor scheduling. In his paper, we address two problems of static task scheduling on a partially runtime reconfigurable FPGA: finding an optimal static schedule for a task graph with the optimization objective of minimizing the total schedule length, and finding a feasible static schedule for a set of periodic tasks within a hyper-period with the objective of meeting all deadlines. We model the multi-tasking system with timed automata and use reachability analysis of the UPPAAL model-checker to explore the design space and find an optimal or feasible schedule View full abstract»

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  • Full Duplex Switched Ethernet for Next Generation "1553B"-Based Applications

    Publication Year: 2007 , Page(s): 45 - 56
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (605 KB) |  | HTML iconHTML  

    Over the last thirty years, the MIL-STD 1553B data bus has been used in many embedded systems, like aircrafts, ships, missiles and satellites. However, the increasing number and complexity of interconnected subsystems lead to emerging needs for more communication bandwidth. Therefore, a new interconnection system is needed to overcome the limitations of the MIL-STD 1553B data bus. Among several high speed networks, full duplex switched Ethernet is put forward here as an attractive candidate to replace the MIL-STD 1553B data bus. However, the key argument against switched Ethernet lies in its non-deterministic behavior that makes it inadequate to deliver hard time-constrained communications. Hence, our primary objective in this paper is to achieve an accepted QoS level offered by switched Ethernet, to support diverse "1553B"-based applications requirements. We evaluate the performance of traffic shaping techniques on full duplex switched Ethernet with an adequate choice of service strategy in the switch, to guarantee the real-time constraints required by these specific 1553B-based applications. An analytic study is conducted, using the network calculus formalism, to evaluate the deterministic guarantees offered by our approach. Theoretical analysis are then investigated in the case of a realistic "1553B"-based application extracted from a real military aircraft network. The results herein show the ability of profiled full duplex switched Ethernet to satisfy 1553B-like real-time constraints View full abstract»

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  • Modeling Device Driver Effects in Real-Time Schedulability Analysis: Study of a Network Driver

    Publication Year: 2007 , Page(s): 57 - 68
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (389 KB) |  | HTML iconHTML  

    Device drivers are integral components of operating systems. The computational workloads imposed by device drivers tend to be aperiodic and unpredictable because they are triggered in response to events that occur in the device, and may arbitrarily block or preempt other time-critical tasks. This characteristic poses significant challenges in real-time systems, where schedulability analysis is essential to guarantee system-wide timing constraints. At the same time, device driver workloads cannot be ignored. Demand-based schedulability analysis is a technique that has been successful in validating the timing constraints in both single and multiprocessor systems. In this paper we present two approaches to demand-based schedulability analysis of systems that include device drivers. First, we derive load-bound functions using empirical measurement techniques. Second, we modify the scheduling of network device driver tasks in Linux to implement an algorithm for which a load-bound function can be derived analytically. We demonstrate the practicality of our approach through detailed experiments with a network device under Linux. Our results show that, even though the network device driver does not conform to conventional periodic or sporadic task models, it can be successfully modeled using hyperbolic load-bound functions that are fitted to empirical performance measurements View full abstract»

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  • Soft Real-Time Chains for Multi-Hop Wireless Ad-Hoc Networks

    Publication Year: 2007 , Page(s): 69 - 80
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (222 KB) |  | HTML iconHTML  

    Prioritized MAC protocols are needed to support soft real-time communication in wireless networks. In this paper, we introduce real-time chain, a new prioritized MAC protocol to support soft real-time data flows in multi-hop wireless ad-hoc networks. By avoiding packet collisions and limiting the effect of priority inversions, real-time chain is able to provide soft real-time and bandwidth guarantees. Furthermore, the use of multiple channels enables high spatial reuse and transmission rates. Finally, our approach can be integrated with a slightly modified version of the IEEE 802.15.4 standard. The protocol has been fully implemented on Crossbow MICAz hardware and its performance has been validated with a large set of both indoor and outdoor experiments View full abstract»

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  • Dynamic Task Scheduling and Processing Element Allocation for Multi-Function SoCs

    Publication Year: 2007 , Page(s): 81 - 90
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    This work is motivated by the rapid increasing of the design complexity of many embedded systems. It aims at the proposing of solutions to resolve the hardware contention issues of non-preemptive processing elements shared among tasks and the cost optimization. A software solution based on the starting time management is proposed to interleave task executions on processing elements. Algorithms are proposed to determine the required processing elements of selected types, when there is no knowledge on the releasing time of any task: When task release orders are known a priori, an optimal algorithm is presented if processing elements have the same cost; otherwise, a pseudo-polynomial-time algorithm based on dynamic programming is presented for optimal solutions. The performance of the algorithms is also evaluated for general cases View full abstract»

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  • Resource-Locking Durations in EDF-Scheduled Systems

    Publication Year: 2007 , Page(s): 91 - 100
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    The duration of time for which each application locks each shared resource is critically important in composing multiple independently-developed applications upon a shared "open" platform. The concept of resource hold time (RHT) - the largest length of time that may elapse between the instant that an application system locks a resource and the instant that it subsequently releases the resource - is formally defined and studied in this paper. An algorithm is presented for computing resource hold times for every resource in an application that is scheduled using earliest deadline first scheduling, with resource access arbitrated using the stack resource policy. An algorithm is presented for decreasing these RHT's without changing the semantics of the application or compromising application feasibility View full abstract»

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  • Soft Real-Time Scheduling on Performance Asymmetric Multicore Platforms

    Publication Year: 2007 , Page(s): 101 - 112
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB) |  | HTML iconHTML  

    This paper discusses an approach for supporting soft real-time periodic tasks in Linux on performance asymmetric multicore platforms (AMPs). Such architectures consist of a large number of processing units on one or several chips, where each processing unit is capable of executing the same instruction set at a different performance level. We discuss deficiencies of Linux in supporting periodic real-time tasks, particularly when cores are asymmetric, and how such deficiencies were overcome. We also investigate how to provide good performance for non-real-time tasks in the presence of a real-time workload. We show that this can be done by using deferrable servers to explicitly reserve a share of each core for non-real-time tasks. This allows non-real-time tasks to have priority over real-time tasks when doing so will not cause timing requirements to be violated, thus improving non-real-time response times. Experiments show that even small deferrable servers can have a dramatic impact on non-real-time task performance View full abstract»

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  • Middleware Support for Aperiodic Tasks in Distributed Real-Time Systems

    Publication Year: 2007 , Page(s): 113 - 122
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    Many mission-critical distributed real-time applications must handle aperiodic tasks with end-to-end deadlines. However, existing middleware (e.g., RT-CORBA) lacks schedulability analysis and run-time enforcement mechanisms needed to give online real-time guarantees for aperiodic tasks. The primary contribution of this work is the design, implementation, and performance evaluation of the first realization of deferrable server and admission control mechanisms for aperiodic tasks in middleware. Empirical results on a KURT-Linux testbed demonstrate the efficiency and effectiveness of our deferrable server and admission control mechanisms in TAO's federated event service View full abstract»

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  • Towards a Synchronous Scheduling Service on Top of a Unicast Distributed Real-Time Java

    Publication Year: 2007 , Page(s): 123 - 132
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB) |  | HTML iconHTML  

    This paper describes an approach towards the definition and implementation of a synchronization service on top of a remote object model offered by an unicast real-time remote object paradigm. Also an architecture model based on the RTSJ (real-time specification for Java) and the distribution middleware RMI (remote method invocation) specifications is proposed in order to give support to the model, defining a convergence layer that manages the underlying resources involved in a master-slave communication through a new API. Finally, preliminary results from an implementation prototype show the feasibility of the model and provide an initial estimation of jitters and the performance of the synchronization service View full abstract»

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  • Hijack: Taking Control of COTS Systems for Real-Time User-Level Services

    Publication Year: 2007 , Page(s): 133 - 146
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    This paper focuses on a technique to empower commercial-off-the-shelf (COTS) systems with an execution environment, and corresponding services, to support real-time and embedded applications. By leveraging COTS systems, we are able to reduce the potentially expensive maintenance and development costs of proprietary solutions. We describe a system called "Hijack" that enables user-level services to take control of features such as CPU scheduling, interrupt handling and synchronization. In contrast to other approaches that support real-time tasks within the kernel of commodity systems such as Linux, Hijack provides the basis for predictable thread execution at user-level. No changes to the kernel source code are required to support this approach. Instead, Hijack works by using a combination of kernel module support and an interposed execution environment between traditional process address spaces and the kernel. This technique enables system calls and hardware interrupts to be intercepted with bounded latencies via the kernel module, that passes control to a user-level real-time executive. From within the executive, system-wide services and policies can be deployed to over-ride certain features of the underlying kernel, while still leveraging base kernel services where appropriate. Using this technique, we show how a vanilla Linux system can be hijacked to support predictable service execution using a series of user-defined policies. In particular, we show how to deliver and process asynchronous events with bounded latency, using interposition agents within a Hijack execution environment. Results show that for realtime streaming applications, Hijack is able to receive and process packets with significantly lower loss rates and jitter compared to using alternative application-level processes for the same task View full abstract»

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  • Preemption Threshold Scheduling: Stack Optimality, Enhancements and Analysis

    Publication Year: 2007 , Page(s): 147 - 157
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    Using preemption threshold scheduling (PTS) in a multi-threaded real-time embedded system reduces system preemptions and hence reduces run-time overhead while still ensuring real-time constraints are met. However, PTS offers other valuable benefits. In this paper we investigate the use of PTS for hard real-lime system with limited RAM. Our primary contribution is to prove the optimality of PTS among all preemption-limiting methods for minimizing a system's total stack memory requirements. We then discuss characteristics of PTS and show how to reduce average worst-case response times. We also introduce a unified framework for using PTS with existing fixed-priority (e.g. rate-or deadline-monotonic), or dynamic-priority scheduling algorithms ( e.g. earliest-deadline first). We evaluate the performance of PTS and our improvements using synthetic workloads and a real-time workload. We show PTS is extremely effective at reducing slack memory requirements. Our enhancements to PTS Improve worst-case, response-times as well View full abstract»

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  • Minimising Task Migration and Priority Changes in Mode Transitions

    Publication Year: 2007 , Page(s): 158 - 167
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB) |  | HTML iconHTML  

    Handling mode changes is one of the most complex and important problems for real-time systems designers. The challenge is to move a system from running one set of software to another while still achieving the quality of service guarantees necessary. There has been previous work which concentrated on how to perform scheduling and timing analysis of mode changes. However, a common theme of all this research is that if the system's schedule and allocation is chosen to minimise the set of differences between modes then the mode transition problem can be performed more easily and quickly. This paper investigates how this can be achieved View full abstract»

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  • Optimal Unified Data Allocation and Task Scheduling for Real-Time Multi-Tasking Systems

    Publication Year: 2007 , Page(s): 168 - 182
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (299 KB) |  | HTML iconHTML  

    Many real-time (RT) embedded systems can benefit from a memory hierarchy to bridge the processor/memory speed gap. These RT embedded systems usually utilize a cacheless architecture to avoid the time variability which complicates the timing analysis essential for RT systems. In the absence of a cache the burden of allocating the data objects to the memory hierarchy is on the programmer/compiler. There has been much research into allocating data objects into the memory hierarchy for efficient execution. However, existing methods have limited scope and ignore some aspects of RT multitasking embedded systems. In this paper we propose a synergistic, optimal approach to allocating data objects and scheduling real-time tasks for embedded systems. We allocate data using integer linear programming (ILP) to minimize each task's worst-case execution time (WCET), then perform preemption threshold scheduling (PTS) on the tasks to reduce stack memory requirements while still meeting hard RT deadlines. The memory reduction of PTS allows these steps to be repeated. The data objects now require less memory, so more can fit into faster memory, further reducing WCET. The increased slack time can be used by PTS to reduce preemptions further, until a fixed point is reached. We evaluate the technique with several levels of data object granularity using both synthetic workloads and a real-time benchmark and find it to be highly effective View full abstract»

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  • Stochastic Metrics for Debugging the Timing Behaviour of Real-Time Systems

    Publication Year: 2007 , Page(s): 183 - 192
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (309 KB) |  | HTML iconHTML  

    Stochastic analysis techniques for real-time systems model the execution time of tasks as random variables. These techniques constitute a very powerful tool to study the behaviour of real-time systems. However, as they can not avoid all the timing bugs in the implementation, they must be combined with measurement techniques in order to gain more confidence in the implemented system. In this paper, a set of tools to measure, analyze and visualize traces of real-time systems is presented. These tools are driven by stochastic models. In order to find bugs in the timing behaviour of the system, two metrics, called "pessimism" and "optimism", are proposed. They are based on two random variables, the optimistic and the pessimistic execution time, which are also introduced in this paper. These metrics are used in the debugging tools to compare the model and the measured system in order to find errors. The metrics are examined in three case studies View full abstract»

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