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Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Date 4-7 Dec. 2006

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Displaying Results 1 - 25 of 502
  • A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25μ BiCMOS Technology

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3316 KB) |  | HTML iconHTML  

    A fully differential low power 10-bit 200MSPS sample and hold has been designed for the front-end of a pipelined analog-to-digital converter using 0.25μm BiCMOS technology. Switched capacitor differential topology has been used with special care taken in linearization of switches. The key issues of the design are optimization of speed, accuracy and power minimization. An op-amp (OTA) having very fast settling time of 1.67ns is designed to meet the speed requirement of the sample and hold. The sample and hold consumes 11mW power while occupying an area of 0.07 mm2 including clock driver circuitry. Analog and digital power-supplies used are 3V and 2.5V respectively View full abstract»

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  • A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4151 KB) |  | HTML iconHTML  

    A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta-stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Simulation based sensitivity analysis is performed to demonstrate the robustness of the new comparator with respect to stray capacitances, common mode voltage errors and timing errors in a TSMC 0.18mu process. Less than 10mV offset can be easily achieved with the proposed structure making it favorable for flash and pipeline data conversion applications View full abstract»

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  • A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs

    Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2683 KB) |  | HTML iconHTML  

    In this paper, the nonlinearity error induced by interpolation amplifier in interpolating analog-to-digital converters (ADCs) is analyzed, and a new differential difference amplifier (DDA) with well restrained nonlinearity error is presented. Its highly steady common-mode output voltage makes it especially suitable for differential interpolating ADCs. The amplifier is designed in a 0.35mum standard CMOS process with a single 3.3V supply. Simulated results show that this amplifier achieves a steady common-mode output in a wide common-mode input range from 0.85V to 2.45V without demanding complex circuitry. The amplifier settles in 4.8ns to an accuracy of 0.01% and dissipates a total power of 398.38muW View full abstract»

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  • INL Prediction Method in Pipeline ADCs

    Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3168 KB) |  | HTML iconHTML  

    In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented View full abstract»

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  • Differential OPAMP with Inherent Common-Mode Control and Self-Biased Cascodes in 120nm CMOS

    Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3491 KB) |  | HTML iconHTML  

    A fully differential operational amplifier with high gain and high bandwidth in deep-sub-mum CMOS is presented. The operational amplifier has up to five serial connected stages. The shown signal-path concept is suitable to reach high gain and bandwidth. The used compensation avoids pole-zero doublet problems. Positive-feedback circuits are used to set the operating point of cascodes and load elements. Production costs are kept low by using only regular-threshold transistors in the design. A DC gain of 99dB and a transit frequency of 330MHz were measured View full abstract»

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  • Improving Source-Follower Buffer for High-Speed ADC Testing

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3374 KB) |  | HTML iconHTML  

    An improved CMOS buffer for high-speed ADC testing is presented. It is based on the circuit means to stabilize the DC output voltage of source-follower test buffer through the replica circuit and amplifier in a feedback loop to generate a regulated biasing voltage. With this biasing arrangement, the proposed test buffer maintains high-speed characteristics whilst yet preserving the headroom for test input signal and providing a defined DC output with immunity to variations of process, supply and temperature. In addition, the third-order harmonic distortion of the buffer is analyzed based on a large signal simplified BSIM3 model. The HSPICE simulation results validate the proposed work and correlate well with the distortion analysis on the basis of a standard 0.35 mum CMOS process at a single 3V supply View full abstract»

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  • 0.7 V Monolithic CMOS LNA for 802.11 A/B WLAN Application

    Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2969 KB) |  | HTML iconHTML  

    A new dual-band, 2.4 GHz and 5.2 GHz, LNA operating at supply voltage as low as 0.7 V, is designed and implemented for WLAN applications. The LNA uses 0.18 mum standard CMOS technology from UMC. It matches the input in two frequency bands easily without using extra on-chip spiral inductor, compared with (Li et al., 2004 and Hashemi and Hajimiri, 2001). The simulation exhibits input matching with S11 of -7.1 dB at 2.4 GHz and -21 dB at 5.2 GHz respectively. Moreover, it achieves power gain of 13.8 dB and 8.5 dB, noise figure 2.8 dB and 3.8 dB, and IIP3 -8.2 dBm and -1.5 dBm respectively View full abstract»

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  • A New Linearity Enhancing Technique for Low Noise Amplifiers

    Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3378 KB) |  | HTML iconHTML  

    In this paper a technique is proposed to enhance the linearity of low noise amplifier using nonlinearity of other components. This technique increases IIP3 of low noise amplifier without large increase in overall noise figure of LNA. This technique can be very useful for 802.11 b/g and Bluetooth applications where high linearity with low noise figure is required. Linearity improvement by use of nonlinear components is the basic idea for IIP3 improvement of this LNA. Currents produced by two amplifiers having different linearity characteristics are fed to current subtractor which gives current having good linearity characteristics but having a lower gain. Simulations based on layout of proposed architecture show that this architecture increases IIP3 up to 10+ dBm and the circuit is suitable for low noise applications. Amplifier achieves a gain of 10.5dB, noise figure of 1.5dB and dissipates 14.5 mwatts power from 1.8 volts supply View full abstract»

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  • A CMOS Current-Reused Transceiver with Stacked LNA and Mixer for WPAN

    Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3291 KB) |  | HTML iconHTML  

    A low power transceiver is designed in 0.25 mum CMOS technology. Designed transceiver is composed of CMOS PA and low-IF receiver architecture for high integration. To reduce the power dissipation, current-reused topology is used in Rx and up-conversion mixer. And, the simulated power consumption of PA is minimized by optimizing the size of power cells. The power consumptions are 31 mW and 69 mW for Rx and Tx paths, respectively, with 2.5 V supply voltage. Voltage conversion gain of designed receiver is varied from 11.5 to 27.5 dB. Output power is 14.7 dBm with 40 % of PAE at P1dB, and phase noise of QVCO is -122 dBc/Hz@1MHz. These performances are sufficient for WPAN applications such as Zig-Bee and Bluetooth View full abstract»

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  • 2.4 GHz High IIP3 and Low-Noise Down-conversion Mixer

    Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3318 KB) |  | HTML iconHTML  

    A RF mixer with low-voltage high performance for 2.4 GHz ISM band applications is presented. The novel topology mixer leads to better performance in terms of linearity, noise and power consumption for low supply voltage. Designed in TSMC 0.18mum CMOS technology, the mixer achieves: 9.3dB power conversion gain; 7.4dB noise figure; 8dBm input third-order intercept point (IIP3); and only 3.4mW of power consumption from a 1V supply voltage View full abstract»

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  • Compact Modeling of MOSFETs Channel Noise for Low-Noise RF ICs Design

    Page(s): 41 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3352 KB) |  | HTML iconHTML  

    A compact modeling of MOSFETs channel noise is proposed by considering short-channel effects of deep submicron MOSFETs, such as mobility degradation, hot carrier, bulk charge and channel length modulation effects. The model is only dependent on bias, size and technology of MOSFETs, and hence is suitable for low-noise RF ICs design. Noise parameters of MOSFETs are achieved and good agreement between calculated and measured results is demonstrated View full abstract»

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  • An 8 GHz Variable Gain Low Noise Amplifier (VGLNA) Utilizing Parallel Inter-Stage Resonance

    Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2746 KB) |  | HTML iconHTML  

    A two-stage variable gain low noise amplifier (VGLNA) topology is proposed, which adopts a parallel interstage resonance. The characteristics of the parallel inter-stage resonance in gain enhancement are analyzed and this is then followed by the application of a simple circuit consisted of two transistors as the variable gain stage. The VGLNA is designed and simulated based on a 0.18 mum CMOS technology for 8-GHz X-band applications. Simulation results show 13.63 dB of power gain, 3.60 dB of noise figure, 4.27 dBm of IIP3 and dc power supply of 1 V with 35.67 mA current drawn View full abstract»

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  • Digital Filter Design: Global Solutions via Polynomial Optimization

    Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB) |  | HTML iconHTML  

    This paper aims at introducing a new design tool based on polynomial optimization, which can be used to obtain globally optimal designs for stable IIR filters, single-stage and multistage frequency response masking filters, and digital filters with discrete coefficients, and many other types of filters and filter banks. We show how these design problems can be formulated as polynomial optimization problems (POPs) and present a simple numerical example to demonstrate the usefulness of this new design framework View full abstract»

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  • Design of Arbitrary FIR Digital Filters with Group Delay Constraint

    Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (143 KB) |  | HTML iconHTML  

    Arbitrary FIR digital filters with prescribed group delays are desirable in certain applications. It is in general not possible to design an FIR filter to meet the prescribed group delays exactly and the main objective is to minimize the group delay errors. This paper generalizes a method recently proposed by the authors in (Lin and Liu, 2006) for the design of band-selective FIR filters to the design of arbitrary FIR filters with prescribed group delays. Instead of adopting several approximations, the new method proposed in this paper uses an iterative method for updating the filter coefficients through a sequence of linear updates with each update carried out by taking both magnitude and group delay errors into account. The effectiveness and advantages of the proposed method are illustrated by a design example View full abstract»

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  • Symmetry Development for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay Filters

    Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (117 KB) |  | HTML iconHTML  

    The authors' previous work has derived an explicit formula for computing the coefficients of arbitrary-order Lagrange-type variable fractional-delay (VFD) digital filter in a closed-form. This paper develops new coefficient symmetry for efficiently implementing odd-order Lagrange-type VFD filters such that an odd-order Lagrange-type VFD filter can be implemented as the Farrow structure and more efficient even-odd structure whose all subfilters have either symmetric or anti-symmetric coefficients. This symmetry exploitation not only saves the storage for VFD filter coefficients and but also reduces the number of multiplications required in VFD filtering by 50%, which speeds up the VFD filtering process View full abstract»

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  • A Methodology for Automatic Hardware Synthesis of Multiplier-less Digital Filters with Prescribed Output Accuracy

    Page(s): 61 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4213 KB) |  | HTML iconHTML  

    This paper proposes a methodology for automatic synthesis of digital filters to meet prescribed output accuracy. Given a given frequency domain specification and output accuracy, a multiplier-less digital filter with canonical signed digits (CSD) will first be designed using advanced filter design techniques. A novel algorithm, based on geometric programming and marginal analysis methods, is proposed to optimize the hardware resources in terms of the internal wordlength of the digital filters to meet the prescribed output accuracy. Because of the use of CSD and multiplier block, the hardware resources can be greatly reduced. Using the system coefficients and wordlength information so obtained, a system for generating the corresponding VHDL codes was also developed. Automatic hardware synthesis is then employed to target the design to different platforms. The effectiveness of the proposed methodology is evaluated by the realization of a digital intermediate frequency receiver in field programmable gate arrays. Design results show that, the proposed methodology greatly reduces the design time of the system, while requiring much less hardware resources than conventional methods View full abstract»

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  • A New Method for Designing Constrained Causal Stable IIR Variable Digital Filters

    Page(s): 65 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3994 KB) |  | HTML iconHTML  

    This paper studies the design of causal stable Farrow-based IIR variable digital filters (VDFs), whose subfilters have a common denominator. This structure has the advantages of reduced implementation complexity and avoiding undesirable transient response when tuning the spectral parameter in the Farrow structure. The design of such IIR VDFs is based on a new model reduction technique which is able to incorporate prescribed flatness and peak error constraints to the IIR VDF under the second order cone programming framework. Design examples are given to demonstrate the effectiveness of the proposed approach View full abstract»

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  • New Structures for Single Filter Based Frequency-Response Masking Approach

    Page(s): 69 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3192 KB) |  | HTML iconHTML  

    New structures combining the frequency-response masking (FRM) and the single filter frequency masking (SFFM) techniques are presented for the design of arbitrary bandwidth sharp FIR filters. The newly introduced SFFM-FRM structures reduce the number of masking filters from two to one and yield significant savings in the number of arithmetic operations. The design example shows that the proposed filter leads to more than 35% savings in the number of multipliers compared with the original single-stage FRM approach View full abstract»

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  • 3D Shape Acquisition and Arbitrary View Image Generation from Monocular Image Based on Primitive Decomposition

    Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3679 KB) |  | HTML iconHTML  

    It is difficult to reconstruct 3D shape of an object from information of a monocular image. In this paper, the authors propose a method for 3D shape acquisition and arbitrary view image generation of objects on the ground. By using 3D spatial information of background and dividing object's shape into simple shape such as rectangular parallelepiped and triangle pole, the authors achieve to acquire it from a monocular image. In some experimental results, the authors show that 3D shape can be simply estimated and arbitrary view images can be generated from monocular vision View full abstract»

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  • Cauchy based Rate-Distortion Optimization Model for H.264 Rate Control

    Page(s): 77 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3712 KB) |  | HTML iconHTML  

    Base on the observation that Cauchy distribution provide accurate estimates of rate and distortion characteristics of video sequences, in this paper, we propose a Cauchy based rate-distortion optimization model for the application of H.264 bit allocation. Lagrange optimization is used as a tool to derive rate and distortion models subject to the target bit rate constraint resulting in optimum choice of quantization step sizes. Linear regression analysis is then used to update model parameters online. The technique proposed has been implemented in H.264 video encoder. Experimental results showed that the proposed rate control algorithm achieves an improvement of average PSNR of up to 0.68 dB with less PSNR variation compared to H.264 JM 8.6 rate control View full abstract»

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  • A Fast Watermarking System for H.264/AVC Video

    Page(s): 81 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4395 KB) |  | HTML iconHTML  

    In this paper, we propose a fast watermarking system that works on the H.264/AVC motion vectors. By restricting access to DCT coefficients and pixel information, the computational complexity of the watermark embedder/extractor is kept low and much lower than that of the H.264 decoder. The error propagation due to motion prediction compensation is monitored and its effect is limited by a tracking method that is based solely on the motion information from the bitstream. Although this work focuses on the H.264/AVC standard, the novel watermarking technique is also applicable to the MPEG1-2 and MPEG4 video standards View full abstract»

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  • A New Efficient Approach for Removal of Impulse Noise for Color Images

    Page(s): 85 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3491 KB) |  | HTML iconHTML  

    An efficient technique for impulsive noise detection and removal for color images is presented in this paper. In order to preserve edge/detail of image, filtering is performed only corrupted pixels. Thus, all noisy pixels should be detected. The pixels detected as noisy are regarded as the missing value. Thus, the interpolation technique can be used for estimating of missing value. In color natural images, all color channels have very similar characteristics such as texture and edge location. In the demosaicking problem of the charge-coupled device (CCD) samples, interpolation of the missing color component is performed using the available two other components. We can use the demosaicking methodology to estimating the value of noisy pixels. This paper presents a novel method for restoring impulsive noisy color images, which is constructed by the noise detector and the interpolator based on the demosaicking methodology View full abstract»

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  • A 0.18 μm CMOS Gaussian Monocycle Pulse Circuit Design for UWB

    Page(s): 89 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2920 KB) |  | HTML iconHTML  

    This paper proposes a new method of monocycle pulse generation by generating the Gaussian pulse, and generate first derivative of the pulse to get a Scholtz's monocycle pulse. The simulation result of the generation is based on 0.18 μm CMOS technology which achieved using HSPICE (Level 49). The Gaussian pulse is generated by using CMOS inverter of which is applied the delay time to perform the Gaussian pulse View full abstract»

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  • VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System

    Page(s): 93 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3615 KB) |  | HTML iconHTML  

    This paper presents a VLSI implementation of a high throughput MIMO-OFDM system in wireless communications. We explore the optimum parameters in a new packet OFDM frame by expanding the IEEE802.11a standard. The proposed system provides a maximum of 600 Mbps by use of an 80-MHz baseband bandwidth and a 2 times 2 MIMO scheme. The proposed system is implemented into hardware according to a full-pipelined architecture. In the MIMO detection circuit, we adopt a low latency architecture to satisfy the timing constraint required for real-time MIMO detection. In a 90-nm CMOS technology, the system performing MMSE-V-BLAST detection has 3.9 millions in logic gates and consumes 584 mW in power dissipation View full abstract»

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  • RaceCheck: A Race Logic Audit Program For SoC Designs

    Page(s): 97 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (70 KB) |  | HTML iconHTML  

    This paper describes RaceCheck, a new verification program that audits System-on-Chip (SoC) designs for race logic design errors. The unique features of RaceCheck are: it can perform both static and dynamic analysis to reveal hard-to-detect race logic, and it makes use of SoC designs' structural and timing information to suppress false violations. The static race logic analysis is testbench independent, and can be used in all stages of a SoC development. The dynamic race logic analysis uses an event-driven simulation kernel to execute a SoC operations, and reports the exact times, locations and frequency of occurrences of all detected race logic in the design. RaceCheck complements traditional design verification tools to aid users achieve 100 % functional coverage of their new SoC products and time-to-market View full abstract»

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