Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

4-6 Nov. 1992

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  • Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (Cat. No.92TH0481-2)

    Publication Year: 1992
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    Freely Available from IEEE
  • Practical application of automated fault diagnosis at the chip and board levels

    Publication Year: 1992, Page(s):297 - 304
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    As the sizes of electronic products grow larger, the process of diagnosing failed components becomes increasingly complex. The problem is compounded by the fact that there exists no unified system with which to diagnose problems at all levels of the product design-integrated circuit (IC), printed circuit board (PCB), and system. This paper presents the results of an industrial experiment with tech... View full abstract»

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  • A universal self-test design for chip, card and system

    Publication Year: 1992, Page(s):305 - 314
    Cited by:  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Describes an implementation of chip built-in self-test using by-pass boundary scan design. This basic structure is then modified to implement a universal self-test structure for cards, boxes and systems View full abstract»

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  • PLA decomposition to reduce the cost of concurrent checking

    Publication Year: 1992, Page(s):117 - 126
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Proposes a combination of PLA decomposition and unidirectional error detecting techniques which permits concurrent testing for all single faults in a circuit (both in the decomposed modules and on the interconnection lines), for a lower area overhead cost than is normally associated with unidirectional error detecting codes View full abstract»

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  • Improved layer assignment for packaging multichip modules

    Publication Year: 1992, Page(s):315 - 324
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The layer assignment problem plays an important role in packaging multichip modules, since the number of layers is directly related to the cost of the final product. In this paper, the authors propose a new model for the problem and a heuristic layer assignment algorithm based on the new model. The experimental results presented show that the solution provided by the algorithm is close to the lowe... View full abstract»

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  • Bridging faults modeling and detection in CMOS combinational gates

    Publication Year: 1992, Page(s):80 - 89
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    A method based on the detectability of bridging faults through test sets developed to locate other types of faults is presented. In particular it will be shown how bridging faults can be detected in CMOS combinational circuits using a test procedure that detects transistor stuck-at faults in a new design for testability for fully CMOS logic. The detection of more than 95% of the possible bridging ... View full abstract»

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  • Concurrent error detection in ALUs by recomputing with rotated operands

    Publication Year: 1992, Page(s):109 - 116
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Analyzes concurrent error detection in arithmetic logic units by recomputing with rotated operands by k bits (RERO-k). Even though RERO-k was suggested as an extension of recomputation with shifted operands by k bits (RESO-k), the RERO implementation for arithmetic operations and its application to carry lookahead adders have not been shown. It is claimed that complex control units should be used ... View full abstract»

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  • New routing and compaction strategies for yield enhancement

    Publication Year: 1992, Page(s):325 - 334
    Cited by:  Papers (16)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Improvements in manufacturing lines alone can not compensate for the yield losses due to the increase in complexity of logic. Manufacturing yield improvement needs to be addressed during the physical layout synthesis stage itself. Several layout strategies for yield enhancement are proposed and they are illustrated with respect to channel compaction and routing in standard cell design. Algorithms ... View full abstract»

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  • Recognition of catastrophic faults

    Publication Year: 1992, Page(s):70 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    For a given design, it is not difficult to identify a set of elements whose failure will have catastrophic consequence. There exist many patterns (random distribution) of faults, not in a block, which can be fatal for the system. Therefore, the characterization of such fault patterns is crucial for the identification, testing and detection of such catastrophic events. This paper, is concerned with... View full abstract»

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  • Time redundant error correcting adders and multipliers

    Publication Year: 1992, Page(s):247 - 256
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. Th... View full abstract»

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  • Time complexity of systolic array testing

    Publication Year: 1992, Page(s):100 - 108
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    The testing time for a C-testable orthogonal iterative systolic array (OISA) is derived where no knowledge on cell functions are assumed. The test inputs are regenerated as inputs for some inner cells at some future times at known distances (regeneration distances) from the outputs of those cells which are currently being tested. For minimum test time, it is required that the test input with maxim... View full abstract»

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  • Defect level estimation for digital ICs

    Publication Year: 1992, Page(s):32 - 41
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Defect level (DL) projections are very important in determining test quality and, thus, the market competitiveness of an integrated circuit (IC) product. However, at present, there is no way of accurately predicting DL in the IC design environment, since no accurate fault models are used. This paper presents a formalism and a method for DL estimation, based on a realistic fault model close to phys... View full abstract»

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  • Comparing results from defect-tolerant yield models

    Publication Year: 1992, Page(s):22 - 31
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    To date, many models have been developed to predict the yield of defect-tolerant integrated circuits (ICs). In this paper, results obtained from several of these models are compared. Their sensitivity to various model parameters is also examined. These results lead one to conclude that, despite differences in the predicted amount of redundancy, it may be possible to obtain good solutions. The diff... View full abstract»

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  • Fault spectrum analysis for fast spare allocation in reconfigurable arrays

    Publication Year: 1992, Page(s):60 - 69
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Repairing a reconfigurable array by row and column replacement using SR rows and SC columns was shown to be an NP -complete problem. In order to reduce the search time, the authors propose to apply a three phase procedure. In the first phase, they suggest using a heuristic to find good, but not necessarily optimal, feasible cover for the faulty array. Only if the heurist... View full abstract»

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  • Application of yield models for semiconductor yield improvement

    Publication Year: 1992, Page(s):237 - 266
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Yield models may be applied to increase the yield learning rate in semiconductor manufacture. Detailed equipment models can be used to predict the defect-limited yield from estimates of particles added per wafer pass. These general yield models may be refined to reflect specific processes, equipment, and design rules in more accurate critical area estimates. After validation, refined models can be... View full abstract»

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  • Probabilistic analysis of memory reconfiguration in the presence of coupling faults

    Publication Year: 1992, Page(s):157 - 166
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The problem of reconfiguring memory arrays using spare rows and spare columns has received a great deal of attention in recent years. However, most of the existing research assumes that the array contains only stuck-at faults. This paper, addresses the problem of reconfiguring memory arrays containing both stuck-at faults and coupling faults. The authors present a probabilistic model for studying ... View full abstract»

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  • Nondeterministic adaptive routing techniques for WSI processor arrays

    Publication Year: 1992, Page(s):177 - 186
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Presents new adaptive routing algorithms for faulty processor arrays. Past research has shown that packet switched based communication performance in mesh connected networks is significantly degraded by the presence of faulty processors. Nondeterministic routing algorithms have been developed based on transport modeling of packet flow in disordered arrays. By utilizing nondeterministic routing str... View full abstract»

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  • High-speed parallel input-output bit-sliced fault-tolerant convolvers

    Publication Year: 1992, Page(s):287 - 296
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    A family of convolvers for high sample rate is proposed, based on the composition of subconvolvers characterized by one bit samples and by modular, regular structures decomposable in identical bit-slices. Samples are represented in parallel or in skew form and the whole circuit is a sequential circuit whose combinatorial part is an array of full adders, assuring a high sampling rate. Fault toleran... View full abstract»

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  • Arithmetic codes for concurrent error detection in artificial neural networks: the case of AN+B codes

    Publication Year: 1992, Page(s):127 - 136
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    A number of digital implementations of neural networks have been presented in recent literature. Moreover, several authors have dealt with the problem of fault tolerance; whether such aim is achieved by techniques typical of the neural computation (e.g. by repeated learning) or by architecture-specific solutions, the first basic step consists clearly in diagnosing the faulty elements. The present ... View full abstract»

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  • Scan-based testability for fault-tolerant architectures

    Publication Year: 1992, Page(s):90 - 99
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The acceptance and use of standard scan-based test access ports (TAPs), such as the IEEE-1149.1-1990 standard, have begun to ease the task of system testability and in-circuit diagnostics. The typical singular nature of these TAPs along with the all-or-nothing manner in which test facilities are accessed make such standard TAPs inappropriate for use in fault-tolerant architectures. The authors pro... View full abstract»

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  • An efficient algorithm-based fault tolerance design using extended rearranged Hamming checksum

    Publication Year: 1992, Page(s):237 - 246
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Fault tolerance has been an important issue for systems involving intensive computations using a large number of processing elements. To effectively tolerate operation time faults in the systems, algorithm-based fault tolerance designs have been developed. Extended rearranged Hamming checksum scheme is proposed as an algorithm-based fault tolerance design. It is based on the rearranged Hamming che... View full abstract»

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  • Defect density assessment in an integrated circuit fabrication line

    Publication Year: 1992, Page(s):2 - 11
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Two complementary approaches used to detect and quantify defects in a wafer fabrication line are described. The first approach uses data from the automated inspection of wafers. Defects that are likely to become electrical faults are identified and classified with the aid of a KLA 2020 inspection system. The second approach uses electrical fault data from the automated testing of defect test struc... View full abstract»

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  • Efficient bi-level reconfiguration algorithms for fault tolerant arrays

    Publication Year: 1992, Page(s):42 - 51
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Considers the problem of reconfiguring processor arrays subject to computational loads that alternate between two modes. A strict mode is characterized by a heavy computational load and severe constraints on response time while a relaxed mode is characterized by a relatively light computational load and relaxed constraints on response time. In the strict mode, reconfiguration is performed by a dis... View full abstract»

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  • On fault probabilities and yield models for analog VLSI neural networks

    Publication Year: 1992, Page(s):167 - 176
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Investigates the estimation of fault probabilities and yield for analog VLSI implementations of neural computation. The analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. The work improves on the framework suggested recently by Feltham and Maly (1991) and is also applicable to analog or mixed analog/digital VLSI systems View full abstract»

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  • A fast pipelined complex multiplier: the fault tolerance issues

    Publication Year: 1992, Page(s):277 - 286
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A comprehensive discussion of a dedicated device for serial complex multiplication is presented, covering architectural, reliability and fault tolerance properties. The pipelined architecture is briefly described. It is optimized w.r.t. several figure of merits: clock rate, external pipelining and pipeline filling degree. Testability features are analyzed under functional fault models by means of ... View full abstract»

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