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Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on

Date 7-9 Oct. 1996

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Displaying Results 1 - 25 of 88
  • Proceedings International Conference on Computer Design. VLSI in Computers and Processors

    Publication Year: 1996
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    Freely Available from IEEE
  • Evaluation of high speed LAN protocols as multimedia carriers

    Publication Year: 1996 , Page(s): 93 - 98
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (533 KB)  

    The complexity of multimedia applications, which integrate a variety of information sources, such as audio, voice, graphics, images, animation, and full-motion video, into a wide range of applications, stresses all the components of computer and communication systems. Many new ideas have been proposed and implemented for advanced LAN (Local Area Network) protocols in order to support multimedia ne... View full abstract»

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  • Index of authors

    Publication Year: 1996 , Page(s): 587 - 589
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    Freely Available from IEEE
  • Early zero detection [integrated adder/subtracter/zero-detector]

    Publication Year: 1996 , Page(s): 545 - 550
    Cited by:  Papers (3)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (632 KB)  

    We present an integrated adder/subtracter/zero-detector in which the zero detection completes well before the sum or difference is known. Previous zero detectors either required the sum to be available before they could complete, or were not well integrated with the ALU. We avoid these problems by exploiting the properties of half-adder form. Sums in half-adder form can be computed very quickly (w... View full abstract»

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  • A new algorithm for division in hardware

    Publication Year: 1996 , Page(s): 551 - 556
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (544 KB)  

    This paper presents a new algorithm for fast hardware division, where two or three dividend bits are retired per iteration. The advantage that this algorithm has over radix-4 SRT is that it is much simpler requiring no lookup table and requiring the comparison of only one two-bit operand pair per iteration. Due to its simplicity, the new algorithm is much easier to implement and verify than radix-... View full abstract»

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  • On the nature and inadequacies of transport timing delay constructs in VHDL descriptions

    Publication Year: 1996 , Page(s): 128 - 130
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (260 KB)  

    The design of VHDL transport delay uses an implicit assumption that bus with multiple taps, only one tap is a driver and the signal reaches the other taps delayed only by the time necessary for the electro-magnetic propagation. Perturbation due to reflection at the intermediate taps, is ignored and this results in incorrect timing behavior. This paper proposes extensions to VHDL grammar and define... View full abstract»

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  • Microarchitecture support for reducing branch penalty in a superscaler processor

    Publication Year: 1996 , Page(s): 208 - 216
    Cited by:  Patents (20)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (776 KB)  

    This paper describes the microarchitecture of the 32-bit superscalar microprocessor GMICRO/400 with simple prejump mechanisms and its performance evaluation. GMICR0/400 has six stages of instruction execution pipeline and implements a dynamic branch prediction scheme, executing jump instructions in early stages. For dynamic branch predictions, GMICR0/400 contains a 1-Kbit table which holds a singl... View full abstract»

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  • Fault location based on circuit partitioning

    Publication Year: 1996 , Page(s): 242 - 247
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (668 KB)  

    We propose a method of fault diagnosis that reduces the number of simulations required to locate defect site(s) by logically partitioning the circuit into subcircuits. Candidate subcircuits that potentially contain the defect site(s) are identified and further partitioned, until the defect site is located with the required resolution. Experimental results are presented to demonstrate the effective... View full abstract»

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  • Design tradeoffs and experience with Motorola PowerPC migration tools

    Publication Year: 1996 , Page(s): 301 - 308
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (748 KB)  

    The Motorola PowerPC migration tools enable the conversion of assembly programs from other architectures to PowerPC. This paper describes the design approach and experience with the tool to translate x86 assembly programs to PowerPC. The key problems of handling 16-bit code, the effects of masking 16-bit operations into 32-bit registers and optimization of condition flags are discussed. The effici... View full abstract»

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  • DNA computations can have global memory

    Publication Year: 1996 , Page(s): 344 - 347
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (364 KB)  

    Ever since Adleman's seminal paper (1994) there has been a flood of ideas on how one could use DNA to compute. There have been many papers on using DNA to solve various computational problems. At the top-most level all these papers use DNA in the same way. Each strand of DNA encodes the state of a processor. Each processor operates independently: there is no communication from one processor to ano... View full abstract»

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  • FPGA module minimization

    Publication Year: 1996 , Page(s): 566 - 571
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (524 KB)  

    We examine the problem of minimizing the number of modules in an FPGA with combinational and sequential modules (like the C-modules and S-modules of the ACT2 and ACTS architectures). The constraint is that a combinational module can be combined with one flip-flop in a single sequential module, only if the combinational module drives no other combinational modules. We show that the problem of rearr... View full abstract»

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  • Exact dichotomy-based constrained encoding

    Publication Year: 1996 , Page(s): 426 - 431
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (588 KB)  

    Constrained encoding has several applications in the synthesis of finite state machines (FSMs), e.g., it can be used to generate asynchronous FSM state assignment that guarantees a critical hazard-free implementation, or to generate synchronous FSM state assignment with minimum PLA implementation. This paper presents ZEDICHO, an original zero-suppressed binary decision diagram (ZBDD) based algorit... View full abstract»

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  • Module generators for a regular analog layout

    Publication Year: 1996 , Page(s): 280 - 285
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (692 KB)  

    In general, automatic layout composition techniques based on pre-designed devices facilitate the production of small IC numbers by prefabricating their basic structures. They also enable a high degree of automatic layout synthesis. However for their correct electrical behavior it is essential, that potential problems caused by electro-magnetic compatibility (EMC) are fully considered during the de... View full abstract»

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  • Profile-driven generation of trace samples

    Publication Year: 1996 , Page(s): 217 - 224
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (792 KB)  

    Trace driven simulation is a common technique for evaluating different machine design options. Since the computing resources needed for simulation depend on the size of the trace, it is not always practical to use the complete trace of an application for simulation. This paper proposes a new technique, profile-driven sampling, for obtaining a reduced trace that is representative of the complete tr... View full abstract»

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  • The Augmint multiprocessor simulation toolkit for Intel x86 architectures

    Publication Year: 1996 , Page(s): 486 - 490
    Cited by:  Papers (28)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (564 KB)  

    Most publicly available simulation tools only simulate RISC architectures. These tools cannot capture the instruction mix and memory reference patterns of CISC architectures. We present an overview of Augmint, an execution driven multiprocessor simulation toolkit that fills this gap by supporting Intel x86 architectures. Augmint also supports trace driven simulation for uniprocessors as well as mu... View full abstract»

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  • A practical algorithm for retiming level-clocked circuits

    Publication Year: 1996 , Page(s): 440 - 445
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (612 KB)  

    A new approach for fast retiming of level-clocked circuits is presented. The method relies on the relation between clock skew and retiming, and computes the optimal skew solution to translate it to a retiming. Since clock skew optimization operates on the latches (rather than the gates as in conventional retiming), it is much faster because of a smaller problem size; the translation to the retimin... View full abstract»

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  • Design methodologies for tolerating cell and interconnect faults in FPGAs

    Publication Year: 1996 , Page(s): 326 - 331
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (664 KB)  

    Significant increases in chip yield can result if faulty logic cells and wiring in field programmable gate arrays (FPGAs) can be isolated from the remainder of the circuitry to retain a completely usable chip. Utilizing the principle of node-covering, a routing discipline has been developed that allows each logic cell in an FPGA to cover-to be able to replace-its neighbor in a row. An FPGA is fact... View full abstract»

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  • Modeling the difficulty of sequential automatic test pattern generation

    Publication Year: 1996 , Page(s): 261 - 271
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1192 KB)  

    This paper introduces a model which describes the cost of automatic test pattern generation for (non-scan) sequential logic in terms of attributes of the circuit under test. This model addresses a core issue involved in integrated circuit design and test trade-offs, and can be used to evaluate the cost effectiveness of potential design-for-testability (DFT) techniques. This knowledge can also be u... View full abstract»

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  • An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design

    Publication Year: 1996 , Page(s): 572 - 578
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (720 KB)  

    A novel algorithm, named SeqMapII, of technology mapping with retiming for optimal clock period for K-LUT based FPGAs was recently proposed by P. Pan and C.L. Liu (1996). The time complexity of their algorithm, however, is O(K3n4 log(Kn2) log n) for sequential circuits with n gates, which is too high for medium and large size designs in practice. In this paper, we ... View full abstract»

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  • Design and implementation of a new synchronization method for high-speed cell-based network interfaces

    Publication Year: 1996 , Page(s): 158 - 164
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (708 KB)  

    This paper presents the coding and timing recovery issues of an interface for high-speed cell-based communication networks. The synchronization technique used in this interface is based on the functionality resulting from combining functions of Fibre Channel with the basic features of pure ATM. The line coding properties, along with a pseudo-framing structure, are used to simplify the cell delinea... View full abstract»

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  • Can trace-driven simulators accurately predict superscalar performance?

    Publication Year: 1996 , Page(s): 478 - 485
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1012 KB)  

    There are four crucial issues associated with performance simulators: simulator retargetability, simulator validation, simulation speed and simulation accuracy. The paper documents our experiences in developing performance simulators and our recent findings in using these simulators. We are concerned with all four of the crucial issues. Our first generation tool, VMW, focused on achieving retarget... View full abstract»

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  • A scalable resistor-less PLL design for PowerPCTM microprocessors

    Publication Year: 1996 , Page(s): 293 - 300
    Cited by:  Papers (2)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (612 KB)  

    A new resistor-less phase locked loop implemented in a 2.5 V, 0.35 μm, CMOS technology is described. The design supports 13 different clock multiplier settings and uses a current-controlled-oscillator along with switched current sources to adjust the clock phase. Practical issues concerning system design and PLL stability parameters are also discussed. Simulation and characterization results sh... View full abstract»

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  • Multiplexor network generation in high level synthesis

    Publication Year: 1996 , Page(s): 78 - 83
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (532 KB)  

    In high level synthesis, after the binding stage, multiplexor network is generated to connect the outputs of modules (functional-units/registers) to the inputs of modules. In this paper we present an algorithm to generate a 2-to-1 multiplexor network with minimum number of multiplexors. Our algorithm is based on iteratively solving minimum vertex cover problems. Experimental results show that our ... View full abstract»

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  • Early quantification and partitioned transition relations

    Publication Year: 1996 , Page(s): 12 - 19
    Cited by:  Papers (17)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (936 KB)  

    Hardware systems are generally specified as a set of interacting finite state machines (FSMs). An important problem in formal verification using Binary Decision Diagrams (BDDs) is forming the transition relation of the product machine. This problem reduces to conjuncting (or multiplying) the BDDs representing the transition relations of the individual machines, and then existentially quantifying o... View full abstract»

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  • Latch redundancy removal without global reset

    Publication Year: 1996 , Page(s): 432 - 439
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (880 KB)  

    For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch removal assumes a designated initial state. Without this assumption, the design can power up in any state and earlier techniques are not applicable. We present an algorithm for identifying and replacing redundant latches by ... View full abstract»

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