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Proceedings International Conference on Computer Design. VLSI in Computers and Processors

7-9 Oct. 1996

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Displaying Results 1 - 25 of 88
  • Proceedings International Conference on Computer Design. VLSI in Computers and Processors

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (517 KB)
    Freely Available from IEEE
  • Evaluation of high speed LAN protocols as multimedia carriers

    Publication Year: 1996, Page(s):93 - 98
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (533 KB)

    The complexity of multimedia applications, which integrate a variety of information sources, such as audio, voice, graphics, images, animation, and full-motion video, into a wide range of applications, stresses all the components of computer and communication systems. Many new ideas have been proposed and implemented for advanced LAN (Local Area Network) protocols in order to support multimedia ne... View full abstract»

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  • Index of authors

    Publication Year: 1996, Page(s):587 - 589
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    Freely Available from IEEE
  • Testing of embedded A/D converters in mixed-signal circuit

    Publication Year: 1996, Page(s):135 - 136
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    In this paper, a complete functional testing of embedded ADC is presented. The integral non-linearity error, INLE, differential non-linearity error, DNLE, offset error, OSE, gain error and the signal-to-noise ratio, SNR are rested. The problem related to the propagation of the analog signal to the input of the ADC and the observation of the digital output of the converter at the output of the digi... View full abstract»

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  • Arithmetic pattern generators for built-in self-test

    Publication Year: 1996, Page(s):131 - 134
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Adders, subtracters, ALUs, and multipliers, which are available in many data paths, can be utilized to generate test patterns for built-in self-test. In this paper guidelines for the design of arithmetic pattern generators are developed. Experimental results show that the generated patterns achieve similar fault coverage as pseudo-random sequences and require about the same test length. Hence, ins... View full abstract»

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  • On the nature and inadequacies of transport timing delay constructs in VHDL descriptions

    Publication Year: 1996, Page(s):128 - 130
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    The design of VHDL transport delay uses an implicit assumption that bus with multiple taps, only one tap is a driver and the signal reaches the other taps delayed only by the time necessary for the electro-magnetic propagation. Perturbation due to reflection at the intermediate taps, is ignored and this results in incorrect timing behavior. This paper proposes extensions to VHDL grammar and define... View full abstract»

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  • Pausible clocking: a first step toward heterogeneous systems

    Publication Year: 1996, Page(s):118 - 123
    Cited by:  Papers (70)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous FIFO channel; communication between a module and the FIFO is done using a request/acknowledge handshaking. Synchronization of handshaki... View full abstract»

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  • Behavioral verification of an ATM switch fabric using implicit abstract state enumeration

    Publication Year: 1996, Page(s):20 - 26
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    We investigate equivalence checking of the RTL hardware implementation of the Cambridge Fairisle Asynchronous Transfer Mode (ATM) 4 by 4 switch fabric against a high-level behavioral specification which has unrestricted frame size, cell length and word width. The verification is based on the reachability analysis of the product machine of the implementation and the specification, both modeled as A... View full abstract»

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  • Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs

    Publication Year: 1996, Page(s):112 - 117
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    In this paper, we propose a novel fault-tolerance scheme, band reconfiguration, to handle multiple permanent faults in functional units of general ASIC designs. An associated high-level synthesis procedure that automatically generates such fault-tolerant systems is also presented. The proposed scheme permits multiple levels of graceful degradation. During each reconfiguration the system instantly ... View full abstract»

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  • Early quantification and partitioned transition relations

    Publication Year: 1996, Page(s):12 - 19
    Cited by:  Papers (20)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB)

    Hardware systems are generally specified as a set of interacting finite state machines (FSMs). An important problem in formal verification using Binary Decision Diagrams (BDDs) is forming the transition relation of the product machine. This problem reduces to conjuncting (or multiplying) the BDDs representing the transition relations of the individual machines, and then existentially quantifying o... View full abstract»

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  • Spare cutting approaches for repairing memories

    Publication Year: 1996, Page(s):106 - 111
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    This paper presents new algorithms for yield enhancement of redundant memories. These algorithms are based on the technique of spare cutting for a redundant memory chip in which repair is implemented by row/column deletion. Different approaches are proposed: some of these approaches are based on a fully exhaustive process, while others try to heuristically reduce the computational overhead involve... View full abstract»

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  • Enhancing FSM traversal by temporary re-encoding

    Publication Year: 1996, Page(s):6 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Synthesis and optimization of large finite-state machines has improved dramatically over the last few years with the introduction and rapid improvement of symbolic-state manipulation techniques. The algorithms efficiently visit each reachable state in the machine while computing and storing information about these states. We propose a new technique for improving the efficacy of traversal algorithm... View full abstract»

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  • A compact neural network based CDMA receiver for multimedia wireless communication

    Publication Year: 1996, Page(s):99 - 103
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A compact neural network receiver to process code division multiple access (CDMA) communication is presented. In CDMA system, near-far problem is a major impediment for the performance of a conventional detector. By using a compact neural network with hardware annealing function and combinatorial optimization technique, an optimal multiuser detector can be implemented. The algorithm and architectu... View full abstract»

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  • Large standard cell libraries and their impact on layout area and circuit performance

    Publication Year: 1996, Page(s):378 - 383
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    We present a complete study of layout area and circuit performance as a result of utilizing a large library of standard cells. We built libraries of all possible static CMOS cells having a chain length of up to 7. We refer to a library of all possible cells having a chain length limit of n as sn. Although library s7 has billions of possible cells in it, our technology mapper only selected on the o... View full abstract»

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  • Low voltage and low power: how low can you go?

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    Power management is an important design issue. For mobile electronics, the motivation is to extend battery life. For desktop systems, the design goal is to reduce audible noise from cooling fans which are a cause of annoyance, and to reduce the heat release in closed environments. For large systems, the motivation is to hold the packaging cost down. In communication applications, the limit on RF p... View full abstract»

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  • Multimodal query support in database servers

    Publication Year: 1996, Page(s):86 - 92
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    This paper introduces a novel approach to optimizing and monitoring database queries which involve operations on multiple data types in a parallel multimedia engine. Our approach uses dataflow graphs to represent the multimedia operations in a query. We have extended the Actors parallel programming model by designing an agent model for query execution that incorporates extensions for efficient dat... View full abstract»

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  • The use of random simulation in formal verification

    Publication Year: 1996, Page(s):371 - 376
    Cited by:  Papers (11)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    In this paper we present the application of random simulation in formal verification of functional equivalence of hardware designs. We demonstrate that random simulation can effectively complement BDD-based verification approaches in three areas: (1) quick generation of counter example pattern for miscomparing designs, (2) exhaustive comparison of small functions, and (3) providing meaningful sign... View full abstract»

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  • Clock-delayed domino for adder and combinational logic design

    Publication Year: 1996, Page(s):332 - 337
    Cited by:  Papers (23)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    An innovative dynamic logic family, clock-delayed (CD) domino, was developed to provide gates with either inverting or non-inverting outputs, and the high speed and layout compactness of dynamic logic. The characteristics of CD domino are demonstrated in two carry lookahead adder designs and three MCNC combinational logic benchmark circuits. The CD domino designs are compared to designs using stat... View full abstract»

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  • Multiplexor network generation in high level synthesis

    Publication Year: 1996, Page(s):78 - 83
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    In high level synthesis, after the binding stage, multiplexor network is generated to connect the outputs of modules (functional-units/registers) to the inputs of modules. In this paper we present an algorithm to generate a 2-to-1 multiplexor network with minimum number of multiplexors. Our algorithm is based on iteratively solving minimum vertex cover problems. Experimental results show that our ... View full abstract»

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  • RSFQ: What we know and what we don't

    Publication Year: 1996, Page(s):406 - 412
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    Rapid Single Flux Quantum (RSFQ) Josephson-junction technology is capable of processing digital data at sub-terahertz frequencies while dissipating almost negligible power. At the present time one can routinely simulate, optimize, design, manufacture, and test an elementary RSFQ logic/memory cell consisting of dozens of Josephson junctions. Furthermore, a number of relatively complex (few hundred ... View full abstract»

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  • Distributed binary decision diagrams for verification of large circuits

    Publication Year: 1996, Page(s):365 - 370
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Binary Decision Diagrams (BDDs) are widely used for efficiently representing logic designs and for verifying their equivalence. However, they often require large amounts of memory even for relatively small circuits. This paper presents a new mechanism for alleviating the memory consumption problem by exploiting the memory available in a cluster of workstations. The memory required for a BDD node m... View full abstract»

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  • Design methodologies for tolerating cell and interconnect faults in FPGAs

    Publication Year: 1996, Page(s):326 - 331
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    Significant increases in chip yield can result if faulty logic cells and wiring in field programmable gate arrays (FPGAs) can be isolated from the remainder of the circuitry to retain a completely usable chip. Utilizing the principle of node-covering, a routing discipline has been developed that allows each logic cell in an FPGA to cover-to be able to replace-its neighbor in a row. An FPGA is fact... View full abstract»

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  • A scalable resistor-less PLL design for PowerPCTM microprocessors

    Publication Year: 1996, Page(s):293 - 300
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    A new resistor-less phase locked loop implemented in a 2.5 V, 0.35 μm, CMOS technology is described. The design supports 13 different clock multiplier settings and uses a current-controlled-oscillator along with switched current sources to adjust the clock phase. Practical issues concerning system design and PLL stability parameters are also discussed. Simulation and characterization results sh... View full abstract»

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  • Optimal selection of supply voltages and level conversions during data path scheduling under resource constraints

    Publication Year: 1996, Page(s):72 - 77
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    In this paper we will consider how to select an optimal set of supply voltages and account for level conversion costs when optimizing the schedule of a resource dominated data path for minimum energy dissipation. An integer linear program (ILP) is presented for minimum energy schedules under latency, supply voltage, and resource constraints. The supply voltage assignment for each resource is model... View full abstract»

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  • Optimal single probe traversal algorithm for testing of MCM substrate

    Publication Year: 1996, Page(s):396 - 401
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    An algorithm for finding the optimal traversal route of a single probe to test MCM interconnects is presented. The goal of this work is to optimize the total distance traveled by a single test probe on an MCM substrate and thereby reduce the substrate testing time. It is assumed that only one terminal pad of each interconnection net is to be probed. Our algorithm is based on tour construction and ... View full abstract»

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