By Topic

Circuits, Devices & Systems, IET

Issue 2 • Date March 2013

Filter Results

Displaying Results 1 - 5 of 5
  • Effects of imbalance input on linearity of pseudodifferential ladder Gm-C filters

    Page(s): 51 - 58
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    This study presents distortion analysis of the fully differential Gm-C filters in which the imbalance of the differential input voltages is taken into consideration. Closed-form equations expressing distortions of differential-mode (DM) output voltages as functions of DM and common-mode input voltages are developed. It was found that the HD3 of the DM output voltage is independent of the input imbalance. On the contrary, the HD2 of the DM output voltage is directly dependent upon the input imbalance. Simulation results are shown to be in good agreement with the analytical results. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient ultra-high-voltage controller-based complementary-metal-oxide-semiconductor switched-capacitor DC-DC converter for radio-frequency micro-electro-mechanical systems switch actuation

    Page(s): 59 - 73
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1729 KB)  

    Achieving wireless connectivity in ever smaller, lower power portable devices with increasing number of features and better radio-frequency (RF) performance is becoming difficult to fulfill through existing RF front-end technology. RF micro-electro-mechanical systems (MEMS) switch technology, which has significantly better RF characteristics than conventional technology and has near-zero power consumption, is one of the emerging solutions for next generation RF front-ends. However, to achieve satisfactory RF MEMS device performance, it is often necessary to have an actuating circuitry to generate high direct current (DC) voltages for device actuation with low power consumption. In this study, the authors present an RF MEMS switch controller based on a switched-capacitor (SC) DC-DC converter in a 0.35 μm CMOS technology. In this design, novel design techniques for a higher output voltage and lower power consumption in a smaller die area are proposed. The authors demonstrate the design of the high-voltage (HV) SC DC-DC converter by using low-voltage transistors and address reliability issues in the design. Through the proposed design techniques, the SC DC-DC converter achieves more than 25% higher boosted voltage compared to converters that use HV transistors. The proposed design provides 40% power reduction through the charge recycling circuit. Moreover, the SC DC-DC converter achieves 45% smaller than the area of the conventional converter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical model for energy recovery circuit of plasma display panel data driver integrated circuit

    Page(s): 74 - 80
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    An analytical model is proposed to analyse the energy recovery circuit (ERC) efficiency of plasma display panel (PDP) data driver integrated circuit (IC). The experimental measurements agree with the analysis results very well. The analysis results show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time TERC, the channel resistor Ron and the capacitance of CL. The range of TERC is restricted in actual PDP system. CL is determined by physical parameters of PDP panel, and its value is nearly changeless. Therefore the ERC efficiency of PDP data driver IC can be improved significantly by using superior DPLD (double-channel p-type lateral extended drain metal oxidesemi conductor) transistor that has smaller Ron. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Embedded processor optimised for vascular pattern recognition

    Page(s): 81 - 92
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1118 KB)  

    In this study, the authors propose an efficient embedded processing architecture that uses the vascular pattern extraction (VPE) algorithm to authenticate a user to an embedded system. This study first considers the use of direction-based vascular pattern extraction (DBVPE), and analyses the computational workload involved in running software implementations on an embedded processor. The authors then present a comprehensive performance analysis of the VPE algorithm and examine in detail the various factors that contribute to processing latencies, including VPE recognition processing. In order to improve the efficiency of VPE processing in embedded devices, the authors offer details regarding the process needed to create a highly efficient application-specific processor and extend the base instruction set of the processor by using custom instructions for recognition processing. The authors implemented our proposed methodology in the context of a commercial extensible processor design flow using the Xtensa platform from Tensilica Inc. Our experiments show that our proposed methodology achieves a 3.95-fold increase in the vascular pattern recognition speed. Hence, the authors consider our technique to be efficient. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

    Page(s): 93 - 103
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 × 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IET Circuits, Devices & Systems covers circuit theory and design, circuit analysis and simulation, computer aided design,  filters, circuit implementations, cells and architectures for integration.

Full Aims & Scope

Meet Our Editors

Publisher
IET Research Journals
iet_cds@theiet.org