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Embedded Systems for Real Time Multimedia, Proceedings of the 2006 IEEE/ACM/IFIP Workshop on

Date 26-27 Oct. 2006

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  • [Front cover]

    Publication Year: 2006 , Page(s): C1
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  • [Title page]

    Publication Year: 2006 , Page(s): C2
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  • Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia

    Publication Year: 2006 , Page(s): i
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  • Copyright page

    Publication Year: 2006 , Page(s): ii
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  • [Commentary]

    Publication Year: 2006 , Page(s): iii
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  • Conference committee

    Publication Year: 2006 , Page(s): iv
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  • Table of contents

    Publication Year: 2006 , Page(s): v - vi
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 1
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 5
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 19
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 39
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 65
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 85
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 99
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  • [Breaker page]

    Publication Year: 2006 , Page(s): 113
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  • Real-time processing on configurable multimedia systems

    Publication Year: 2006 , Page(s): 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (27 KB) |  | HTML iconHTML  

    This paper shows the actually measured response times that can be achieved with Linux configurations on Virtex processor+FPGA architectures, containing both hard PowerPC processors or soft Microblaze processors and FPGA fabric. How the various response times drive system design is shown in this paper. The trade-off between the part of an application that can be handled with a real-time operating system, a hard-coded software loop and accelerators configured in FPGA fabric. A system performing HDTV rate image processing will also be discussed View full abstract»

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  • Recent developments in video compression standards and their impact on implementation complexity: From scalable to multi-view video coding

    Publication Year: 2006 , Page(s): 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (28 KB) |  | HTML iconHTML  

    This paper focuses on the implementation challenges of recent developments in video compression standards. The collaborative effort, which goes under the name of joint video team (JVT), has recently completed the standardization of the new H.264/MPEG-4 advanced video coding (AVC) standard. The scalable video coding (SVC), will be standardized as an amendment to MPEG-4 Part 10 AVC/ITU-T 1-1.264. The goal of this amendment is to provide scalability at the bit-stream level, with good compression efficiency, and allowing free combinations of scalable modes. In addition to SVC, JVT recently started to work on extending H.264/MPEG-4 AVC to include multiple-view video coding (MVC) techniques, i.e. an encoding framework for multiple video streams and associated camera parameters. MVC is a key technology that serves a wide variety of applications, including free-viewpoint television, 3D television, and surveillance View full abstract»

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  • Hardware/Software Partitioned Implementation of Real-time Object-oriented Camera for Arbitrary-shaped MPEG-4 Contents

    Publication Year: 2006 , Page(s): 7 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6543 KB) |  | HTML iconHTML  

    Recently developed MPEG-4 part 2 compression standard provides a novel capability to handle arbitrary video objects. To support this capability, an efficient object segmentation technique is required. This paper proposes a real-time algorithm for foreground object segmentation in video sequences. The proposed algorithm consists of two steps: the first step that segments a frame into several sub-regions using spatio-temporal watershed transform and the second one that extracts a foreground object segment from the sub-regions generated in the first step. For real-time processing, the algorithm is partitioned into hardware and software parts so that computationally expensive parts are off-loaded from a processor and executed by hardware accelerators. Simulation results show that the proposed implementation can handle QCIF-size video at 15 fps to extract an accurate foreground object View full abstract»

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  • A Low Complexity MPEG Video Decoder with Arbitrary Downscaling Capability

    Publication Year: 2006 , Page(s): 13 - 18
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5518 KB) |  | HTML iconHTML  

    This paper presents some new techniques to implement arbitrary downscaling in decoding MPEG video with very low complexity. The DCT block recomposition method, which was used in resizing static image, is introduced to downscale video in frequency domain with arbitrary factors. New motion compensation based on the block group motion evaluation is proposed to correspond to the downscaled IDCT. Block groups of regular motion and irregular motion are handled respectively to balance the computation cost and picture quality. Analysis indicates the great complexity reduction and experiments show the decoder performance on the MPEG-4 video sequence. These techniques will be beneficial to the video applications on the mobile devices and many other low end embedded systems View full abstract»

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  • An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems

    Publication Year: 2006 , Page(s): 21 - 26
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    The design exploration procedure of DSP systems using simulation tools is a time-consuming process, even for low complexity applications. The main goal of the design methodology introduced in this paper is to provide fast and accurate estimates of the number of (-micro) instructions and the instruction cache miss rate of DSP applications implemented on a programmable embedded platform, during the early design phases. Specific information is extracted from both the high-level code description (C code) of the DSP application considered and its corresponding assembly code, without carrying out any kind of simulation. The proposed methodology requires only a single execution of the application in a general-purpose processor and uses only the assembly code of the targeted embedded processor. In order to automate the estimation procedure, a new software tool, which implements the proposed methodology, has been developed. Using nine real-life applications from different domains of the DSP field, it has been proved that with the proposed methodology the number of instructions and the miss rate of instruction cache can be estimated with high accuracy (>95%). Furthermore, the required time cost is much smaller (orders of magnitude) than the simulation-based approaches View full abstract»

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  • A Mixed-level Co-simulation Method for System-level Design Space Exploration

    Publication Year: 2006 , Page(s): 27 - 32
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (131 KB) |  | HTML iconHTML  

    The Sesame modeling and simulation framework aims at efficient system-level design space exploration of embedded multimedia systems. A primary objective of Sesame is the exploration at multiple levels of abstraction. As such, it targets gradual refinement of its (initially abstract) architecture performance models while maintaining architecture-independent application specifications. In this paper, we present a mixed-level co-simulation method, called trace calibration, for incorporating external simulators into Sesame's abstract system-level performance models. We show that trace calibration only requires minor modification of the incorporated simulators and that performance overheads due to co-simulation are minimal. Also, we show that trace calibration transparently supports distributed co-simulation, allowing for effectively reducing the system-level simulation slowdown due to the incorporation of lower-level simulators View full abstract»

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  • Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip

    Publication Year: 2006 , Page(s): 33 - 38
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    Increasingly more MPSoC platforms are being developed to meet the rising demands from concurrently executing applications. These systems are often heterogeneous with the use of dedicated IP blocks and application domain specific processors. While there is a host of research done to provide good performance guarantees and to analyze applications for preemptive uniprocessor systems, the field of heterogeneous, non-preemptive MPSoCs is a mostly unexplored territory. In this paper, we propose to use a resource manager (RM) to improve the resource utilization of these systems. The basic functionalities of such a component are introduced. A high-level simulation model of such a system is developed to study the performance of RM, and a case study is performed for a system running an H.263 and a JPEG decoder. The case study illustrates at what control granularity a resource manager can effectively regulate the progress of applications such that they meet their performance requirements View full abstract»

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  • High-Level Power Management of Audio Power Amplifiers for Portable Multimedia Applications

    Publication Year: 2006 , Page(s): 41 - 46
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (434 KB) |  | HTML iconHTML  

    Modern hand-held multimedia devices are equipped with high-power audio subsystems with built-in loudspeakers. These audio subsystems consume around 30% of the total system power, due to the poor efficiency of loudspeakers, even though high-efficiency class-D amplifiers are used. We introduce an elaborated system-level approach to the analysis of power consumption in amplifiers and consequent power saving for hand-held multimedia applications. Loudspeakers act like resistors below the resonant region and above the linear region, dissipating battery power without producing audible sound output. We exploit the poor frequency response of typical built-in miniature loudspeakers with inadequate enclosures, and limit the production of unnecessary frequencies that never become recognizable sound. We achieve up to 23% and 35% power reduction without appreciable fidelity degradation, with an SNR (signal to noise ratio) of 33% and 35%, for a class-AB and class-D amplifiers, respectively. All the data and experimental results in this paper are actual measurements using our in-house audio power analysis platform View full abstract»

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  • Annotation Based Multimedia Streaming Over Wireless Networks

    Publication Year: 2006 , Page(s): 47 - 52
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB) |  | HTML iconHTML  

    The relatively high power consumption of wireless network interfaces represents an important detriment in multimedia streaming for mobile devices. The IEEE 802.11 built-in power saving mode was designed for transfers of different nature and is not able to take advantage of the short idle intervals and continuous, periodic transmissions inherent in multimedia streaming. We propose an annotation based approach to wireless network power management that analyzes the variations in data transfer bandwidth during playback and uses the results to buffer data into larger burst transmissions with longer idle periods when the network card is transitioned into a lower power, sleep mode. Annotations allow for energy savings of up to 75% for the network interface, with practically no quality degradation or packet loss, only a small delay due to the buffer View full abstract»

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  • A Low-Power Implementation of 3D Graphics System for Embedded Mobile Systems

    Publication Year: 2006 , Page(s): 53 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6266 KB) |  | HTML iconHTML  

    For mobile 3D graphics systems, even though performance requirements are met, an efficient power management is even more important for battery-powered mobile devices since they require a large number of arithmetic operations as well as a high frequency of memory accesses. According to the analysis of the power consumption of mobile 3D graphics pipelines and the slacks across the pipeline stages, we describe intra-frame and inter-frame DVS low-power techniques reducing the power consumption of mobile devices based on a variable voltage processor. Our implementation on a PDA development board shows that the proposed DVS techniques achieve an energy saving of up to 46% over a non-DVS implementation View full abstract»

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