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Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on

Date 29-30 Oct. 2006

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Displaying Results 1 - 25 of 42
  • 2006 IEEE Dallas / CAS Workshop on Design, Applications, Integration and Software (DCAS-06)

    Publication Year: 2006 , Page(s): nil1
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  • 2006 IEEE Dallas / CAS Workshop on Design, Applications, Integration and Software (DCAS-06)

    Publication Year: 2006 , Page(s): i
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  • [Copyright notice]

    Publication Year: 2006 , Page(s): ii
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  • Foreword

    Publication Year: 2006 , Page(s): iii
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  • Organizing Committee

    Publication Year: 2006 , Page(s): iv
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  • Fifth IEEE Dallas Circuits and Systems Workshop

    Publication Year: 2006 , Page(s): v
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  • Program for the 5th IEEE Dallas/CAS Workshop (DCAS-06)

    Publication Year: 2006 , Page(s): vi - viii
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  • Table of contents

    Publication Year: 2006 , Page(s): ix - x
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  • Short distance wireless and its opportunities

    Publication Year: 2006
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4554 KB)  

    Short distance wireless presents a huge window of opportunity. It needs clear metrics to allow for classification of different approaches in terms of energy and size efficiency. Power and size are dominated by need for precision time and frequency references and can be overcome through innovative system solutions. Short distance wireless may ultimately lead to novel computation and communication models. View full abstract»

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  • Mixed-Domain Signal Processing

    Publication Year: 2006 , Page(s): 9 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3971 KB)  

    We argue that mixing domains within circuits and systems can result in new possibilities. We have presented several examples of mixed-domain systems. Internally time-varying (but externally time-invariant) circuits can be designed to consume only the minimum power needed for each task at hand. Several techniques have been presented for making this possible, while avoiding output transients. Internally nonlinear (but externally linear) digital filters make possible 1) keeping internal signal strength large, even for small-strength inputs and 2) maximizing signal-to-error ratio for a large range of input signals. Continuous-time DSP may offer certain advantages of digital technology without its drawbacks: 1) fully digital (noise immunity, programmability), 2) no sampling; thus no signal aliasing, 3) smaller in-band quantization error, and 4) power goes down with decreasing input activity. All of the principles discussed are at the early research stage; none has reached commercial feasibility. Thorough experimental validation and application of some of the principles presented are being pursued View full abstract»

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  • Cellular handset integration

    Publication Year: 2006
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2940 KB) |  | HTML iconHTML  

    The article examines cellular wireless evolution from 1G (analog cellular) up to the present day, 4G (wideband network). The following conclusions are made: approximately 1 billion phones/year to be produced; cost challenge in low end market; there are higher costs, areas and power in the high end; lots of air interfaces are available; Moore's Law meets logic and memory challenge; single-chip integration offers compelling benefit for analog/RF; and new air interfaces are coming soon. View full abstract»

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  • Digitally Assisted Analog Circuits; Fifth IEEE Dallas Circuits and Systems Workshop

    Publication Year: 2006 , Page(s): 23 - 30
    Cited by:  Papers (1)
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    This paper presents compelling reasons for "digitally assisting" analog functions and important design considerations. ADCs, power amplifier, and MEMS accelerometer are used as examples. In a variety of analog circuits, "digital assistance" can be used to offload accuracy constraints to a digital processor. Key benefits are lower power and potentially higher speed and compatibility with "ultimately scaled CMOS" while key challenges are interdisciplinary nature of design problem; device modeling, circuit design, signal processing algorithms, and consideration of application layer; and design complexity and turnaround time View full abstract»

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  • Reversible Computing and Truly Adiabatic Circuits: Truly Adiabatic Circuits: The Next Great Challenge for Digital Engineering

    Publication Year: 2006 , Page(s): 31 - 38
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5974 KB)  

    This paper provides a brief review of the energy dissipation problem in conventional FET-based logic. Some alternative device switching principles that might help with this problem in the relatively near term are described. Fundamental limits to dissipation that apply to any non-energy-recovering digital technology are described. Elements required as part of any long-term solution (i.e. adiabatic switching, reversible logic, and resonant clocking) are discussed View full abstract»

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  • High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems

    Publication Year: 2006 , Page(s): 39 - 42
    Cited by:  Papers (12)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. Based on architecture-aware LDPC codes, we propose an efficient joint LDPC coding and decoding hardware architecture. The prototype architecture is being implemented on FPGA and tested over the air on our wireless OFDM testbed, which is a highly capable, scalable and extensible platform for advanced wireless research. The ASIC resource requirements of the decoder are reported and a trade-off between pipelined and non-pipelined implementation is described View full abstract»

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  • Power-Supply Noise Attributed Timing Jitter in Nonoverlapping Clock Generation Circuits

    Publication Year: 2006 , Page(s): 43 - 46
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (165 KB) |  | HTML iconHTML  

    This paper describes an analysis of timing jitter induced by power-supply noise in nonoverlapping clock generation circuits typically used in switched-capacitor sigma-delta modulators. Substrate noise effects are also included but not treated as a separate phenomenon since the MOSFET bulk contacts are connected to the power-supply or ground. Two different nonoverlapping clock generation circuits have been compared and treated independently: the NOR based and the NAND based architectures. Furthermore, all possible connection topologies of the circuit blocks in the clock generation circuits are investigated. Monte Carlo simulations have been performed in Spectre at BSIM3v3 transistor model level using parameters from a 0.18mum process to show which of the topologies is most suitable as clock generator for wideband applications. In terms of timing jitter sensitivity to power-supply noise, the NOR based architecture is slightly more robust and suitable for providing a timing reference to a sampling circuit View full abstract»

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  • Optimal Gate Size Selection for Standard Cells in a Library

    Publication Year: 2006 , Page(s): 47 - 50
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3875 KB) |  | HTML iconHTML  

    Standard cell libraries provide designers with a fixed set of well characterized logic blocks. As designs are pushed for high performance, low area, and low power, it is essential to have a, good standard cell library that can help achieve these goals. As gate sizing is crucial to timing, the number of gate sizes (drive strengths) available for each of the primitives is an important factor to be considered. While an infinite granularity of gate sizes is preferable to get the best entitlement, it is often impractical due to the huge cost associated with developing and maintaining libraries. It is therefore essential to find ways to achieve the best performance, power and area, with a, reasonable library size. In this paper we focus on the problem of finding out the optimal ratio of gate sizes to be selected. 65nm libraries were used for validating the claims on a real design and the results are presented in this paper View full abstract»

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  • Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability

    Publication Year: 2006 , Page(s): 51 - 54
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    Compact synthesis result for reversible logic is of major interest in low-power design and quantum computing. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoli gates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boolean satisfiability (SAT) instances. Such an instance is satisfiable iff there exists a network representation with d gates. Thus we can guarantee minimality. For a set of benchmarks experimental results are given View full abstract»

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  • Grand Challenge: The Future of CMOS System-on-Chip Hardware and Software Application Development

    Publication Year: 2006 , Page(s): 55 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB) |  | HTML iconHTML  

    CMOS technology trends are forcing system designers to use multiple processors on a single die to meet power performance objectives. Power performance optimization also leads to heterogeneous combinations of processors, DSP units, ASSPs and FPGAs. Both of these trends exacerbate the crisis in software productivity. New tools, languages and implementation techniques must be utilized to ensure achievement of time-to-market objectives for today's system-on-chip designs. Several examples are included to illustrate the problems, issues and opportunities as systems on chips drive towards hundreds of concurrent processes. These issues and their successful resolution are expected to cut across hardware and software boundaries and pervade the electronics industry as the drive for power performance continues over the coming decade View full abstract»

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  • A Built-in Tester for Modulation Noise in a Wireless Transmitter

    Publication Year: 2006 , Page(s): 59 - 62
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4656 KB) |  | HTML iconHTML  

    A fully digital implementation for an RF built-in self-test (RF BIST), incorporated within a digital RF processor (DRPtrade)-based system-on-chip (SoC), is presented. The proposed mechanism serves as an on-chip built-in modulation-noise estimation-module (BIMNEM) for the testing of the 2.4 GHz local oscillator of a Bluetooth transceiver offered by Texas Instruments. This SoC, realized in a standard 130 nm digital CMOS process, is being tested in mass production using a digital very-low-cost-tester (VLCT) that leverages on the internal test capabilities of the SoC, thereby minimizing test costs. Experimental results are shown and the extension of this approach for implementation in the later generations of DRP based SoCs is briefly discussed View full abstract»

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  • Efficient Procedures for Analyzing Large-Scale RF Circuits

    Publication Year: 2006 , Page(s): 63 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    The majority of CAD tools have limited modes of the sensitivity analysis: PSPICE only contains a static mode and SPECTRE includes frequency domain and static modes. However, many RF systems use symmetrical structures for enhancing the properties of the circuits. For such systems, the static sensitivities are zero in principle and therefore the time domain sensitivity analysis must be used. In the paper, a new recurrent formula for the time domain sensitivity analysis is derived, which uses by-products of an implicit integration algorithm. Moreover, for a very fast estimation of mixed products, an efficient procedure is described, which is also not implemented in PSPICE. Both methods are demonstrated by analyses of a four-quadrant RF multiplier View full abstract»

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  • Feedforward Interference Cancellation in Narrow-Band Receivers

    Publication Year: 2006 , Page(s): 67 - 70
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (114 KB) |  | HTML iconHTML  

    Design considerations related to feedforward interference cancellation in a narrow-band receiver are discussed. A design is presented that distributes the noise and linearity requirements across two parallel receiver branches. Simulation results from a 1GHz front-end designed in a UMC-0.13mum CMOS process are presented View full abstract»

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  • Analog-to-Information Conversion via Random Demodulation

    Publication Year: 2006 , Page(s): 71 - 74
    Cited by:  Papers (80)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    Many problems in radar and communication signal processing involve radio frequency (RF) signals of very high bandwidth. This presents a serious challenge to systems that might attempt to use a high-rate analog-to-digital converter (ADC) to sample these signals, as prescribed by the Shannon/Nyquist sampling theorem. In these situations, however, the information level of the signal is often far lower than the actual bandwidth, which prompts the question of whether more efficient schemes can be developed for measuring such signals. In this paper we propose a system that uses modulation, filtering, and sampling to produce a low-rate set of digital measurements. Our "analog-to-information converter" (AIC) is inspired by the theory of compressive sensing (CS), which states that a discrete signal having a sparse representation in some dictionary can be recovered from a small number of linear projections of that signal. We generalize the CS theory to continuous-time sparse signals, explain our proposed AIC system in the CS context, and discuss practical issues regarding implementation View full abstract»

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  • A Fixed-Point Implementation for QR Decomposition

    Publication Year: 2006 , Page(s): 75 - 78
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (135 KB) |  | HTML iconHTML  

    Matrix triangularization and orthogonalization are prerequisites to solving least square problems and find applications in a wide variety of communication systems and signal processing applications such as MIMO systems and matrix inversion. QR decomposition using modified Gram-Schmidt (MGS) orthogonalization is one of the numerically stable techniques used in this regard. This paper presents a fixed point implementation of QR decomposition based on MGS algorithm using a novel LUT based approach. The proposed architecture is based on log-domain arithmetic operations. The error performance of various fixed-point arithmetic operations has been discussed and optimum LUT sizes are presented based on simulation results for various fractional-precisions. The proposed architecture also paves way for an efficient parallel VLSI implementation of QR decomposition using MGS View full abstract»

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  • Design Methodology of On-Chip Power Distribution Network

    Publication Year: 2006 , Page(s): 79 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4237 KB) |  | HTML iconHTML  

    The effect of the capacitors in the power distribution network (PDN) was reviewed based on electromagnetic theory. It was clarified that the capacitors used in the PDN are not suitable for high-frequency decoupling or for lowering the impedance. Based on this result, a novel design methodology of an on-chip PDN is proposed in this paper. The low-impedance lossy line (LILL) technology is used as the PDN instead of capacitors and other components. This methodology improves both the performance of the SoC and also the signal transmission rate markedly because the LILL in the PDN shortens the rise time of the signal. An analysis of the effect of the novel design methodology, SPICE simulation result, and an example of an on-chip LILL structure for the SoC are presented in this paper View full abstract»

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  • Phase Noise Reduction in High Speed Frequency Divider

    Publication Year: 2006 , Page(s): 83 - 86
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4119 KB) |  | HTML iconHTML  

    Maximum operating frequency, phase noise characteristics close to output carrier frequency and power consumption during operation are major parameters of a frequency divider. Since these parameters are interrelated, design optimization involves tradeoffs among them. A new differential D-latch based topology for a low phase noise frequency divider for cellular transceivers is presented. An optimization process for the design of frequency divider is given and various phenomena that dominate phase noise and high frequency behavior of the frequency dividers are discussed. The proposed divider designed using 65 nm CMOS has a maximum input frequency of 11.8 GHz with phase noise level of 153.3 dBc/Hz at an offset of 20 MHz. It consumes 11 mA average current while operating at a nominal frequency of 8 GHz View full abstract»

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