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2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software

Date 29-30 Oct. 2006

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  • 2006 IEEE Dallas / CAS Workshop on Design, Applications, Integration and Software (DCAS-06)

    Publication Year: 2006, Page(s): nil1
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  • 2006 IEEE Dallas / CAS Workshop on Design, Applications, Integration and Software (DCAS-06)

    Publication Year: 2006, Page(s): i
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  • [Copyright notice]

    Publication Year: 2006, Page(s): ii
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  • Foreword

    Publication Year: 2006, Page(s): iii
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  • Organizing Committee

    Publication Year: 2006, Page(s): iv
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  • Fifth IEEE Dallas Circuits and Systems Workshop

    Publication Year: 2006, Page(s): v
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  • Program for the 5th IEEE Dallas/CAS Workshop (DCAS-06)

    Publication Year: 2006, Page(s):vi - viii
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  • Table of contents

    Publication Year: 2006, Page(s):ix - x
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  • Short distance wireless and its opportunities

    Publication Year: 2006
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4554 KB) | HTML iconHTML

    Short distance wireless presents a huge window of opportunity. It needs clear metrics to allow for classification of different approaches in terms of energy and size efficiency. Power and size are dominated by need for precision time and frequency references and can be overcome through innovative system solutions. Short distance wireless may ultimately lead to novel computation and communication m... View full abstract»

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  • Mixed-Domain Signal Processing

    Publication Year: 2006, Page(s):9 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3971 KB) | HTML iconHTML

    We argue that mixing domains within circuits and systems can result in new possibilities. We have presented several examples of mixed-domain systems. Internally time-varying (but externally time-invariant) circuits can be designed to consume only the minimum power needed for each task at hand. Several techniques have been presented for making this possible, while avoiding output transients. Intern... View full abstract»

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  • Cellular handset integration

    Publication Year: 2006
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2940 KB) | HTML iconHTML

    The article examines cellular wireless evolution from 1G (analog cellular) up to the present day, 4G (wideband network). The following conclusions are made: approximately 1 billion phones/year to be produced; cost challenge in low end market; there are higher costs, areas and power in the high end; lots of air interfaces are available; Moore's Law meets logic and memory challenge; single-chip inte... View full abstract»

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  • Digitally Assisted Analog Circuits; Fifth IEEE Dallas Circuits and Systems Workshop

    Publication Year: 2006, Page(s):23 - 30
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (653 KB) | HTML iconHTML

    This paper presents compelling reasons for "digitally assisting" analog functions and important design considerations. ADCs, power amplifier, and MEMS accelerometer are used as examples. In a variety of analog circuits, "digital assistance" can be used to offload accuracy constraints to a digital processor. Key benefits are lower power and potentially higher speed and compatibility with "ultimatel... View full abstract»

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  • Reversible Computing and Truly Adiabatic Circuits: Truly Adiabatic Circuits: The Next Great Challenge for Digital Engineering

    Publication Year: 2006, Page(s):31 - 38
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5974 KB) | HTML iconHTML

    This paper provides a brief review of the energy dissipation problem in conventional FET-based logic. Some alternative device switching principles that might help with this problem in the relatively near term are described. Fundamental limits to dissipation that apply to any non-energy-recovering digital technology are described. Elements required as part of any long-term solution (i.e. adiabatic ... View full abstract»

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  • High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems

    Publication Year: 2006, Page(s):39 - 42
    Cited by:  Papers (17)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (238 KB) | HTML iconHTML

    This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. Based on architecture-aware LDPC codes, we propose an efficient joint LDPC coding and decoding hardware architecture. The prototype ar... View full abstract»

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  • Power-Supply Noise Attributed Timing Jitter in Nonoverlapping Clock Generation Circuits

    Publication Year: 2006, Page(s):43 - 46
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (165 KB) | HTML iconHTML

    This paper describes an analysis of timing jitter induced by power-supply noise in nonoverlapping clock generation circuits typically used in switched-capacitor sigma-delta modulators. Substrate noise effects are also included but not treated as a separate phenomenon since the MOSFET bulk contacts are connected to the power-supply or ground. Two different nonoverlapping clock generation circuits h... View full abstract»

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  • Optimal Gate Size Selection for Standard Cells in a Library

    Publication Year: 2006, Page(s):47 - 50
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3875 KB) | HTML iconHTML

    Standard cell libraries provide designers with a fixed set of well characterized logic blocks. As designs are pushed for high performance, low area, and low power, it is essential to have a, good standard cell library that can help achieve these goals. As gate sizing is crucial to timing, the number of gate sizes (drive strengths) available for each of the primitives is an important factor to be c... View full abstract»

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  • Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability

    Publication Year: 2006, Page(s):51 - 54
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (119 KB) | HTML iconHTML

    Compact synthesis result for reversible logic is of major interest in low-power design and quantum computing. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoli gates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boole... View full abstract»

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  • Grand Challenge: The Future of CMOS System-on-Chip Hardware and Software Application Development

    Publication Year: 2006, Page(s):55 - 58
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB) | HTML iconHTML

    CMOS technology trends are forcing system designers to use multiple processors on a single die to meet power performance objectives. Power performance optimization also leads to heterogeneous combinations of processors, DSP units, ASSPs and FPGAs. Both of these trends exacerbate the crisis in software productivity. New tools, languages and implementation techniques must be utilized to ensure achie... View full abstract»

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  • A Built-in Tester for Modulation Noise in a Wireless Transmitter

    Publication Year: 2006, Page(s):59 - 62
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4656 KB) | HTML iconHTML

    A fully digital implementation for an RF built-in self-test (RF BIST), incorporated within a digital RF processor (DRPtrade)-based system-on-chip (SoC), is presented. The proposed mechanism serves as an on-chip built-in modulation-noise estimation-module (BIMNEM) for the testing of the 2.4 GHz local oscillator of a Bluetooth transceiver offered by Texas Instruments. This SoC, realized in a standar... View full abstract»

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  • Efficient Procedures for Analyzing Large-Scale RF Circuits

    Publication Year: 2006, Page(s):63 - 66
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (281 KB) | HTML iconHTML

    The majority of CAD tools have limited modes of the sensitivity analysis: PSPICE only contains a static mode and SPECTRE includes frequency domain and static modes. However, many RF systems use symmetrical structures for enhancing the properties of the circuits. For such systems, the static sensitivities are zero in principle and therefore the time domain sensitivity analysis must be used. In the ... View full abstract»

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  • Feedforward Interference Cancellation in Narrow-Band Receivers

    Publication Year: 2006, Page(s):67 - 70
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (114 KB) | HTML iconHTML

    Design considerations related to feedforward interference cancellation in a narrow-band receiver are discussed. A design is presented that distributes the noise and linearity requirements across two parallel receiver branches. Simulation results from a 1GHz front-end designed in a UMC-0.13mum CMOS process are presented View full abstract»

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  • Analog-to-Information Conversion via Random Demodulation

    Publication Year: 2006, Page(s):71 - 74
    Cited by:  Papers (130)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (227 KB) | HTML iconHTML

    Many problems in radar and communication signal processing involve radio frequency (RF) signals of very high bandwidth. This presents a serious challenge to systems that might attempt to use a high-rate analog-to-digital converter (ADC) to sample these signals, as prescribed by the Shannon/Nyquist sampling theorem. In these situations, however, the information level of the signal is often far lowe... View full abstract»

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  • A Fixed-Point Implementation for QR Decomposition

    Publication Year: 2006, Page(s):75 - 78
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (135 KB) | HTML iconHTML

    Matrix triangularization and orthogonalization are prerequisites to solving least square problems and find applications in a wide variety of communication systems and signal processing applications such as MIMO systems and matrix inversion. QR decomposition using modified Gram-Schmidt (MGS) orthogonalization is one of the numerically stable techniques used in this regard. This paper presents a fix... View full abstract»

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  • Design Methodology of On-Chip Power Distribution Network

    Publication Year: 2006, Page(s):79 - 82
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4237 KB) | HTML iconHTML

    The effect of the capacitors in the power distribution network (PDN) was reviewed based on electromagnetic theory. It was clarified that the capacitors used in the PDN are not suitable for high-frequency decoupling or for lowering the impedance. Based on this result, a novel design methodology of an on-chip PDN is proposed in this paper. The low-impedance lossy line (LILL) technology is used as th... View full abstract»

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  • Phase Noise Reduction in High Speed Frequency Divider

    Publication Year: 2006, Page(s):83 - 86
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4119 KB) | HTML iconHTML

    Maximum operating frequency, phase noise characteristics close to output carrier frequency and power consumption during operation are major parameters of a frequency divider. Since these parameters are interrelated, design optimization involves tradeoffs among them. A new differential D-latch based topology for a low phase noise frequency divider for cellular transceivers is presented. An optimiza... View full abstract»

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