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2006 IEEE International High Level Design Validation and Test Workshop

Date 8-10 Nov. 2006

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  • Eleventh Annual IEEE International High-Level Design Validation and Test Workshop

    Publication Year: 2006, Page(s): i
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (281 KB)

    The following topics are dealt with: high-level design validation; test specification; inductive logic programming; cell-based genetic algorithm; formal verification in modern chip design; and program slicing View full abstract»

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  • Copyright page

    Publication Year: 2006, Page(s): ii
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  • Chairs' welcome message

    Publication Year: 2006, Page(s): iii
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  • Committees

    Publication Year: 2006, Page(s): iv
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  • Table of contents

    Publication Year: 2006, Page(s):v - viii
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  • Session 1: Test Case Generation I

    Publication Year: 2006, Page(s): 9
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  • DVGen: Increasing Coverage by Automatically Combining Test Specifications

    Publication Year: 2006, Page(s):3 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9424 KB) | HTML iconHTML

    DVGen is a novel microprocessor test generator that allows the verification engineer to focus only on capturing test intent via minimally constrained test specifications. DVGen combines test specifications to generate tests that preserve the intent of each specification while causing the concurrent occurrence of interesting events from each specification. DVGen is very effective at uncovering mult... View full abstract»

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  • Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming

    Publication Year: 2006, Page(s):11 - 18
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9986 KB) | HTML iconHTML

    Functional verification is a complex and time-consuming task in the design process. Recently, various approaches have been developed to improve verification efficiency, including advanced coverage analysis techniques, coverage-driven verification methodologies and coverage-directed stimulus generation techniques. One remaining challenge is to fully automate functional coverage closure. This paper ... View full abstract»

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  • Session 2: Special Session I

    Publication Year: 2006, Page(s): 35
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  • Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm

    Publication Year: 2006, Page(s):19 - 26
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9191 KB) | HTML iconHTML

    Functional verification is a major challenge in the hardware design development cycle. Defining the appropriate coverage points that capture the design's functionalities is a non-trivial problem. However, the real bottleneck remains in generating the suitable testbenches that activate those coverage points adequately. In this paper, we propose an approach to enhance the coverage rate of multiple c... View full abstract»

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  • Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis

    Publication Year: 2006, Page(s):29 - 36
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5372 KB) | HTML iconHTML

    The applicability of disjunctive transition relation decompositions in the context of symbolic model checking is researched. An algorithm that generates such decompositions is proposed and evaluated on the VIS benchmarks. The obtained decompositions are well-balanced and the algorithm compares well with IWLS'95 View full abstract»

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  • Trends in Test: Challenges and Techniques

    Publication Year: 2006, Page(s): 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    Summary form only given. Ever increasing design sizes and the need for more sophisticated fault models at smaller process geometries require the use of compression technology to reduce the size of the ATPG pattern set. Otherwise those don't fit on the automated test equipment. Compression is becoming the norm on the most advanced chips and is the enabling technology for true at speed testing of ve... View full abstract»

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  • Session 3: Testing and Design for Testability

    Publication Year: 2006, Page(s): 47
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  • Formal Verifications in Modern Chip Designs

    Publication Year: 2006, Page(s): 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, design-constraint management, and low-power design verifications. In addition, we examine modern and eme... View full abstract»

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  • DFT and Probabilistic Testability Analysis at RTL

    Publication Year: 2006, Page(s):41 - 47
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8443 KB) | HTML iconHTML

    This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using three different approaches, an exact one, an approximated one that ignores the correlation between state variables and a third that only takes into account correlations within pre-defined groups that are formed based on an origi... View full abstract»

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  • Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)

    Publication Year: 2006, Page(s):48 - 54
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7355 KB) | HTML iconHTML

    A testable implementation of bit parallel multiplier over the finite field GF(2m) is proposed. A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2m) multiplier circuit, is also presented. Test set can be determined readily from the corresponding algebraic forms without running an ATPG tool. The test complexity is low... View full abstract»

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  • Session 4: Assertions and Transactions

    Publication Year: 2006, Page(s): 67
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  • Error Detection Using Model Checking vs. Simulation

    Publication Year: 2006, Page(s):55 - 58
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4390 KB) | HTML iconHTML

    Design simulation and model checking are two alternative and complementary techniques for verifying hardware designs. This paper presents a comparison between the two techniques based on detection of design errors, performance, and memory use. We perform error detection experiments using model checking and simulation to detect errors injected into a verification benchmark suite. The results allow ... View full abstract»

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  • Assertion-based Verification of Behavioral Descriptions with Non-linear Solver

    Publication Year: 2006, Page(s):61 - 68
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8145 KB) | HTML iconHTML

    Verification has become the major bottleneck of the design process. According to the latest report of the International Technology Roadmap for Semiconductors, the challenge is to develop new design-for-verifiability techniques and verification methods for higher levels of abstraction. Several design-for-verifiability methodologies (DFV) have been proposed and assertion-based verification (ABV) is ... View full abstract»

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  • Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties

    Publication Year: 2006, Page(s):69 - 76
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (10096 KB) | HTML iconHTML

    Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertion to be represented by a single automaton, hence allowing optimizations w... View full abstract»

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  • Specification Language for Transaction Level Assertions

    Publication Year: 2006, Page(s):77 - 84
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8912 KB) | HTML iconHTML

    Transaction level (TL) modeling is the basis of the so called electronic system level that allows development of systems on chip at a quicker pace than with classical RTL approaches. Starting from the specification phase of the product development cycle, TL modeling enables easy architecture exploration and early software co-development. In contrast to RTL, TL models (TLM) are more abstract and do... View full abstract»

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  • Session 5: Test Case Generation II

    Publication Year: 2006, Page(s): 101
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  • On the Automatic Transactor Generation for TLM-based Design Flows

    Publication Year: 2006, Page(s):85 - 92
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8951 KB) | HTML iconHTML

    Transaction level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems design and verification. It allows designers to focus on the functionalities of the design, while abstracting away implementation details that are added at lower abstraction levels. A TLM-based design flow can afford several advantages, such as, TLM-RTL mixed si... View full abstract»

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  • Addressing Test Generation Challenges for Configurable Processor Verification

    Publication Year: 2006, Page(s):95 - 101
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8259 KB) | HTML iconHTML

    Having only recently entered the mainstream, configurable processor technology already provides practical automated hardware design. In this paper, we address the challenges of verifying these software-constructed hardware artifacts and show that sophisticated automation is mandatory. We describe how a model-based test generation technology was integrated into the verification flow of a configurab... View full abstract»

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  • DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms

    Publication Year: 2006, Page(s):102 - 110
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8586 KB) | HTML iconHTML

    This paper presents a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs and increasing the need for such technology. DeepTrans is a package that extends existing test generators with address translation testing c... View full abstract»

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