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High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International

Date 8-10 Nov. 2006

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Displaying Results 1 - 25 of 48
  • Eleventh Annual IEEE International High-Level Design Validation and Test Workshop

    Page(s): i
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB)  

    The following topics are dealt with: high-level design validation; test specification; inductive logic programming; cell-based genetic algorithm; formal verification in modern chip design; and program slicing View full abstract»

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  • Copyright page

    Page(s): ii
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    Freely Available from IEEE
  • Chairs' welcome message

    Page(s): iii
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    Freely Available from IEEE
  • Committees

    Page(s): iv
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    Freely Available from IEEE
  • Table of contents

    Page(s): v - viii
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    Freely Available from IEEE
  • Session 1: Test Case Generation I

    Page(s): 9
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    Freely Available from IEEE
  • DVGen: Increasing Coverage by Automatically Combining Test Specifications

    Page(s): 3 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9424 KB) |  | HTML iconHTML  

    DVGen is a novel microprocessor test generator that allows the verification engineer to focus only on capturing test intent via minimally constrained test specifications. DVGen combines test specifications to generate tests that preserve the intent of each specification while causing the concurrent occurrence of interesting events from each specification. DVGen is very effective at uncovering multi-dimensional corner case bugs, which have historically been the bane of complex designs View full abstract»

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  • Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming

    Page(s): 11 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9986 KB) |  | HTML iconHTML  

    Functional verification is a complex and time-consuming task in the design process. Recently, various approaches have been developed to improve verification efficiency, including advanced coverage analysis techniques, coverage-driven verification methodologies and coverage-directed stimulus generation techniques. One remaining challenge is to fully automate functional coverage closure. This paper presents a novel approach for coverage-directed stimulus generation based on inductive learning from examples. Test sequences and their related coverage are examined to induce general rules which describe the characteristics of these tests. Coverage closure can be automated by applying the rule learning to clusters similar to the target coverage hole and combining the resulting rules to obtain directives for test generation. The validity of the approach is demonstrated on a pilot case study View full abstract»

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  • Session 2: Special Session I

    Page(s): 35
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    Freely Available from IEEE
  • Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm

    Page(s): 19 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9191 KB) |  | HTML iconHTML  

    Functional verification is a major challenge in the hardware design development cycle. Defining the appropriate coverage points that capture the design's functionalities is a non-trivial problem. However, the real bottleneck remains in generating the suitable testbenches that activate those coverage points adequately. In this paper, we propose an approach to enhance the coverage rate of multiple coverage points through the automatic generation of appropriate test patterns. We employ a directed random simulation, where directives are continuously updated until achieving acceptable coverage rates for all coverage points. We propose to model the solution of the test generation problem as sequences of directives or cells, each of them with specific width, height and distribution. Our approach is based on a genetic algorithm, which automatically optimizes the widths, heights and distributions of these cells over the whole input domain with the aim of enhancing the effectiveness of test generation. We illustrate the efficiency of our approach on a set of designs modeled in SystemC View full abstract»

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  • Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis

    Page(s): 29 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5372 KB) |  | HTML iconHTML  

    The applicability of disjunctive transition relation decompositions in the context of symbolic model checking is researched. An algorithm that generates such decompositions is proposed and evaluated on the VIS benchmarks. The obtained decompositions are well-balanced and the algorithm compares well with IWLS'95 View full abstract»

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  • Trends in Test: Challenges and Techniques

    Page(s): 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    Summary form only given. Ever increasing design sizes and the need for more sophisticated fault models at smaller process geometries require the use of compression technology to reduce the size of the ATPG pattern set. Otherwise those don't fit on the automated test equipment. Compression is becoming the norm on the most advanced chips and is the enabling technology for true at speed testing of very large deep submicron designs. In this talk, the author reviews challenges and techniques for high quality at speed test at 90nm and below View full abstract»

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  • Session 3: Testing and Design for Testability

    Page(s): 47
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    Freely Available from IEEE
  • Formal Verifications in Modern Chip Designs

    Page(s): 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, design-constraint management, and low-power design verifications. In addition, we examine modern and emerging design styles and techniques, and requirements on formal technologies to meet the new verification challenges View full abstract»

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  • DFT and Probabilistic Testability Analysis at RTL

    Page(s): 41 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8443 KB) |  | HTML iconHTML  

    This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using three different approaches, an exact one, an approximated one that ignores the correlation between state variables and a third that only takes into account correlations within pre-defined groups that are formed based on an originally proposed heuristic that uses RTL information. These controllability analysis methods are evaluated using simulation based controllability as a reference. Two observability metrics are originally defined: event observability and LSA observability. The proposed testability analysis methods were implemented in a tool that takes as input a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability. A methodology for partial-scan and TPI optimization is proposed. The methodology is based on the testability metrics and on a "DFT dictionary". The proposed heuristic and methodology are evaluated using the ITC99 benchmark circuits View full abstract»

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  • Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)

    Page(s): 48 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7355 KB) |  | HTML iconHTML  

    A testable implementation of bit parallel multiplier over the finite field GF(2m) is proposed. A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2m) multiplier circuit, is also presented. Test set can be determined readily from the corresponding algebraic forms without running an ATPG tool. The test complexity is lower than ATPG generated or algorithmic test set. The test set provides 100 percent single stuck-at fault coverage. The gate counts of the proposed testable multiplier as a function of degree m has been analyzed. The testable circuit realization requires only two extra inputs for controllability and some additional EX ns and need field testing, built-in self-test (BIST) circuit may be used to generate test pattern internally for detecting faults in the multiplier circuits View full abstract»

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  • Session 4: Assertions and Transactions

    Page(s): 67
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    Freely Available from IEEE
  • Error Detection Using Model Checking vs. Simulation

    Page(s): 55 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4390 KB) |  | HTML iconHTML  

    Design simulation and model checking are two alternative and complementary techniques for verifying hardware designs. This paper presents a comparison between the two techniques based on detection of design errors, performance, and memory use. We perform error detection experiments using model checking and simulation to detect errors injected into a verification benchmark suite. The results allow a quantitative comparison of simulation and model checking which can be used to understand weaknesses of both approaches View full abstract»

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  • Assertion-based Verification of Behavioral Descriptions with Non-linear Solver

    Page(s): 61 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8145 KB) |  | HTML iconHTML  

    Verification has become the major bottleneck of the design process. According to the latest report of the International Technology Roadmap for Semiconductors, the challenge is to develop new design-for-verifiability techniques and verification methods for higher levels of abstraction. Several design-for-verifiability methodologies (DFV) have been proposed and assertion-based verification (ABV) is one of the most promising. In order to automatically verify assertions at the higher abstraction levels, it is necessary to improve the performances and capabilities of current constraint solvers. This paper presents a new technique based on non-linear solvers that automatically checks assertions in behavioral descriptions of hardware systems. These descriptions are modeled with a set of integer polynomial inequalities. These techniques have been verified with several control dominated modules of an MPEG decoder and with data dominated designs, such as Viterbi decoders or vocoder digital filters View full abstract»

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  • Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties

    Page(s): 69 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (10096 KB) |  | HTML iconHTML  

    Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertion to be represented by a single automaton, hence allowing optimizations which can not be done in a modular approach where sub-circuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is developed and applied for all other operators. We show that the generated checkers are resource-efficient for use in hardware emulation, simulation acceleration and silicon debug View full abstract»

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  • Specification Language for Transaction Level Assertions

    Page(s): 77 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8912 KB) |  | HTML iconHTML  

    Transaction level (TL) modeling is the basis of the so called electronic system level that allows development of systems on chip at a quicker pace than with classical RTL approaches. Starting from the specification phase of the product development cycle, TL modeling enables easy architecture exploration and early software co-development. In contrast to RTL, TL models (TLM) are more abstract and do not contain micro-architectural details for instance; the design focus is on high-level control and data flow. Since TLMs are essential at the decision process in early system development and as they can serve as golden reference models for later RTL regression, it is imperative to ensure that they implement the specification correctly. Assertion based verification (ABV) has given a good return of investment in RTL verification, decreasing debug time while preserving the design intent leveraging these benefits on the transaction level for the verification of TLMs requires the adaptation of current ABV approaches to the specific characteristics of these abstract models. In this paper we present an assertion specification language, based on formal definitions, that allows the specification of transaction level properties and their execution in simulation. We derive the language from known ABV languages and extend these by the required TL functionality, and explain how simulation traces of finite length can be checked against properties View full abstract»

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  • Session 5: Test Case Generation II

    Page(s): 101
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    Freely Available from IEEE
  • On the Automatic Transactor Generation for TLM-based Design Flows

    Page(s): 85 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8951 KB) |  | HTML iconHTML  

    Transaction level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems design and verification. It allows designers to focus on the functionalities of the design, while abstracting away implementation details that are added at lower abstraction levels. A TLM-based design flow can afford several advantages, such as, TLM-RTL mixed simulation, testbench and assertion reuse by exploiting the transactor concept. Nevertheless, transactors implementation and verification are duty of designers so far and their generation effort often overcomes the benefits of the TLM-based design adoption. In this paper a methodology is proposed to automate some parts of the transactor generation aiming at reaching their correct-by-construction implementation. The methodology relies on (i) the adoption of a TLM API standard to ensure a correct refinement degree of transactors and (ii) the extended finite state machine (EFSM) model to formally represent the communication environment through the generation process View full abstract»

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  • Addressing Test Generation Challenges for Configurable Processor Verification

    Page(s): 95 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8259 KB) |  | HTML iconHTML  

    Having only recently entered the mainstream, configurable processor technology already provides practical automated hardware design. In this paper, we address the challenges of verifying these software-constructed hardware artifacts and show that sophisticated automation is mandatory. We describe how a model-based test generation technology was integrated into the verification flow of a configurable processor design. We report on experiments with two complex verification tasks. In both experiments, the model-based technology has achieved much higher coverage than standard verification tools and required considerably fewer engineering resources. We conclude that processor-oriented test generation technology addresses well the challenges of verifying automated hardware design View full abstract»

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  • DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms

    Page(s): 102 - 110
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8586 KB) |  | HTML iconHTML  

    This paper presents a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs and increasing the need for such technology. DeepTrans is a package that extends existing test generators with address translation testing capabilities. It uses a declarative modeling language that includes constructs for describing the address translation process, commonly used translation resources, and architecture rules related to translation. The address translation model is converted to a constraint satisfaction problem that is solved simultaneously with the problem formulated by the generator. DeepTrans is currently used by two different IBM test generators View full abstract»

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