[1992] Proceedings 29th ACM/IEEE Design Automation Conference

8-12 June 1992

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  • Proceedings. 29th ACM/IEEE Design Automation Conference (Cat. No.92CH3144-3)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (14 KB)
    Freely Available from IEEE
  • Exact evaluation of diagnostic test resolution

    Publication Year: 1992, Page(s):347 - 352
    Cited by:  Papers (33)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The authors introduce a new measure of the diagnostic resolution of a test set: the sizes of all equivalence classes in the circuit under the test set. This measure is a better indicator of the diagnostic capabilities of a test set than single-value metrics based on undistinguished pairs of faults or completely distinguished faults. A symbolic algorithm for computing equivalence class sizes has be... View full abstract»

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  • Algorithms for current monitor based diagnosis of bridging and leakage faults

    Publication Year: 1992, Page(s):353 - 356
    Cited by:  Papers (23)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Current monitor based diagnosis algorithms for bridging and leakage faults for combinational and sequential circuits are described. Experimental evaluation results of these algorithms are represented. The algorithms do not use fault dictionaries. A set of ordered-pairs of sets (SOPS) is used to represent all two line bridging faults. If m is the size of the circuit then SOPS uses O View full abstract»

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  • Recurrence equations and the optimization of synchronous logic circuits

    Publication Year: 1992, Page(s):556 - 561
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The authors present a formulation for the problem of optimizing synchronous logic across register boundaries. They describe the degrees of freedom that are the don't-care conditions of an embedded subnetwork by means of sets of execution traces, described implicitly by synchronous recurrence equations. The optimization problem reduces to that of finding minimum-cost solutions to such equations. An... View full abstract»

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  • A novel approach to delay-fault diagnosis

    Publication Year: 1992, Page(s):357 - 360
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault... View full abstract»

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  • Finite state machine synthesis with fault tolerant test function

    Publication Year: 1992, Page(s):562 - 567
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The authors propose a new method of synthesizing programmable logic array (PLA)-based finite-state machines with fault tolerant test machines. The procedure allows arbitrary state encoding. This can be exploited to achieve other objectives like minimizing the area of the PLA. Also, they do not assume an explicit reset state, and test generation does not require traversal of state transition progra... View full abstract»

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  • Acquiring and maintaining state-of-the-art DA systems

    Publication Year: 1992, Page(s):387 - 392
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The authors describe ways to successfully acquire and maintain a state-of-the-art design automation (DA) environment. Information is presented on strategies for evaluating DA technologies, assessing and justifying their acquisition, negotiating their purchase, and resolving postsales issues with vendors. A practical strategy for managing and operating a working DA environment is outlined. The stra... View full abstract»

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  • TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections

    Publication Year: 1992, Page(s):361 - 367
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    TEMPT is a technology mapping algorithm aimed at exploring field-programmable gate array (FPGA) architectures with hard-wired connections. TEMPT maps a network of basic blocks to a netlist of hard-wired logic blocks (HLBs), in which each HLB consists of several basic hard-wire blocks connected in an arbitrary tree topology, and optimizes either speed or area. TEMPT is as effective as the Xilinx 40... View full abstract»

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  • Zero skew clock net routing

    Publication Year: 1992, Page(s):518 - 523
    Cited by:  Papers (86)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The authors present an algorithm, called the zero skew segment tree method (ZSTM), for the clock net routing problem. To eliminate the lock skew and minimize the total wire length, ZSTM recursively partitions the sink nodes into two subsets which have equal loadings and minimum sum of diameters, and then constructs a zero skew segment tree according to the partitioning result. The final layout of ... View full abstract»

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  • Test-set preserving logic transformations

    Publication Year: 1992, Page(s):454 - 458
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Logic transformations that preserve minimal or complete test sets of a combinational circuit are examined. Some basic transformation types are rigorously defined and characterized with respect to test-set preservation. The authors apply the transformations to adder design and show that any complete test set for a two-level adder is preserved on transformation to ripple-carry and carry-lookahead de... View full abstract»

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  • Solving the state assignment problem for signal transition graphs

    Publication Year: 1992, Page(s):568 - 572
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The authors propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit. They first solve the STG state assignment problem by minimizing the number of states in the corresponding finite-state machine (FSM) and by using a critical race-free state assignment technique. State signal transitions may be added t... View full abstract»

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  • A new hierarchical layout compactor using simplified graph models

    Publication Year: 1992, Page(s):323 - 326
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A new hierarchy-preserving hierarchical compactor which can be used with either 1-D or 2-D leafcell compaction techniques has been developed. The compactor is applicable to hierarchical layouts which consist of a number of arrays of identical cells. The hierarchy is maintained throughout the compaction process so that all the instances of a subarray of identical cells have the same shape after com... View full abstract»

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  • The role of long and short paths in circuit performance optimization

    Publication Year: 1992, Page(s):543 - 548
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The authors consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. To develop the timing of the circuit, they use a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. The bounds on the clock period can alternatively be viewed as optimization objectives. At the physica... View full abstract»

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  • Maximum current estimation in CMOS circuits

    Publication Year: 1992, Page(s):2 - 7
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    The authors propose pattern-independent, linear-time algorithms that provide tight upper bounds on maximum envelope current (MEC) waveforms. The proposed approach represents a trade-off between execution speed and tightness of these bounds. The MEC waveform is a point-wise maximum on all the possible waveforms that the circuit can draw. Experimental results on several benchmark circuits are provid... View full abstract»

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  • Analyzing cycle stealing on synchronous circuits with level-sensitive latches

    Publication Year: 1992, Page(s):393 - 398
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The authors present a new method to fully explore cycle steal opportunities in the timing analysis for level-sensitive synchronous circuit designs. The algorithm first constructs a latch graph from a timing analysis on the combinational logic, and then it analyzes cycle stealing based on overlay timing relationships among latch nodes. A breadth-first search examines all possible cycle stealing amo... View full abstract»

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  • Area and delay mapping for table-look-up based field programmable gate arrays

    Publication Year: 1992, Page(s):368 - 373
    Cited by:  Papers (20)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The authors present a new approach to technology mapping for area and delay for truth-table-based field programmable gate arrays. They view the area and delay optimizations during technology mapping as a case of clique partitioning for which an efficient heuristic was developed. Alternate decompositions were explored by using Shannon expansion. Experimental results are included that were obtained ... View full abstract»

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  • Power and ground network topology optimization for cell based VLSIs

    Publication Year: 1992, Page(s):524 - 529
    Cited by:  Papers (47)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    A new power and ground network design problem for cell-based VLSIs is discussed. In contrast to the conventional method, the network topology is optimized, or wiring resource consumption subject to electromigration and voltage drop constraints is minimized. The proposed method has been implemented. Using several examples, the validity of the problem formulation and the solution method was confirme... View full abstract»

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  • Experiments with a performance driven module generator

    Publication Year: 1992, Page(s):687 - 690
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The authors describe a performance-driven module generator (perflex) for efficient generation of fast static combinational CMOS circuit modules. A new flexible CMOS layout style provides the foundation for implementing fast circuits. Timing optimization is performed via transistor sizing, transistor reordering, and the reduction of wiring capacitance on critical paths, all of which are performed i... View full abstract»

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  • Challenges and advances in electrical interconnect analysis

    Publication Year: 1992, Page(s):460 - 465
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    The authors review key issues regarding electrical interconnect analysis (EIA) for VLSI parasitic circuits. They give a general introduction to important aspects for technologies with a variety of performances and then review some issues relating to the state of the art for high-performance chips and packages. For high-performance technologies, the state-of-the-art tools leave a lot to be desired.... View full abstract»

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  • Transformation-based high-level synthesis of fault-tolerant ASICs

    Publication Year: 1992, Page(s):662 - 665
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The authors present a transformation-based approach to the high-level synthesis of fault-tolerant application-specific ICs (ASICs) satisfying a given performance constraint but requiring less than proportional increase in hardware over their nonredundant counterparts. They propose a synthesis methodology to exploit hardware minimizing transformations. A simple set of transformations are identified... View full abstract»

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  • Time constrained allocation and assignment techniques for high throughput signal processing

    Publication Year: 1992, Page(s):124 - 127
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A technique for the allocation of complex application specific datapaths is presented. The technique is especially suited for the synthesis of application specific architectures for high-throughput signal processing applications. Such applications comprise hierarchical compositions of nested loops and condition blocks. A minimum area set of datapaths is allocated and the available cycle budget is ... View full abstract»

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  • State assignment using input/output functions

    Publication Year: 1992, Page(s):573 - 577
    Cited by:  Papers (2)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A finite state machine synthesis procedure is proposed. The aim of the synthesis procedure is to combine some state variable functions with primary inputs and primary output functions, the former requiring zero area and the latter having to be implemented. The number of next state functions that have to be implemented is thus reduced, potentially reducing the area of the synthesized circuit. Also,... View full abstract»

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  • An integrated approach to realistic worst-case design optimization of MOS analog circuits

    Publication Year: 1992, Page(s):704 - 709
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming p... View full abstract»

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  • On the circuit implementation problem [combinatorial logic circuits]

    Publication Year: 1992, Page(s):478 - 483
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The authors consider the problem of selecting an implementation of each circuit module from a cell library to satisfy overall delay and area, or delay and power requirements. Two versions of the circuit implementation problem, the basic circuit implementation problem and the general circuit implementation problem, are shown to be NP-hard. A pseudo-polynomial-time algorithm for the basic circuit im... View full abstract»

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  • Over-the-cell routers for new cell model

    Publication Year: 1992, Page(s):604 - 607
    Cited by:  Papers (22)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The authors present new over-the-cell routing techniques for the standard cell design style. They have developed both a two-layer and a three-layer router. The key feature of the routers is the use of a new cell model, in which the terminals are located in the middle of the cells in the second metal layer. This model is similar to one currently being developed for three-layer cell libraries in ind... View full abstract»

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