[1992] Proceedings 29th ACM/IEEE Design Automation Conference

8-12 June 1992

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  • Proceedings. 29th ACM/IEEE Design Automation Conference (Cat. No.92CH3144-3)

    Publication Year: 1992
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  • At-speed delay testing of synchronous sequential circuits

    Publication Year: 1992, Page(s):177 - 181
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (524 KB)

    Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonst... View full abstract»

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  • The Princeton University behavioral synthesis system

    Publication Year: 1992, Page(s):182 - 187
    Cited by:  Papers (35)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (476 KB)

    The Princeton University behavioral synthesis system (PUBSS) is a high-level synthesis system targeted to control-dominated machines. PUBSS compiles a very high-speed integrated circuit description language (VHDL) behavior model, in which the design can be described as multiple communicating processes plus registers, and generates a register-transfer implementation. The authors describe the compil... View full abstract»

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  • High-level synthesis from VHDL with exact timing constraints

    Publication Year: 1992, Page(s):188 - 193
    Cited by:  Papers (14)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (568 KB)

    The authors present a solution to the interface timing problem in high-level synthesis by requiring that the algorithmic specification must completely determine the interface timing on the basis of cycles. They explain the timing problem and discuss the solution, which is closely related to a specific subset of the very high-speed IC description language (VHDL). This approach has been integrated i... View full abstract»

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  • Synthesis from production-based specifications

    Publication Year: 1992, Page(s):194 - 199
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (588 KB)

    The authors describe a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant machine is derived from a hierarchy of sub-machine descriptions, each represented by a production. The production-based specification (PBS) consists of productions annotated with HDL action code, and forms the input to a ... View full abstract»

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  • State assignment using input/output functions

    Publication Year: 1992, Page(s):573 - 577
    Cited by:  Papers (2)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (452 KB)

    A finite state machine synthesis procedure is proposed. The aim of the synthesis procedure is to combine some state variable functions with primary inputs and primary output functions, the former requiring zero area and the latter having to be implemented. The number of next state functions that have to be implemented is thus reduced, potentially reducing the area of the synthesized circuit. Also,... View full abstract»

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  • Maximum current estimation in CMOS circuits

    Publication Year: 1992, Page(s):2 - 7
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (572 KB)

    The authors propose pattern-independent, linear-time algorithms that provide tight upper bounds on maximum envelope current (MEC) waveforms. The proposed approach represents a trade-off between execution speed and tightness of these bounds. The MEC waveform is a point-wise maximum on all the possible waveforms that the circuit can draw. Experimental results on several benchmark circuits are provid... View full abstract»

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  • Generalized moment-matching methods for transient analysis of interconnect networks

    Publication Year: 1992, Page(s):201 - 206
    Cited by:  Papers (31)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (468 KB)

    An approach is introduced which improves published moment matching methods used in transient waveform estimation of large linear networks including lossy, coupled transmission lines. The method, which selects from a general set of moment-matching approximations, ensures stability while increasing the accuracy of the transient response. The technique is useful for analysis of high-speed interconnec... View full abstract»

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  • Area and delay mapping for table-look-up based field programmable gate arrays

    Publication Year: 1992, Page(s):368 - 373
    Cited by:  Papers (20)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (452 KB)

    The authors present a new approach to technology mapping for area and delay for truth-table-based field programmable gate arrays. They view the area and delay optimizations during technology mapping as a case of clique partitioning for which an efficient heuristic was developed. Alternate decompositions were explored by using Shannon expansion. Experimental results are included that were obtained ... View full abstract»

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  • A new efficient approach to multilayer channel routing problem

    Publication Year: 1992, Page(s):579 - 584
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (508 KB)

    A very efficient multilayer channel router, the M3CR, is described. The goal of M3CR is to use an optimum number of tracks for any multilayer routing instance in the dogleg-free routing model. M3CR has a simple time complexity because it is not a maze-running-based router. The experiment demonstrated that M3CR produced an optimum number of tracks for all... View full abstract»

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  • Incremental circuit simulation using waveform relaxation

    Publication Year: 1992, Page(s):8 - 11
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (368 KB)

    Two algorithms were developed using waveform relaxation for the rapid re-simulation of circuits that have been modified slightly compared to a previous simulation run. Both local and global changes can be handled so long as the changes are relatively small. In this approach, the window sizes, step sizes, and final waveforms from a previous simulation were used to drive the incremental simulation. ... View full abstract»

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  • Multipole-accelerated 3-D capacitance extraction algorithms for structures with conformal dielectrics

    Publication Year: 1992, Page(s):710 - 715
    Cited by:  Papers (9)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (400 KB)

    The new three-dimensional capacitance calculation program FASTCAP2 is described. Like the earlier program FASTCAP, FASTCAP2 is based on a multipole-accelerated algorithm that is efficient enough to allow three-dimensional capacitance calculations to be part of an iterative design process. FASTCAP2 differs from FASTCAP in that it was able to analyze problems with multiple-dielectrics, thus extendin... View full abstract»

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  • FPGA design principles

    Publication Year: 1992, Page(s):45 - 46
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (216 KB)

    The authors describe current field programmable gate array (FPGA) technology from three perspectives: programming technology, functional block capabilities, and routing architectures. They sketch the following FPGA CAD issues: logic synthesis for FPGAs, placement and routing, and issues in the design of new FPGAs View full abstract»

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  • Optimization of primitive gate networks using multiple output two-level minimization

    Publication Year: 1992, Page(s):449 - 453
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (420 KB)

    A novel method for the optimization of a primitive gate network is presented. The author explains why a primitive gate representation may be necessary in certain situations and describes the problems associated with using two-level minimization in that case. He then describes a method for applying two-level minimization for the optimization of a primitive gate network. The approach is based on mul... View full abstract»

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  • Time constrained allocation and assignment techniques for high throughput signal processing

    Publication Year: 1992, Page(s):124 - 127
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    A technique for the allocation of complex application specific datapaths is presented. The technique is especially suited for the synthesis of application specific architectures for high-throughput signal processing applications. Such applications comprise hierarchical compositions of nested loops and condition blocks. A minimum area set of datapaths is allocated and the available cycle budget is ... View full abstract»

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  • HOPE: an efficient parallel fault simulator

    Publication Year: 1992, Page(s):336 - 340
    Cited by:  Papers (67)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (444 KB)

    The authors present an efficient sequential circuit parallel fault simulator, HOPE, which simulates 32 faults at a time. HOPE is a parallel fault simulator based on single fault propagation. It adopts the zero gate delay model. The key idea incorporated in HOPE is to screen out faults with short propagation paths, and prevent them from being simulated in parallel. The screening process drastically... View full abstract»

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  • A performance driven macro-cell placement algorithm

    Publication Year: 1992, Page(s):147 - 152
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (508 KB)

    The authors present a new performance driven macro-cell placement algorithm. Placement of modules is guided by a set of upper- and lower-bounds on the net wire lengths. A convex programming algorithm is used to compute a set of upper-bounds on the net wire lengths which will ensure that timing requirements between input and output signals are satisfied. A set of lower-bounds is also computed to co... View full abstract»

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  • Hierarchical pitchmatching compaction using minimum design

    Publication Year: 1992, Page(s):311 - 317
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (680 KB)

    A new hierarchical compactor capable of compacting and pitchmatching hierarchically defined layouts is described. The hierarchical compactor can handle most input hierarchies, including multilevel hierarchies, over the cell routing and cell rotations and reflections. The compactor simultaneously compacts the contents of all the cells of the layout hierarchy maintaining the hierarchy of the input l... View full abstract»

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  • On the stability of moment-matching approximations in asymptotic waveform evaluation

    Publication Year: 1992, Page(s):207 - 212
    Cited by:  Papers (33)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (488 KB)

    Asymptotic waveform evaluation (AWE), which is based upon moment-matching, has been demonstrated as an efficient approach for CAD circuit simulation/analysis. The authors describe an approach for overcoming the inherent instability associated with AWE and moment-matching methods as they apply to circuit analysis problems. The efficiency and accuracy of this algorithm were demonstrated in the analy... View full abstract»

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  • An efficient algorithm for microword length minimization

    Publication Year: 1992, Page(s):651 - 656
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (428 KB)

    The problem of microword length minimization is crucial to the synthesis of microprogrammed controllers in digital systems. The authors formulate the problem as a graph partitioning problem. They employ a local search approach to further reduce the microword length. The algorithm is capable of finding fast and near-optimal solutions for very large size microcodes, efficiently. The algorithm was te... View full abstract»

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  • Characterization of Boolean functions for rapid matching in EPGA technology mapping

    Publication Year: 1992, Page(s):374 - 379
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (488 KB)

    The authors introduce characteristic signatures for Boolean functions. The signatures do not exhibit sensitivity to permutations of input variables. These signatures are used to develop a method of rapidly matching subcircuits with cells in a large library. The procedure is analogous to hashing. Filters are discussed that were found to be useful in improving the matching of variables before applyi... View full abstract»

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  • An approach to symbolic timing verification

    Publication Year: 1992, Page(s):410 - 413
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (368 KB)

    Symbolic timing verification is a critical tool in the development of higher-level synthesis tools. The authors present an approach to symbolic timing verification using constraint logic programming techniques. The techniques are quite powerful in that they not only yield simple bounds on delays but also relate the delays in linear inequalities so that tradeoffs are apparent. They model circuits a... View full abstract»

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  • A multi-layer channel router with new style of over-the-cell routing

    Publication Year: 1992, Page(s):585 - 588
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (356 KB)

    The authors discuss a new style of over-the-cell routing, where a new cell structure is introduced. Terminals are located around the horizontal center line in the cell. The region between the central terminals in the upper cell row and ones in the lower cell row is regarded as an expanded channel. The proposed router processes the expanded channel between the central terminals in the upper cell ro... View full abstract»

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  • Parallel waveform relaxation of circuits with global feedback loops

    Publication Year: 1992, Page(s):12 - 15
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (312 KB)

    Feedback loops often severely degrade the performance of waveform relaxation techniques in solving large circuit analysis problems. Several new approaches have been studied to provide greater parallelism and faster convergence for such circuits. WRV256, an experimental waveform-relaxation-based parallel circuit simulator for the Victor family of distributed memory parallel machines, was used to st... View full abstract»

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  • The role of long and short paths in circuit performance optimization

    Publication Year: 1992, Page(s):543 - 548
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (488 KB)

    The authors consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. To develop the timing of the circuit, they use a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. The bounds on the clock period can alternatively be viewed as optimization objectives. At the physica... View full abstract»

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