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VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Date 6-10 Jan. 2007

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  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems - Cover

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  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems - Title

    Page(s): i - iii
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  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems - Copyright

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  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems - Table of contents

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  • Message from the General Chair

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  • Message from the Program Chairs

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  • Message from the Organizing Team

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  • Conference Committee

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  • Program Committee

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  • Technical Program Committee Members

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  • Steering Committee

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  • VLSI Design 2006 Conference Awards

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  • list-reviewer

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  • VLSI Design Conference History

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  • Embedded Systems Design Conference History

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  • P.S. Subramanian: Obituary

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  • Tutorial T1: Designing Secure SoCs

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (159 KB) |  | HTML iconHTML  

    Information security is a critical concern in a wide range of embedded computing and communications systems. Embedded systems are being used in critical applications (medical electronics, automotive systems, and avionics), where the consequence of security attacks can be severe. Several business models (e.g., distribution of multimedia content, mobile e- commerce, etc.) require an adequate level of security in the associated electronic systems in order to be viable. On the other hand, the increasing complexity and networked nature of embedded systems has led to many vulnerabilities or weaknesses that can be easily targeted for security attacks. IBM's Global Business Security Index Report (2005) projected "the aggressive spread of viruses and worms to handheld devices, cell phones, wireless networks, car and satellite systems, and other embedded computers" as a major emerging trend. If our past experience is any indication, conventional approaches to security or simple add-on security schemes are insufficient. Adequate security can be achieved in a system only if security is considered throughout the design process, including the design of the SoCs (HW and embedded SW). It is therefore imperative that SoC architects, HW designers, and embedded SW developers be aware of the security challenges and techniques to address them. This tutorial will introduce security challenges in embedded systems, identify the security requirements for SoCs that they contain, and present approaches to designing secure SoCs. Secure SoC design will be described as an attempt to bridge three "design gaps" - the assurance gap, performance gap, and battery gap. Examples from various state-of-the-art commercial SoCs will be used to illustrate the presented concepts. The tutorial will be organized into the following parts: part 1. security concerns in embedded systems and challenges in secure SoC design; part 2. efficient security processing architectures - bridging the performance/battery gaps- - ; part 3. SW attacks and SW attack-resistant architectures - bridging the assurance gap; part 4. physical & side-channel attacks, and attack-resistant circuit design - bridging the assurance gap. View full abstract»

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  • Tutorial T2: Organic Electronics: Technology, Devices, Circuits, and Applications

    Page(s): 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (153 KB) |  | HTML iconHTML  

    The field of organic semiconductor based electronics has seen significant and unprecedented progress in the past decade. Low-cost, less energy-intensive and high-throughput production, implementation on flexible and non-planar surfaces, novel applications, as well as the potential to move to more environmentally friendly electronics makes this technology particularly attractive. A wide range of applications of organic electronics are being currently explored, including displays, lighting, solar cells, printed RFID tags and disposable low-cost sensors. Work in some areas, such as organic light emitting diodes used in displays, have matured and have moved into production. Other fields, such as organic RFID tags and sensors are already in industrial development, and preliminary products are expected within the next few years. This tutorial will start with a brief background of organic semiconductors. This will be followed by four sessions, each covering an area of organic electronic application - solar cells, display and lighting, RFID tags and sensors. The physics, device, circuit and production aspects relevant to each of the application will be covered in the sessions. View full abstract»

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  • Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller

    Page(s): 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (151 KB) |  | HTML iconHTML  

    Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs. In this tutorial we present the importance of low power microprocessor/SOC design from the high level microarchitectural, RTL, gate level to transistor level design. We cover the conflicting goals of performance vs low power, routinely faced by designers today. Embedded microprocessor/SOC designs are particularly dictated by standby and max/thermal design power and battery life constraints and not performance/frequency alone. Designing with the power envelope is a standard challenge even for the high end server platforms. Performance/watt or MlPS/watt is the design metric of today that we focus on. We cover the main components of leakage power and how does the transistor design determines whether the extreme stringent battery life requirements determined by standby and average power are met. A short discussion of different process variants for various types of applications will also be discussed followed by an introduction of shadow latches and state retention techniques used by microprocessors and DSPs of today. Tradeoff between amount of state retained and the exit latency of the processor from deep sleep/standby states will be discussed. We also cover all areas of focus for low power optimization and design: active power reduction techniques, various leakage power reduction techniques, different types of power optimization techniques from clock gating, clock tree optimization, state assignment for lower power during synthesis, long channel device insertion, multi Vt designs, gate sizing and power optimization based on positive slack in timing to name a few. We also cover the various low power friendly circuit design families as well as various techniques to reduce active power like dynamic voltage scaling, thermal throttling, sleep transistor based shutdown for various blocks like the memory hierarchy. Last but not the least we cover the whol- - e suite of EDA tools geared towards low power estimation and optimization from the ESL domain to layout optimization for low power. View full abstract»

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  • Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs

    Page(s): 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    Integrated circuit technology has evolved from micro-controllers and discrete components to fully integrating a large system on a single chip (SoC). Today, verification is the most expensive component in the design cycle in term of cost and time. This cost is estimated to consume about 70% to 80% of the total design effort. The verification cost is expected to increase for SoC designs. This is mainly due to the increase in complexity and to the shrinking of the product design cycle. For example, the color TV took over 10 years to sell 1 million units, while the DVD player took just over a year. This shrinking of the design cycle is going to put more pressure on increasing designer productivity which is affected directly by the cost of verification. For these reasons, verification of complex designs is becoming a bottleneck in the process of producing integrated SoC systems. This tutorial provides an overview of emerging directions in formal verification and a discussion of new tools being developed in industry and research directions to enable automated verification of next generation systems on a chip. The tutorial will begin with a comprehensive overview of techniques for formally verifying complex designs. It will include the fundamental theory, applicability to different types of VLSI designs, as well as the performance and limitations of various approaches. The focus will be on Formal methods and will include both equivalence checking and property checking. Formal equivalence checking methods (between RTL and gate levels) incorporated into industry tools will be described, as well as new techniques for checking the equivalence between electronic system languages (such as SystemC) and RTL. The basics of property checking techniques in existing tools will be described, including the basics of model checking, and search algorithms that automatically show the correctness/violation of a property. Limitation and benefits of both SATisfiability and automatic test patt- - ern generation (ATPG) based bounded model property checking (BMC) will be described. In order to deal with complexity, powerful model abstractions which can be automatically generated from static analysis of the RTL descriptions will be introduced. These include functional partitioning, static slicing and antecedent conditional slicing. These techniques can be used with existing tools to reduce their CPU and memory requirements while producing exactly the same results. This would be of particular interest to verification engineers and designers View full abstract»

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  • Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting

    Page(s): 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    Increased complexities of hardware designs have made exhaustive simulation of designs near impossible - thereby creating a need for some complementary verification technique. This has generated a renewed interest in use of formal analysis on industrial hardware designs. Formal analysis of hardware design involves use of mathematical techniques to prove that the design implementation confirms to the specification. The specification is a set of properties which should hold on the design under verification. Advances in formal analysis techniques with more sophisticated heuristics, have made them usable on big blocks of hardware. In this tutorial, we begin by giving a brief theoretical introduction to various methods applied in formal hardware verification, and then discuss various automated and manual techniques to handle the state explosion problem. Application of formal analysis techniques on appropriate designs and in a methodical way is key to successful verification. In this tutorial we elaborate on how one can effectively plan for formal verification, and successfully close verification. We illustrate these techniques using several case studies. Finally we present the future directions for commercial tools in this domain View full abstract»

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  • Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends

    Page(s): 8
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    The increasing complexity of systems-on-chip (SoCs) has led to the critical "design productivity gap" problem. Several strategies are being employed to cope with this problem, including an IP-based design flow, as well as platform-based designs for application domains. These approaches have critically increased the amount of on-chip communication. Since on-chip communication architectures have a significant impact on system performance, power dissipation and time-to-market, system designers, as well as the research community have focused on the issue of exploring, evaluating, and designing SoC communication architectures to meet the targeted design goals. On the other hand, aggressive scaling of VLSI technology has resulted in nanoscale effects that adversely affect interconnect performance, reliability, power dissipation, and predictability; new approaches to on-chip communication architectures (e.g., networks-on-chip) need to be devised in order to overcome these effects. The tutorial is structured into four parts, covering: i) scaling trends in nanometer interconnects and related methodology challenges; ii) architectural modeling and analysis of communication traffic and synthesis of current on-chip bus-based communication architectures iii) high-performance bus protocols and topologies, including design examples; and iv) emerging network-on-chip (NoC) paradigms for next generation designs. The tutorial begins by highlighting the key emerging issues in the domain of interconnect modeling and analysis. The implications of various nanoscale effects on VLSI interconnect performance, reliability, power dissipation and parasitic extraction are also presented. Promising new technologies including 3-D ICs and carbon nanotube (CNT) interconnects are outlined which have the potential to meet these interconnect challenges in the nanometer era. The second part of the tutorial will cover modeling abstractions suitable for communication centric designs, analysis techniques fo- - r estimating bus communication traffic, and synthesis of current protocols and standards such as OCP-IP, VSIA, and AMBA. The third part of the tutorial will cover the use of advanced architectural concepts in bus-based communication architecture design, and will include design examples from the industry. Finally, the last part of the tutorial will introduce the basic concepts on networks-on-chip and the challenges involved in the deployment of this on-chip communication paradigm. View full abstract»

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  • Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations

    Page(s): 9
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    The lack of process uniformity in the semiconductor manufacturing has caused variability to become the primary cause of concern for nanometer scale CMOS design. The variations are caused by either global effects such as mask imperfections and lens aberration, or local effects such as layout pattern variations. These variations result in a significant amount of spread in the performance as well as leakage of the manufactured circuits. The effect of variations on circuit leakage current is much more pronounced compared to their effect on the delay. The variations can cause up to 30% variations in the circuit delay and up to 20X variations in the leakage current. Due to this, a large number of chips with significantly large leakage have to be discarded, thus resulting in a considerable yield loss. The microelectronics industry is now facing one of the most important and difficult challenges - the loss of predictability in the functional correctness and performance of nanometer scale integrated circuits. For technology to continue to advance along Moore's curve, it has become imperative to develop techniques to both predict and to optimize the performance of ICs in the presence of process variations. The proposed full day tutorial will be a comprehensive look at the state-of-art techniques for (1) accurately predicting the performance and power in the presence of both inter-die and intra-die process variations, accounting for spatial correlations, and (2) optimizing the power and/or performance in the presence of process variations. The tutorial will cover four main topics: 1. Introduction to process variations: sources and their impact 2. Statistical models for gates and interconnect 3. Statistical static timing analysis and total leakage analysis 4. Performance and power optimization in the presence of process variations. View full abstract»

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  • Tutorial T7A: Advanced IC Packaging

    Page(s): 10
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    This course will address advanced packaging and assembly technologies. Demands for increased miniaturization and performance of electronic systems have driven traditional IC packaging technologies to higher levels of sophistication and miniaturization. The different styles of IC packages and their evolution will be discussed, from through-hole to surface mount, from leaded to leadless packages and from 2D to 3D packaging. Novel technology trends will be discussed, in particular wafer level packaging and 3D packaging technologies. The ultimate miniaturised package has a size equal to the die size. Such packages may be fabricated at the wafer level, before die singulation. This not only results in the smallest possible packages, but also enables cost reduction. All die on a wafer are simultaneously packaged, in contrast to the sequential traditional package flows. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer- level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. The trends for these different 3D-flavours will be discussed in more detail. View full abstract»

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  • Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP Methodology

    Page(s): 11
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    Radio frequency (RF) involves complexities in the circuit design. Non-linearity issues in active as well as passive circuit designs and issues such as parasitic couplings and radiation effects introduce challenges in the RF circuit designs. Besides these, engineers face challenges, such as reduction in design cycle, overall development cost, and the time to market. To address these challenges, RF designs require extensive analysis and simulations techniques, as well as special measurement techniques. Traditionally, at the system level, separate groups design ICs and packages. However, cost, time-to-market issues, and ever-growing package complexity in the nanometer design space demand close collaboration between design groups. System level integration with SiP requires design flows and methodologies that bridge the gap between IC design and package design. An RF SiP is a complete functional system or sub system that includes multiple ICs from different or same process technology, and embedded passives connected using a complex RF structure. This system or sub system can either be packaged as an IC and mounted or integrated into a PCB. This tutorial will first introduce the basic understanding and challenges in RF system designs. This will be followed by the discussion on the analysis, simulation and measurement techniques used for RF designs. Finally, the tutorial would talk about the RF SiP flow and the design methodology. An RF SiP design example will be used to discuss various aspects of SiP, interfaces between IC layout and SiP layout, embedded components, interconnects, constraints, SiP level routing, design rule checks and RF SiP level simulation. In the next generation nanometer designs, the RF SiP design flow and methodology will be critical to meet the overall design requirements View full abstract»

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