By Topic

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date 7-10 Sept. 1992

Filter Results

Displaying Results 1 - 25 of 122
  • EURO-DAC '92. European Design Automation Conference, EURO-VHDL '92 (Cat. No.92CH3126-0)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (20 KB)
    Freely Available from IEEE
  • Information modelling of folded and unfolded design

    Publication Year: 1992, Page(s):459 - 464
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    An information model for a folded design description which corresponds to electronic design interchange format (EDIF) version 2.0.0, using the language Express, is presented. It is shown that it can be easily extended to a model for an unfolded description. A method to compute the actual values for occurrences of views, nets, and ports, is given, which is based on the back-annotation facilities of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On modeling integrated design environments

    Publication Year: 1992, Page(s):452 - 458
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The authors describe an approach towards modeling the heterogeneous aspects of design environments which is based on a paradigm of separation and integration, yielding an adequate, well structured, non-redundant, and integrated design model for generic design environments. The design model consists of five partial models: (1) design flow model; (2) design tool model; (3) design structure model; (4... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Semantics and synthesis of signals in behavioral VHDL

    Publication Year: 1992, Page(s):616 - 621
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Signals are a fundamental part of VHSIC hardware description language (VHDL) behavioral descriptions. Synthesis tools often inadequately address synthesis of global signals. The research presented eases the restrictions placed by existing synthesis systems on the VHDL shows that can be used to specify designs. In order to obtain functionally equivalent hardware from VHDL descriptions, it is essent... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Asynchronous state machine synthesis using data driven clocks

    Publication Year: 1992, Page(s):9 - 14
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The author presents a systematic approach to the design of asynchronous state machines with minimum state variables and arbitrary state encoding. Multiple input changes are allowed. Simple latches in master-slave configuration are used as memory elements rendering the method suitable for implementation in SSI or VLSI. This approach avoids the extra delay elements often necessary in self-clocked ci... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of delay insensitive circuits using multi-ring structures

    Publication Year: 1992, Page(s):15 - 20
    Cited by:  Papers (24)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is bas... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The design cube-a model for VHDL designflow representation

    Publication Year: 1992, Page(s):752 - 757
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Hardware design under the use of the VHSIC hardware description language (VHDL) has to consider three independent property scales that influence the design process from an abstract level to gate level, namely, the design view, the timing aspect, and the value representation. The well-known Y-chart model is not suitable to describe these property scales in a satisfactory way. A new model for the de... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SEESIM-a fast synchronous sequential circuit fault simulator with single event equivalence

    Publication Year: 1992, Page(s):446 - 449
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The authors present a sequential circuit fault simulator of `single event equivalent', which combines the advantages of several techniques: fanout-free region, critical path tracing, and the dominator, techniques which were previously only applicable to combinational fault simulation. The simulator requires the minimal amount of memory, and its speed is superior to that of a state-of-the-art concu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient constrained encoding for VLSI sequential logic synthesis

    Publication Year: 1992, Page(s):266 - 271
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A fast heuristic algorithm called ENCORE is proposed for the dichotomy-based constrained encoding problem. Its implementation has been tested on MCNC synchronous sequential logic benchmarks. For the case of complete encoding, ENCORE generates the same or shorter encoding lengths than the programs KISS, NOVA and DIET, for most of the benchmarks, and uses much less CPU time. For bounded-length encod... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I and M

    Publication Year: 1992, Page(s):746 - 751
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    VHSIC hardware description language (VHDL) is compared to three other well-known hardware description languages: Verilog (from Cadence Design Systems, now public), UDL/1 (new Japanese standards,) and M (from Mentor Graphics). This comparative study parallels the fundamental concepts of these languages and highlights the different design processes and methodologies they require. VHDL is a general-p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VHDL intermediate format standardization activity: status and trends

    Publication Year: 1992, Page(s):687 - 688
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    The VIFASG is a Design Automation Standards Subcommittee (DASS) subgroup which was setup to develop a proposal for a standard intermediate format representation of VHSIC hardware description language (VHDL) models. The status of the current proposal and the remaining issues to be addressed are summarized View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Towards a standard VHDL synthesis package

    Publication Year: 1992, Page(s):706 - 712
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The VHSIC hardware description language (VHDL) Synthesis Special Interest Group (SSIG) has been working on the development of a standard VHDL package for synthesis. The efforts of the group have been divided into four different areas: logic type, representation of numeric types, specification of constraints, and special identifications. Each of these areas addresses an important part of the inform... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Linear time fault simulation algorithm using a content addressable memory

    Publication Year: 1992, Page(s):442 - 445
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type pa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions

    Publication Year: 1992, Page(s):181 - 186
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    A theory has been developed to calculate the Rademacher-Walsh transform from a reduced representation (disjoint cubes) of incompletely specified Boolean functions. The transform algorithm makes use of the properties of an array of disjoint cubes and allows the determination of the spectral coefficients in an independent way. The program for the algorithms uses advantages of C language to speed up ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the intrinsic Rent parameter and spectra-based partitioning methodologies

    Publication Year: 1992, Page(s):202 - 208
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    The complexity of circuit designs requires a top-down approach to layout synthesis. A good partitioning hierarchy, as measured by the associated Rent parameter, will correspond to an area-efficient layout. The intrinsic Rent parameter of a netlist is defined as the minimum possible Rent parameter of any partitioning hierarchy for the netlist. Experimental results show that spectra-based ratio cut ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Challenges in the analysis of VHDL

    Publication Year: 1992, Page(s):740 - 745
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    VHSIC hardware description language (VHDL) is a rich and complex formal language. Its many constructs allow for a wide description of hardware behavior. Many of the features, however, require semantics which are often difficult or expensive to properly analyze. The authors discuss several of these features, explaining why they exist, why they are hard to implement, and some strategies for easing t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wolverines: standard cell placement on a network of workstations

    Publication Year: 1992, Page(s):46 - 51
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    The typical computer-aided design environment today consists of a number of workstations connected by a high-speed local area network. The authors present a placement program that makes use of this distributed computing environment to achieve linear speedup without sacrificing the quality of the results obtained by the serial version of this program. The placement program is based on the genetic a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Combined topological and functionality based delay estimation using at layout-driven approach for high level applications

    Publication Year: 1992, Page(s):72 - 78
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    The problem of accurate delay estimation of cell-based designs, prior to any physical design tasks, is discussed. For this purpose, accurate wire-length estimates are required, since wire delays contribute significantly to the overall delay. A new technique is presented for wire-length estimation based on a combination of analytical and constructive approaches. Given these wire-length estimates an... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design for testability view on placement and routing

    Publication Year: 1992, Page(s):382 - 387
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    It is demonstrated that there is a relationship between the topology of the layout of the designed IC and the quality of testing. Based on this relationship, a testability cost function is developed for automated layout generation. The presented example indicates that a decrease in the testability objective function does correspond to an increase in the quality of testing without any penalty in te... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Routing algorithms for multi-chip modules

    Publication Year: 1992, Page(s):286 - 291
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Routing algorithms for multi-chip modules are presented. Two routing strategies, a channel routing and a grid-based routing, are discussed. The channel routing enables the designer to examine an effective routing during the placement phase. The grid-based routing calculates the net ordering with a new cost function and includes an effective rip-up and reroute procedure. The routing results of thre... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synchronous design in VHDL

    Publication Year: 1992, Page(s):680 - 681
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    VHSIC hardware description language (VHDL) is a very rich and flexible language, which offers large possibilities in the simulation domain. The current state of the art of the formal proof technique does not enable handling all these possibilities. It applies only to synchronous descriptions. The author proposes definitions of the main object semantics to be used in a synchronous description. The ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Providing a VHDL-interface for proof systems

    Publication Year: 1992, Page(s):698 - 703
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    When integrating formal methods into the design process, VHSIC hardware description language (VHDL) is unavoidable. A VHDL front end for the proof system LAMBDA is presented. The idea is to provide support for almost the full VHDL language and to generate executable ML descriptions that closely resemble the original VHDL programs. Choosing a purely functional approach has the benefit that the gene... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The exact solution of timing verification

    Publication Year: 1992, Page(s):132 - 137
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    The authors describe a new method of timing verification that searches the longest sensitizable path of a combinationorial network. The algorithm is exact in the sense that an exhaustive simulation would produce the same result. The concept of robustness in the algorithm is included. The extension of the theory for edge dependent delays has been completed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ALU synthesis from HDL descriptions to optimized multi-level logic

    Publication Year: 1992, Page(s):175 - 180
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The author presents a new tool for automatic ALU (arithmetic and logic unit) synthesis that combines the translation from an HDL to logic level and subsequent multi-level logic synthesis. The existing tools treat ALUs as random logic in that they neglect the regularity of ALUs. These tools do not achieve good results for ALUs. In contrast, the described tool partitions the ALU into blocks such as ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Experiments on the synthesis and testability of non-scan finite state machines

    Publication Year: 1992, Page(s):537 - 542
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Synthesis of testable sequential circuits has been proposed as an alternative to scan design methodologies. A number of synthesis procedures have been proposed to eliminate some or all combinational redundancies (CRs) and sequential redundancies (SRs). The latter are in principle the harder to detect and remove. Experiments on single-stuck fault testability of finite state machines (FSMs) implemen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.