By Topic

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

7-10 Sept. 1992

Filter Results

Displaying Results 1 - 25 of 122
  • Multi-kernel simulation description within VHDL

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Summary form only given. The authors describe ongoing work on multikernel description facilities within VHSIC hardware description language (VHDL) which is performed in the scope of ECIP (European CAD Integration Project). The motivation, aims, and scope of the work are outlined.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Selected aspects of component modeling

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (86 KB)

    Summary form only given. VHSIC hardware description language (VHDL) models should be defined along precise guidelines in order to guarantee their compatibility and efficiency. The author reports on the generation of component models and the quantitative analysis of models.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Towards a common RT-level subset of VHDL

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (61 KB)

    Summary form only given. The activities and goals of the European working group on synthesis requirements for VHSIC hardware description language (VHDL) are described. Some of the problems concerning the use of VHDL at RT level are reported. A formal model for hardware semantics of RT-level VHDL could rely on deterministic automata. This is important for the cooperation of synthesis and formal ver... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • EURO-DAC '92. European Design Automation Conference, EURO-VHDL '92 (Cat. No.92CH3126-0)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (20 KB)
    Freely Available from IEEE
  • Challenges for CAD in computer development in the 1990s

    Publication Year: 1992, Page(s):597 - 598
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (98 KB)

    Summary form only given. CAD tools play a key role in determining the productivity and the time-to-market of computer development. To predict future trends in CAD, the future trends of technology and computer architecture have to be considered because of its strong interaction with tools and design methodology. The current computer development methodology is summarized. The CAD tools supporting th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic partitioning for deterministic test

    Publication Year: 1992, Page(s):322 - 325
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Automatic partitioning for digital circuits is proposed. The partitions are defined by using functional testability measures and a test difficulty estimation. The software, developed with an expert system generator, is embedded in a hierarchical test generation process. The partitioning technique proposed uses difficulty test estimation corresponding to the maximal number of logical gates that can... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic module allocation in high level synthesis

    Publication Year: 1992, Page(s):328 - 333
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    A main step in high-level synthesis is data-path synthesis consisting of allocation, scheduling and assignment. The authors present an allocation algorithm designed for an environment where the allocation precedes scheduling and assignment. This algorithm selects the hardware components (in type and number) fully automatically and supports a realistic area/time tradeoff. During this allocation a d... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Heuristics for branch-and-bound global attraction

    Publication Year: 1992, Page(s):334 - 340
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    A set of heuristics designed to guide the behavior of a global branch-and-bound hardware allocator is described. An area estimation heuristic, including interconnection area, is used as a cost function to be minimized. A design space bounding heuristic allows pruning the design space in a more intelligent way than any other system. Design space search guiding heuristics are incorporated so that re... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Random current testing for CMOS logic circuits by monitoring a dynamic power supply current

    Publication Year: 1992, Page(s):480 - 485
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Assuming a stuck-at type fault, the authors discuss current testing for CMOS logic circuits where the random patterns generated by a linear feedback shift register (LFSR) are applied, and a dynamic power supply current is monitored. The LFSR is modified such that there exists a feedback from the outputs of a circuit under test to the LSFR. This modification is intended for amplifying the effect of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ANT-A test harness for the NELSIS CAD system

    Publication Year: 1992, Page(s):506 - 511
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    ANT, a test harness for validation of a suite of design tools incorporated in a framework, is described. The harness is built upon the same framework used to support the tools and tests are modeled as hierarchical CAD objects. ANT is currently being employed for regression testing of the NELSIS (VLSI) CAD framework, and is available only for internal use at the university where it is being tested View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A distributed routing system for multilayer SOG

    Publication Year: 1992, Page(s):298 - 303
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    A distributed processing system dedicated to multilayer sea-of-gates (SOG) routing is described. The system is constructed of global and detailed routers, each based on distinct rip-up and rerouting procedures, so as to be run on a computer network composed of a number of workstations. Several implementation results attained for five-year SOG are also shown to reveal the practicality of the system... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On modeling integrated design environments

    Publication Year: 1992, Page(s):452 - 458
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The authors describe an approach towards modeling the heterogeneous aspects of design environments which is based on a paradigm of separation and integration, yielding an adequate, well structured, non-redundant, and integrated design model for generic design environments. The design model consists of five partial models: (1) design flow model; (2) design tool model; (3) design structure model; (4... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A neural network based algorithm for the scheduling problem in high-level synthesis

    Publication Year: 1992, Page(s):341 - 346
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    A new scheduling approach for high-level synthesis based on a deterministic modified Hopfield model is presented. The model uses a four-dimensional neural network architecture to schedule the operations of a data flow graph (DFG), and maps them to specific functional units. Neural network-based scheduling (NNS) is achieved by formulating the scheduling problem in terms of an energy function, and b... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test generation for IDDQ testing and leakage fault detection in CMOS circuits

    Publication Year: 1992, Page(s):486 - 491
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The authors describe a two-stage method to generate test sets for quiescent power supply current, IDDQ, testing and to determine the leakage fault coverage for given test pattern sets. The method is integrated within a fault simulator. It is proved that any complete test pattern set generated for stuck-at faults detects all leakage faults caused by intra-gate shorts within a st... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compiling VHDL into a high-level synthesis design representation

    Publication Year: 1992, Page(s):604 - 609
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    An approach to the use of VHDL (VHSIC hardware description language) as an input specification to the CAMAD high-level synthesis system is presented. A synthesis-oriented compiler which takes a subset of VHDL as input and compiles it into the interal design representation of CAMAD is described. CAMAD can then be synthesized into register-transfer level design. Since CAMAD supports the design of ha... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Temporal verification of behavioral descriptions in VHDL

    Publication Year: 1992, Page(s):692 - 697
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    An approach for verifying the temporal scheduling of behavioral models of VHSIC hardware description language (VHDL) is presented. The aim is to verify that the control flow of a behavioral description satisfies its behavioral specifications described in a formalism based on reified temporal logics, and on a notion of physical activity. From this formalism, a verification procedure is established ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A generic software system for drift reliability optimization of VLSI circuits

    Publication Year: 1992, Page(s):578 - 583
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A generic software system called GOSSIPDR (generic optimization system for statistical improvement of performance) to perform DR (drift reliability) analysis and optimization is presented. This system was developed based on new DR analysis and optimization methodologies. Several useful system features and functions are described. Applications in VLSI circuit design are given, in which degradations... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Unifying tool, data and process flow management

    Publication Year: 1992, Page(s):500 - 505
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Typically, modern design management is achieved through either a data management system or a flow sequence controller. Each is highly productive in specific parts of a design process, but becomes cumbersome in others. A design management approach which is generally applicable throughout the development of a product is presented. It offers flow control and automation to manage readily definable pro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cross-fertilizing FSM verification techniques and sequential diagnosis

    Publication Year: 1992, Page(s):306 - 311
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    The authors present a technique for assessing the diagnostic power of an existing detection-oriented test pattern by means of diagnostic fault simulation and a procedure to improve it. The procedure successfully exploits enhanced symbolic finite state machine (FSM) equivalence proof algorithms. In order to resort to product machine traversal only when needed, special checks are performed to verify... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Information modelling of folded and unfolded design

    Publication Year: 1992, Page(s):459 - 464
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    An information model for a folded design description which corresponds to electronic design interchange format (EDIF) version 2.0.0, using the language Express, is presented. It is shown that it can be easily extended to a model for an unfolded description. A method to compute the actual values for occurrences of views, nets, and ports, is given, which is based on the back-annotation facilities of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up

    Publication Year: 1992, Page(s):436 - 441
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Several methods accelerating fault simulation for combinational circuits using parallel pattern evaluation are presented. All methods make use of a very efficient data structure which allows the easy recognition of special situations that can be used to avoid a lot of gate evaluations during explicit fault simulation. An implementation of the concepts shows that the resulting fault simulation algo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integration of SDL and VHDL for high-level digital design

    Publication Year: 1992, Page(s):624 - 629
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A study of Specification and Description Language (SDL) and VHSIC hardware description language (VHDL) that their semantics differ considerably in several essential areas. The languages can be used to provide descriptions of systems from different and complementary viewpoints. It is shown that these viewpoints can be usefully integrated by defining them as specific views of a more general system m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the intrinsic Rent parameter and spectra-based partitioning methodologies

    Publication Year: 1992, Page(s):202 - 208
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    The complexity of circuit designs requires a top-down approach to layout synthesis. A good partitioning hierarchy, as measured by the associated Rent parameter, will correspond to an area-efficient layout. The intrinsic Rent parameter of a netlist is defined as the minimum possible Rent parameter of any partitioning hierarchy for the netlist. Experimental results show that spectra-based ratio cut ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An optimal channel pin assignment with multiple intervals for building block layout

    Publication Year: 1992, Page(s):348 - 353
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    The authors present a linear time optimal algorithm to determine positions of the pins of nets on the top and the bottom sides of a channel, which is partitioned into several intervals. The pins are permutable within their associated intervals. The proposed algorithm is optimal in the sense that it can minimize both the density and the total wire length of the channel. Experimental results show th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of complex systems with a VHDL based methodology

    Publication Year: 1992, Page(s):658 - 663
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    The design of complex systems requires a solid methodology in order to avoid dangerous anarchy during the design phase and to increase the overall quality of the final product. The presented methodology is founded on the use of VHSIC hardware description language (VHDL) as a common modeling language. The authors discuss modeling techniques in different areas: memory devices, ASICs, μ-processors... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.