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Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

7-10 Sept. 1992

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Displaying Results 1 - 25 of 122
  • Multi-kernel simulation description within VHDL

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Summary form only given. The authors describe ongoing work on multikernel description facilities within VHSIC hardware description language (VHDL) which is performed in the scope of ECIP (European CAD Integration Project). The motivation, aims, and scope of the work are outlined.<> View full abstract»

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  • Selected aspects of component modeling

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (86 KB)

    Summary form only given. VHSIC hardware description language (VHDL) models should be defined along precise guidelines in order to guarantee their compatibility and efficiency. The author reports on the generation of component models and the quantitative analysis of models.<> View full abstract»

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  • Towards a common RT-level subset of VHDL

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (61 KB)

    Summary form only given. The activities and goals of the European working group on synthesis requirements for VHSIC hardware description language (VHDL) are described. Some of the problems concerning the use of VHDL at RT level are reported. A formal model for hardware semantics of RT-level VHDL could rely on deterministic automata. This is important for the cooperation of synthesis and formal ver... View full abstract»

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  • EURO-DAC '92. European Design Automation Conference, EURO-VHDL '92 (Cat. No.92CH3126-0)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (20 KB)
    Freely Available from IEEE
  • Challenges for CAD in computer development in the 1990s

    Publication Year: 1992, Page(s):597 - 598
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (98 KB)

    Summary form only given. CAD tools play a key role in determining the productivity and the time-to-market of computer development. To predict future trends in CAD, the future trends of technology and computer architecture have to be considered because of its strong interaction with tools and design methodology. The current computer development methodology is summarized. The CAD tools supporting th... View full abstract»

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  • On modeling integrated design environments

    Publication Year: 1992, Page(s):452 - 458
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The authors describe an approach towards modeling the heterogeneous aspects of design environments which is based on a paradigm of separation and integration, yielding an adequate, well structured, non-redundant, and integrated design model for generic design environments. The design model consists of five partial models: (1) design flow model; (2) design tool model; (3) design structure model; (4... View full abstract»

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  • A generic software system for drift reliability optimization of VLSI circuits

    Publication Year: 1992, Page(s):578 - 583
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A generic software system called GOSSIPDR (generic optimization system for statistical improvement of performance) to perform DR (drift reliability) analysis and optimization is presented. This system was developed based on new DR analysis and optimization methodologies. Several useful system features and functions are described. Applications in VLSI circuit design are given, in which degradations... View full abstract»

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  • Information modelling of folded and unfolded design

    Publication Year: 1992, Page(s):459 - 464
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    An information model for a folded design description which corresponds to electronic design interchange format (EDIF) version 2.0.0, using the language Express, is presented. It is shown that it can be easily extended to a model for an unfolded description. A method to compute the actual values for occurrences of views, nets, and ports, is given, which is based on the back-annotation facilities of... View full abstract»

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  • Combined topological and functionality based delay estimation using at layout-driven approach for high level applications

    Publication Year: 1992, Page(s):72 - 78
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    The problem of accurate delay estimation of cell-based designs, prior to any physical design tasks, is discussed. For this purpose, accurate wire-length estimates are required, since wire delays contribute significantly to the overall delay. A new technique is presented for wire-length estimation based on a combination of analytical and constructive approaches. Given these wire-length estimates an... View full abstract»

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  • Challenges in the analysis of VHDL

    Publication Year: 1992, Page(s):740 - 745
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    VHSIC hardware description language (VHDL) is a rich and complex formal language. Its many constructs allow for a wide description of hardware behavior. Many of the features, however, require semantics which are often difficult or expensive to properly analyze. The authors discuss several of these features, explaining why they exist, why they are hard to implement, and some strategies for easing t... View full abstract»

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  • GOSSIP-a generic system for statistical circuit design

    Publication Year: 1992, Page(s):572 - 577
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    A new system called GOSSIP (generic optimization system for statistical improvement of performance) is described. GOSSIP can be considered as a new framework for optimal circuit design. It has several useful features, such as flexibility of combining various solution methods, scaling algorithms, circuit analyzers, etc. Two important design methodologies implemented in GOSSIP are described, based o... View full abstract»

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  • Locating logic design errors via test generation and don't-care propagation

    Publication Year: 1992, Page(s):466 - 471
    Cited by:  Papers (25)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The author presents a new technique, the don't-care propagation method, for logic verification and design error location in a circuit. Test patterns for single stuck-line faults are used to compare the gate-level implementation of a circuit with its functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree wit... View full abstract»

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  • Correctness verification of concurrent controller specifications

    Publication Year: 1992, Page(s):80 - 85
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    An integrated design concept that focuses on the correctness of concurrent controllers is presented. This approach is based on the specification of concurrent tasks with the aid of structured flow charts. A new formal proceeding for the verification of the correct behavior is introduced. Algorithms reduce the verification process to a polynomial amount of computational effort. The method can be ap... View full abstract»

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  • Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I and M

    Publication Year: 1992, Page(s):746 - 751
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    VHSIC hardware description language (VHDL) is compared to three other well-known hardware description languages: Verilog (from Cadence Design Systems, now public), UDL/1 (new Japanese standards,) and M (from Mentor Graphics). This comparative study parallels the fundamental concepts of these languages and highlights the different design processes and methodologies they require. VHDL is a general-p... View full abstract»

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  • Chip assembly in the PLAYOUT VLSI design system

    Publication Year: 1992, Page(s):215 - 221
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    Chip assembly in PLAYOUT is designed for top-down chip planning. An example of a three-level hierarchy demonstrates the new design strategy. Three-phase chip planning and chip assembly have close interaction to guarantee an exchange of constraints between levels of the hierarchy. Chip assembly is composed of two different functions: cell synthesis, and cell assembly. For cell synthesis, standard c... View full abstract»

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  • Representing the hardware design process by a common data schema

    Publication Year: 1992, Page(s):564 - 569
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    An open, extensible, administrative data schema that is based on electronic design interchange format (EDIF) is presented. The schema closely reflects the hardware design process. Thus, it enables the realization of central design management services. The use of a common schema implemented with the help of an object management system allows the integrated tools to share the data covered by this sc... View full abstract»

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  • Semantics and synthesis of signals in behavioral VHDL

    Publication Year: 1992, Page(s):616 - 621
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Signals are a fundamental part of VHSIC hardware description language (VHDL) behavioral descriptions. Synthesis tools often inadequately address synthesis of global signals. The research presented eases the restrictions placed by existing synthesis systems on the VHDL shows that can be used to specify designs. In order to obtain functionally equivalent hardware from VHDL descriptions, it is essent... View full abstract»

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  • PERFLEX: a performance driven module generator

    Publication Year: 1992, Page(s):154 - 159
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A performance-driven approach to module generation, called PERFLEX, for static combinational CMOS logic circuits is described. The flexible layout style supports implementation of fast and reliable circuits. Improvement in circuit speed is achieved through minimization of diffusion and interconnection capacitance, transistor sizing, and transistor reordering. By integrating transistor sizing and r... View full abstract»

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  • Interest of a VHDL native environment

    Publication Year: 1992, Page(s):684 - 685
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    A VHSIC hardware description language (VHDL) native environment enables the use of VHDL in the design of accurate tools. The author reports on the Perennity constraint, portability, coding strategy, and possible improvements. A VHDL native environment example is provided View full abstract»

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  • Subtype concept of VHDL for synthesis constraints

    Publication Year: 1992, Page(s):720 - 725
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The authors propose to exploit the VHSIC hardware description language (VHDL) subtype concept for formulating ranges for design constraints which could be used as inputs for synthesis tools. The proposed method relies on interpreting the range of a VHDL constant's type as a range specification for a design constraint. Presynthesis simulation is done with an estimated value inside the specified ran... View full abstract»

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  • New design error modeling and metrics for design validation

    Publication Year: 1992, Page(s):472 - 477
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    When simulation is used for design verification, a subset of simulation input patterns is used, since exhaustive simulation is usually not practical. This produces uncertainty as to how much of the design has been verified. To provide a measure of the simulation pattern coverage based on design error modeling, a new simulation coverage metric is introduced. This measure is useful for obtaining ins... View full abstract»

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  • Design verification considering manufacturing tolerances by using worst-case distances

    Publication Year: 1992, Page(s):86 - 91
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A new method for design verification on circuit level considering the inevitable manufacturing tolerances is presented. It is based on a specific backward evaluation of performance specifications, which can be done efficiently with a sequential quadratic programming method using standard simulation tools. The specific backward evaluation yields exact worst-case parameter sets and corresponding wor... View full abstract»

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  • The design cube-a model for VHDL designflow representation

    Publication Year: 1992, Page(s):752 - 757
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Hardware design under the use of the VHSIC hardware description language (VHDL) has to consider three independent property scales that influence the design process from an abstract level to gate level, namely, the design view, the timing aspect, and the value representation. The well-known Y-chart model is not suitable to describe these property scales in a satisfactory way. A new model for the de... View full abstract»

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  • Parallel algorithms for slicing based final placement

    Publication Year: 1992, Page(s):40 - 45
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The authors present parallel algorithms for solving the final placement problem of rectangular modules assuming predefined neighborhood relations, between the modules to be placed. By enumerating all arrangements (i.e. slicing structures) of local module subsets, optimum solutions are obtained. They are combined in a global evaluation step such that the local solutions fit well into the global arr... View full abstract»

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  • Asynchronous state machine synthesis using data driven clocks

    Publication Year: 1992, Page(s):9 - 14
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The author presents a systematic approach to the design of asynchronous state machines with minimum state variables and arbitrary state encoding. Multiple input changes are allowed. Simple latches in master-slave configuration are used as memory elements rendering the method suitable for implementation in SSI or VLSI. This approach avoids the extra delay elements often necessary in self-clocked ci... View full abstract»

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