Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

7-10 Sept. 1992

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  • Multi-kernel simulation description within VHDL

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (80 KB)

    Summary form only given. The authors describe ongoing work on multikernel description facilities within VHSIC hardware description language (VHDL) which is performed in the scope of ECIP (European CAD Integration Project). The motivation, aims, and scope of the work are outlined.<> View full abstract»

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  • Selected aspects of component modeling

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (86 KB)

    Summary form only given. VHSIC hardware description language (VHDL) models should be defined along precise guidelines in order to guarantee their compatibility and efficiency. The author reports on the generation of component models and the quantitative analysis of models.<> View full abstract»

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  • Towards a common RT-level subset of VHDL

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (61 KB)

    Summary form only given. The activities and goals of the European working group on synthesis requirements for VHSIC hardware description language (VHDL) are described. Some of the problems concerning the use of VHDL at RT level are reported. A formal model for hardware semantics of RT-level VHDL could rely on deterministic automata. This is important for the cooperation of synthesis and formal ver... View full abstract»

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  • EURO-DAC '92. European Design Automation Conference, EURO-VHDL '92 (Cat. No.92CH3126-0)

    Publication Year: 1992
    Request permission for commercial reuse | |PDF file iconPDF (20 KB)
    Freely Available from IEEE
  • Challenges for CAD in computer development in the 1990s

    Publication Year: 1992, Page(s):597 - 598
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (98 KB)

    Summary form only given. CAD tools play a key role in determining the productivity and the time-to-market of computer development. To predict future trends in CAD, the future trends of technology and computer architecture have to be considered because of its strong interaction with tools and design methodology. The current computer development methodology is summarized. The CAD tools supporting th... View full abstract»

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  • An efficient methodology for symbolic compaction of analog ICs with multiple symmetry constraints

    Publication Year: 1992, Page(s):148 - 153
    Cited by:  Papers (9)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (428 KB)

    An efficient approach to the symbolic compaction of analog integrated circuits is presented. A fast graph-based algorithm performs a preliminary compaction taking into account a set of basic spacing constraints. The obtained configuration provides the starting point for a linear program, which optimizes the layout introducing multiple device and wire symmetry constraints. The efficiency and robust... View full abstract»

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  • PERFLEX: a performance driven module generator

    Publication Year: 1992, Page(s):154 - 159
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (552 KB)

    A performance-driven approach to module generation, called PERFLEX, for static combinational CMOS logic circuits is described. The flexible layout style supports implementation of fast and reliable circuits. Improvement in circuit speed is achieved through minimization of diffusion and interconnection capacitance, transistor sizing, and transistor reordering. By integrating transistor sizing and r... View full abstract»

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  • Flexible timing specification in a VHDL synthesis subset

    Publication Year: 1992, Page(s):610 - 615
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (520 KB)

    A VHSIC hardware description language (VHDL) subset for high-level synthesis allowing a flexible timing specification of the circuit interface such that the optimization potential of classical scheduling and allocation techniques can be fully used is presented. The algorithmic circuit specification can be validated by a conventional VHDL simulator if the description style follows the proposed guid... View full abstract»

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  • P.Size: a sizing aid for optimized designs

    Publication Year: 1992, Page(s):160 - 165
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (440 KB)

    Transistor sizing at layout level is necessary to improve the overall performance of integrated circuits. The authors present the definition and the validation of a sizing aid, P.Size, integrated in a flexible cell generator. Based on a local optimization defined through an explicit formulation of delays, this sizing aid can be used to optimize real data paths, under constraint, with few CPU time ... View full abstract»

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  • Design of delay insensitive circuits using multi-ring structures

    Publication Year: 1992, Page(s):15 - 20
    Cited by:  Papers (32)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (504 KB)

    The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is bas... View full abstract»

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  • Compiling VHDL into a high-level synthesis design representation

    Publication Year: 1992, Page(s):604 - 609
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (480 KB)

    An approach to the use of VHDL (VHSIC hardware description language) as an input specification to the CAMAD high-level synthesis system is presented. A synthesis-oriented compiler which takes a subset of VHDL as input and compiles it into the interal design representation of CAMAD is described. CAMAD can then be synthesized into register-transfer level design. Since CAMAD supports the design of ha... View full abstract»

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  • Routing algorithms for multi-chip modules

    Publication Year: 1992, Page(s):286 - 291
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (424 KB)

    Routing algorithms for multi-chip modules are presented. Two routing strategies, a channel routing and a grid-based routing, are discussed. The channel routing enables the designer to examine an effective routing during the placement phase. The grid-based routing calculates the net ordering with a new cost function and includes an effective rip-up and reroute procedure. The routing results of thre... View full abstract»

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  • Boolean matching in logic synthesis

    Publication Year: 1992, Page(s):168 - 174
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (608 KB)

    A new formulation for finding the existence of a Boolean match between two functions with `don't cares' is presented. An algorithm for Boolean matching is developed based on this new foundation and is used within a technology mapper as a substitute for tree matching algorithms. The new algorithm is fast and uses symmetries of the gates in the library to speed up the matching process. Local `don't ... View full abstract»

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  • Locating logic design errors via test generation and don't-care propagation

    Publication Year: 1992, Page(s):466 - 471
    Cited by:  Papers (27)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    The author presents a new technique, the don't-care propagation method, for logic verification and design error location in a circuit. Test patterns for single stuck-line faults are used to compare the gate-level implementation of a circuit with its functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree wit... View full abstract»

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  • DESB, a functional abstractor for CMOS VLSI circuits

    Publication Year: 1992, Page(s):22 - 27
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (324 KB)

    DESB is included in a set of tools for hierarchical verification of custom VLSI circuits. These tools include the layout extractor DAX, DESB, the electrical rule checker VERTEC, and the timing analyzer TAS. The functional abstractor DESB is the key point in a hierarchical verification process. A functional abstractor for CMOS VLSI circuits is presented. A gate-level descriptions is derived from a ... View full abstract»

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  • Electronic systems design-tools and methodology to meet the productivity change

    Publication Year: 1992, Page(s):599 - 600
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (136 KB)

    The author examines the technology shifts that will drive the electronic design automation (EDA) tools needed for right-first-time integrated system design. The major issues facing the design community and possible ways to improve productivity and quality are considered View full abstract»

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  • Parallel algorithms for slicing based final placement

    Publication Year: 1992, Page(s):40 - 45
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    The authors present parallel algorithms for solving the final placement problem of rectangular modules assuming predefined neighborhood relations, between the modules to be placed. By enumerating all arrangements (i.e. slicing structures) of local module subsets, optimum solutions are obtained. They are combined in a global evaluation step such that the local solutions fit well into the global arr... View full abstract»

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  • Interest of a VHDL native environment

    Publication Year: 1992, Page(s):684 - 685
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (140 KB)

    A VHSIC hardware description language (VHDL) native environment enables the use of VHDL in the design of accurate tools. The author reports on the Perennity constraint, portability, coding strategy, and possible improvements. A VHDL native environment example is provided View full abstract»

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  • An optimal channel pin assignment with multiple intervals for building block layout

    Publication Year: 1992, Page(s):348 - 353
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (416 KB)

    The authors present a linear time optimal algorithm to determine positions of the pins of nets on the top and the bottom sides of a channel, which is partitioned into several intervals. The pins are permutable within their associated intervals. The proposed algorithm is optimal in the sense that it can minimize both the density and the total wire length of the channel. Experimental results show th... View full abstract»

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  • The design cube-a model for VHDL designflow representation

    Publication Year: 1992, Page(s):752 - 757
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (400 KB)

    Hardware design under the use of the VHSIC hardware description language (VHDL) has to consider three independent property scales that influence the design process from an abstract level to gate level, namely, the design view, the timing aspect, and the value representation. The well-known Y-chart model is not suitable to describe these property scales in a satisfactory way. A new model for the de... View full abstract»

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  • A multilevel testability assistant for VLSI design

    Publication Year: 1992, Page(s):258 - 263
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (556 KB)

    The possibility of applying techniques for VLSI testability analysis at abstract design levels will considerably help in reducing system design costs. A new approach to high-level testability analysis has been introduced at different design representation levels. A testability assistant has been defined to support the VLSI designer on testability and design for testability issues. The testability ... View full abstract»

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  • A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping

    Publication Year: 1992, Page(s):230 - 235
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (540 KB)

    An approach to the decomposition of incompletely specified Boolean functions is introduced, and its application to lookup-table-based field programmable gate array (FPGA) mapping is described. Three methods are developed: fast graph coloring to perform a quasi-optimum `don't care' assignment; variable partitioning to quickly find the `best' partitions; and local transformation to transform a nonde... View full abstract»

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  • PAR-APLAC: parallel circuit analysis and optimization

    Publication Year: 1992, Page(s):584 - 589
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (420 KB)

    The authors describe a circuit simulation, analysis and optimization software which can utilize the most common parallel processing hardware, i.e. the workstation network. The parallel processing ability has been implemented using an easy-to-use but powerful methodology. The efficiency of this methodology is demonstrated in terms of both CPU and programmer time. The feasibility of converting even ... View full abstract»

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  • State machine abstraction from circuit layouts using BDDs: applications in verification and synthesis

    Publication Year: 1992, Page(s):92 - 97
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (484 KB)

    The authors discuss a formal technique for abstracting a finite state machine (FSM) from a transistor netlist, given information relating to clock signals and clo·cking methodology. The abstracted FSM is represented as a transition relation using binary decision diagrams (BDDs) and then converted into a synchronous sequential network. Both the relational and network representations are comm... View full abstract»

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  • Timing models for high-level synthesis

    Publication Year: 1992, Page(s):60 - 65
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous m... View full abstract»

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