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Innovative Architecture for Future Generation High Performance Processors and Systems, 2006. IWIA '06. International Workshop on

Date 23-25 Jan. 2006

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Displaying Results 1 - 17 of 17
  • International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems [Cover]

    Publication Year: 2006, Page(s): c1
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  • International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems-Title

    Publication Year: 2006, Page(s):i - iii
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  • International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems-Copyright

    Publication Year: 2006, Page(s): iv
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  • International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems - TOC

    Publication Year: 2006, Page(s):v - vi
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  • Message from the Editors

    Publication Year: 2006, Page(s): vii
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  • Reviewing Committee

    Publication Year: 2006, Page(s): viii
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  • A Holistic Approach to System Reliability in Blue Gene

    Publication Year: 2006, Page(s):3 - 12
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5157 KB) | HTML iconHTML

    Optimizing supercomputer performance requires a balance between objectives for processor performance, network performance, power delivery and cooling, cost and reliability. In particular, scaling a system to a large number of processors poses challenges for reliability, availability and serviceability. Given the power and thermal constraints of data centers, the BlueGene/L supercomputer has been d... View full abstract»

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  • Redundancy in Multi-core Memory-Rich Application-Specific PIM Chips

    Publication Year: 2006, Page(s):13 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    A trend of growing significance in the arena of advanced microprocessor chip design is the inclusion of multiple processor cores onto the same die with significant parts of the memory hierarchy. This is done to reduce both non-recurring design costs and power dissipation, and to get more computational capability and utilization out of the silicon. A side-effect, however, is the opportunity to leve... View full abstract»

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  • Improving Instruction Issue Bandwidth for Concurrent Error-Detecting Processors

    Publication Year: 2006, Page(s):21 - 28
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (219 KB) | HTML iconHTML

    Soft error tolerance is a hot research topic for modern microprocessors. We have been investigating soft error tolerance micro architecture, RED, which exploits time redundancy to achieve soft error tolerance without requiring prohibitive additional hardware resources. Unfortunately, our previous study unveiled that a RED-based processor suffers severe performance penalty. We guess that it comes f... View full abstract»

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  • The Speculative Prefetcher and Evaluator Processor for Pipelined Memory Hierarchies

    Publication Year: 2006, Page(s):29 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB) | HTML iconHTML

    We consider extensible processor designs in which the number of gates and the distance that a signal traverses in one clock period are, within a given technology, independent of system size. Consequently such designs scale with system size (in particular, with memory latency) as well as with technological advancement. We assume aggressive memories that are not only hierarchical in nature, but are ... View full abstract»

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  • Responsive Multithreaded Processor for Distributed Real-Time Processing

    Publication Year: 2006, Page(s):44 - 56
    Cited by:  Papers (1)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2405 KB) | HTML iconHTML

    Responsive multithreaded (RMT) processor is a processor chip that integrates almost all functions for parallel/distributed real-time systems such as robots, intelligent rooms/buildings, amusement systems, etc. Concretely, the RMT processor integrates a real-time processing core (RMT PU), a real-time communication (five sets of responsive links), computer I/O peripherals (DDR SDRAM I/Fs, DMAC, PCI-... View full abstract»

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  • A Partial Irregular-Network Routing on Faulty k-ary n-cubes

    Publication Year: 2006, Page(s):57 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB) | HTML iconHTML

    Interconnection networks have been studied to connect a number of processing elements on parallel computers. Their design increasingly includes a challenge to high fault-tolerance, as entire systems become complicated. This paper presents a partial irregular-network routing in order to provide a high fault-tolerance in k-ary n-cube networks. Since an irregular-network routing usually performs poor... View full abstract»

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  • Predictive Switching in 2-D Torus Routers

    Publication Year: 2006, Page(s):65 - 72
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB) | HTML iconHTML

    This paper proposes predictive switching in 2D torus routers to reduce the number of pipeline stages for low-latency communication. By utilizing the communication regularity in parallel applications, a dynamic predicting mechanism presets packet traversal paths inside the router before packet arrivals. Hence, we can bypass the pipeline stages of routing computation, virtual channel allocation and ... View full abstract»

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  • Hardware Support for MPI in DIMMnet-2 Network Interface

    Publication Year: 2006, Page(s):73 - 82
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (303 KB) | HTML iconHTML

    In this paper, hardware support for MPI on the DIMMnet-2 network interface plugged into a DDR DIMM slot is presented. This hardware support realize effective eager protocol and effective derived datatype communication of MPI. As a preliminary evaluation, the evaluation results on the real prototype concerning the bandwidth of elements constituting MPI are shown. IPUSH, which is remote indirect wri... View full abstract»

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  • Compilation for Delay Impact Minimization in VLIW Embedded Systems

    Publication Year: 2006, Page(s):83 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB) | HTML iconHTML

    Tomorrow's embedded devices need to run high-resolution multimedia as well as need to support multi-standard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In this context, the register file is one of the key sources of power consumption and performance bottleneck, and its inappropriate design and manage... View full abstract»

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  • Real-Time Operating System Kernel for Multithreaded Processor

    Publication Year: 2006, Page(s):91 - 100
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (403 KB) | HTML iconHTML

    In embedded system development, multithreaded processors are used for further performance improvement to satisfy large-scale and sophisticated applications. PRESTOR-1, a multithreaded processor we developed, has a mechanism, a processor context buffer (PCB), that accommodates thread contexts spilt from built-in context slots. Threads/tasks located in the PCB are controlled and swapped for built-in... View full abstract»

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  • Author index

    Publication Year: 2006, Page(s): 101
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