Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

23-27 Sept. 1996

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  • Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit [front matter]

    Publication Year: 1996, Page(s):I - IX
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    Freely Available from IEEE
  • Author index

    Publication Year: 1996, Page(s):325 - 326
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    Freely Available from IEEE
  • Maximizing speed performance of multi-level combinational circuits implemented with pass transistors

    Publication Year: 1996, Page(s):15 - 18
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (436 KB)

    Speed optimization techniques are presented in this paper to reduce the propagation delay through multi-level combinational circuits. The circuits are built with a set of CMOS logic gates designed upon pass transistors and transmission gates. The speed optimization techniques include determining the order of connecting the input pins of the gates, determining the minimum number of inverters to red... View full abstract»

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  • Stochastic magnetic field micro-sensor

    Publication Year: 1996, Page(s):11 - 14
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (296 KB)

    Magnetic data field detection requires very small sensitive areas in the range of square-microns. This contribution presents a new MAGFET-driven stochastic flip-flop micro-sensor. In the device a calibration logic is integrated to compensate for technological tolerances. Fast and parallel magnetic field data detection will be possible on very small tracks in the future when an integrated array of ... View full abstract»

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  • High-performance crossbar interconnect for a VLIW video signal processor

    Publication Year: 1996, Page(s):45 - 49
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (520 KB)

    A programmable Very Long Instruction Word (VLIW) Video Signal Processor (VSP) Chip is currently under development. The design of this chip provides some unique VLSI tradeoffs. The architecture requires flexible, high-bandwidth interconnect at fast cycle times. The design targets 32-64 operations per cycle at clock rates in excess of 500 MHz. A high-performance crossbar interconnect has been design... View full abstract»

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  • Small area optical inputs for high speed CMOS circuits

    Publication Year: 1996, Page(s):7 - 10
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (332 KB)

    Compact and fast photoreceivers with on-chip photodiodes in standard CMOS technology have been developed as optical inputs for digital circuits. The time performance of different photodiodes and current/voltage converters has been investigated and optimized by simulations and experiments. The best performance with periodic signals of more than 250 MHz was found for a current comparator circuit wit... View full abstract»

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  • A fast compact addition architecture for low power microprocessors and DSP chips

    Publication Year: 1996, Page(s):41 - 44
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (348 KB)

    An addition scheme is presented which has comparable performance to carry-lookahead for the bit precisions required by most microprocessors and DSP chips. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Several adders of varying architectures and logic styles were built for comparison with our scheme. Designed... View full abstract»

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  • Macrocell design techniques that ease system level ASIC integration

    Publication Year: 1996, Page(s):3 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (480 KB)

    With the tremendous advances in process technology, ASIC integration capability has reached new levels that allow for developing complete systems on a chip, or system level ASICs. However, just because the silicon capabilities allow for these system level ASICs, there are a number of other capabilities that are required to successfully implement these designs. One such capability is the use of mac... View full abstract»

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  • SI technique application for colour image processing

    Publication Year: 1996, Page(s):287 - 290
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (396 KB)

    A new synthesis method of a multiport two-dimensional filter, a set of design tools based on this method and a library of subcells are described in the paper. It is possible to include the programs as modules into design system of integrated circuits (silicon compiler system). The basic cells of the presented multiport filter are delay lines and bilinear fully differential integrators. Realization... View full abstract»

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  • Computer design strategy for MCM-D/flip-chip technology

    Publication Year: 1996, Page(s):35 - 39
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (524 KB)

    A compelling case is made for using MCM-D (thin film MultiChip Module) flip-chip technology to build a `MegaChip' CPU consisting of an Instruction Fetch Unit and Execution Unit. By building part of the Instruction Fetch Unit in an optimized SRAM process, significant performance/cost gains are made. We also address the following important `implementation' (1) Partitioning high speed paths across th... View full abstract»

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  • A 800 μA, 105 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm

    Publication Year: 1996, Page(s):283 - 286
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    A 105 MHz crystal oscillator consuming 800 μA at 1.7 V supply is described. The oscillator is part of a regulated system in a wireless device where the oscillation frequency is controlled digitally. This digital trimming of oscillation frequency is realized by binary capacitor banks of 10-bit resolution. The oscillator can be pulled from ±35 ppm to the required frequency with 0.3 ppm acc... View full abstract»

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  • Development of embedded card-type processor RICE25PC and its packaging technology

    Publication Year: 1996, Page(s):27 - 31
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (772 KB)

    We developed a embedded card-type processor, RICE2SPC, for ATM (Asynchronous Transfer Mode) switching systems. To reduce the size of the card to that of ordinary credit cards, we developed ASIC (Application Specific Integrated Circuit) solutions for peripheral circuits of the CPU, LSI packaging by BGA (Ball Grid Array), board by build-up process, both outer layer plating copper and inner layer cop... View full abstract»

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  • A 60 MHz 0.7 mV-resolution CMOS comparator

    Publication Year: 1996, Page(s):279 - 282
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (260 KB)

    This paper describes the design of a CMOS comparator for high-speed data communication. The comparator consists of two regenerative sense amplifiers working in a pipelined fashion to achieve high speed. It operates from a single +5 V supply and is able to resolve 0.7 mV at 60 MHz sampling rate using a 0.9 μm CMOS process View full abstract»

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  • Format converter IC for field sequential color display

    Publication Year: 1996, Page(s):23 - 26
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (544 KB)

    This paper describes a field sequential color display controller (FSCDC) applied to format conversion of conventional video signals into field sequential format. With a special frame memory design, we attain a low cost system implement using conventional available DRAMs. High resolution and high contrast ratio color display system are thus acquired benefiting from FSCDC. With a built-in 100 Mhz DA... View full abstract»

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  • On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits

    Publication Year: 1996, Page(s):57 - 60
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (440 KB)

    Circuits designed with CMOS wave pipelined logic gates are not fully reliable, even after careful design and tuning, due to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths. This paper addresses the need for on-line correction of these faults. It presents a delay fault sensing technique for CMOS wave pipelining and the results for a des... View full abstract»

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  • Opportunities for non-dissipative computation [adiabatic logic]

    Publication Year: 1996, Page(s):297 - 300
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (380 KB)

    Recent advances in adiabatic or non-dissipative computation, as reflected in conceptions of novel static and dynamic energy recovery logic families, are described. The energy, power and peak power of these logic families are compared with conventional static and dynamic CMOS. Key challenges to successful implementation of adiabatic systems are summarized View full abstract»

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  • A moment matching based methodology for crosstalk analysis

    Publication Year: 1996, Page(s):67 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (536 KB)

    A new fast and accurate methodology for the crosstalk analysis of large VLSI IC interconnects is presented. The proposed approach finds a reduced order approximation of the original interconnect network using an extended moment matching technique. Subsequently, an analytical model of the crosstalk voltage in the time domain is obtained, and a compact model for the crosstalk peak amplitude is deriv... View full abstract»

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  • Reducing power dissipation in low voltage flash memories

    Publication Year: 1996, Page(s):305 - 308
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (340 KB)

    A new low voltage flash circuit model is presented. This SPICE model is used to identify techniques for reducing the average power dissipated in a flash memory during a programming cycle. The AND flash memory cell is used in this analysis. For a selected bitcell in a NOR block, the power dissipated is dominated by a band-to-band transient current. SPICE simulations show that this power can be redu... View full abstract»

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  • Timing and power models for CMOS repeaters driving resistive interconnect

    Publication Year: 1996, Page(s):201 - 204
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (416 KB)

    A delay and power model of a CMOS inverting repeater driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time and ... View full abstract»

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  • A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001

    Publication Year: 1996, Page(s):193 - 196
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (616 KB)

    GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a roadmap for interconnect design, and performance, energy, and area limits View full abstract»

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  • A unified placement algorithm to improve both performance and area through sliceable partitions

    Publication Year: 1996, Page(s):183 - 186
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (408 KB)

    A new placement approach integrating the legal placement arrangement into a combined method of global placement and constrained partitioning for simultaneous optimization of performance and area aspects based on slicing enumeration is presented. With the proposed placement approach the partitioning is constrained to sliceable partitions. This allows the control of critical nets and ensures legal p... View full abstract»

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  • Testing in a mixed-signal world

    Publication Year: 1996, Page(s):241 - 244
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    Wide differences in test signals used for analog and digital circuits make a common test for a mixed-signal device difficult. A divide and conquer strategy partitions the circuit into three types of blocks: analog, digital logic and memory. A design for testability structure using boundary scan and analog test bus allows very effective test application. With this design, separate specialized tests... View full abstract»

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  • Multichip module placement with heat consideration

    Publication Year: 1996, Page(s):175 - 178
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (356 KB)

    A new algorithm for multichip module placement, MPH, using a combined quad-partitioning, genetic search and simulated annealing approach is presented here. In addition to minimizing wire length and vias, the algorithm places chips so that heat is evenly distributed over the substrate. The proposed algorithm obtains better solutions in less time than the simulated annealing and min-cut algorithms o... View full abstract»

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  • Real-time implementation of speech recognition using RISC processor core

    Publication Year: 1996, Page(s):231 - 234
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (368 KB)

    A general application processor with analog interface, based on a RISC processor core, for speech recognition applications has been designed and implemented. The system, designed for large vocabulary applications, integrates speech analysis, feature extraction and pattern recognition, to achieve high recognition performance at low cost. Other speech processing can also utilize the flexible archite... View full abstract»

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  • Adaptation, learning and storage in analog VLSI

    Publication Year: 1996, Page(s):273 - 278
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (696 KB)

    Adaptation and learning are key elements in biological and artificial neural systems for computational tasks of perception, classification, association, and control. They also provide an effective means to compensate for imprecisions in highly efficient analog VLSI implementations of parallel application-specific processors, which offer real-time operation and low power dissipation. The effectiven... View full abstract»

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