Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

23-27 Sept. 1996

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  • Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit [front matter]

    Publication Year: 1996, Page(s):I - IX
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    Freely Available from IEEE
  • Author index

    Publication Year: 1996, Page(s):325 - 326
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    Freely Available from IEEE
  • A closed-form solution to the damped RLC circuit with applications to CMOS ground bounce estimation

    Publication Year: 1996, Page(s):73 - 78
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    A simplified RLC model depicting a packaged CMOS device is used to determine the fall time of an output buffer. The fall time is dependent on how many outputs are switching simultaneously. The analysis was compared with the measurements of a 0.5 μm CMOS test chip with good results. These results indicate that the fall time of a buffer is determined by the parasitic components in the system (R, ... View full abstract»

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  • An integrated, wireless microinstrument for monitoring skin temperature

    Publication Year: 1996, Page(s):107 - 110
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    This paper describes the initial design, construction and testing of an integrated, wireless, temperature microsensor designed to monitor skin temperature and transmit the information to a local receiver using a 350 MHz carrier frequency. The sensor chip measures 4.6 mm by 6.8 mm and is fully self-contained, incorporating the sensing circuitry as well as a microantenna on chip. The chip is fabrica... View full abstract»

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  • Use of binary decision diagrams in the modelling and synthesis of binary multipliers

    Publication Year: 1996, Page(s):159 - 162
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Previous research has proved that the size of binary decision diagrams (BDD) which model the outputs of a binary multiplier grows exponentially with the number of multiplier inputs. This paper presents a method of partitioning the multiplier in a manner which restricts the complexity to the carry bits, which results in BDD's which grow no faster than the square of the number of inputs. These carry... View full abstract»

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  • Design of an ASIC architecture for high speed fractal image compression

    Publication Year: 1996, Page(s):223 - 226
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    We report the results of the design and performance evaluation of an ASIC dedicated to fractal image compression. The ASIC is to be hosted on a PC platform by means of an interface board connected to the PCI bus. The obtained speed-up is 300 times with respect to the direct execution of the compression algorithm on a 100 MHz Pentium platform. The ASIC has been synthesized from VHDL and totals 1500... View full abstract»

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  • Testing in a mixed-signal world

    Publication Year: 1996, Page(s):241 - 244
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Wide differences in test signals used for analog and digital circuits make a common test for a mixed-signal device difficult. A divide and conquer strategy partitions the circuit into three types of blocks: analog, digital logic and memory. A design for testability structure using boundary scan and analog test bus allows very effective test application. With this design, separate specialized tests... View full abstract»

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  • A moment matching based methodology for crosstalk analysis

    Publication Year: 1996, Page(s):67 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    A new fast and accurate methodology for the crosstalk analysis of large VLSI IC interconnects is presented. The proposed approach finds a reduced order approximation of the original interconnect network using an extended moment matching technique. Subsequently, an analytical model of the crosstalk voltage in the time domain is obtained, and a compact model for the crosstalk peak amplitude is deriv... View full abstract»

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  • Opportunities for non-dissipative computation [adiabatic logic]

    Publication Year: 1996, Page(s):297 - 300
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Recent advances in adiabatic or non-dissipative computation, as reflected in conceptions of novel static and dynamic energy recovery logic families, are described. The energy, power and peak power of these logic families are compared with conventional static and dynamic CMOS. Key challenges to successful implementation of adiabatic systems are summarized View full abstract»

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  • High-performance crossbar interconnect for a VLIW video signal processor

    Publication Year: 1996, Page(s):45 - 49
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A programmable Very Long Instruction Word (VLIW) Video Signal Processor (VSP) Chip is currently under development. The design of this chip provides some unique VLSI tradeoffs. The architecture requires flexible, high-bandwidth interconnect at fast cycle times. The design targets 32-64 operations per cycle at clock rates in excess of 500 MHz. A high-performance crossbar interconnect has been design... View full abstract»

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  • Low complexity GSM modulator for integrated circuit implementations

    Publication Year: 1996, Page(s):103 - 106
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Reduced complexity Integrated Circuit (IC) design architecture for constant envelope modulation is presented. This method is demonstrated on the globally standardized Gaussian Minimum Shift Keying (GMSK) for the “Global System for Mobile Communications” (GSM). The in-phase and quadrature signals are generated directly from the input binary data, bypassing the separate steps of integrat... View full abstract»

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  • A 60 MHz 0.7 mV-resolution CMOS comparator

    Publication Year: 1996, Page(s):279 - 282
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    This paper describes the design of a CMOS comparator for high-speed data communication. The comparator consists of two regenerative sense amplifiers working in a pipelined fashion to achieve high speed. It operates from a single +5 V supply and is able to resolve 0.7 mV at 60 MHz sampling rate using a 0.9 μm CMOS process View full abstract»

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  • Using complex sequential modules in RTL synthesis

    Publication Year: 1996, Page(s):139 - 142
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    This paper presents a new method that enables our RTL-synthesis tool to use complex sequential modules such as counters, accumulators and shift-registers (CASRs). If the target library contains such modules, the method automatically recognizes them. If the RTL design contains patterns that can be implemented on CASR modules, the method maps them to the CASR modules found in the target library. Thi... View full abstract»

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  • Format converter IC for field sequential color display

    Publication Year: 1996, Page(s):23 - 26
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper describes a field sequential color display controller (FSCDC) applied to format conversion of conventional video signals into field sequential format. With a special frame memory design, we attain a low cost system implement using conventional available DRAMs. High resolution and high contrast ratio color display system are thus acquired benefiting from FSCDC. With a built-in 100 Mhz DA... View full abstract»

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  • Circuit design compliance checking in VLSI circuits

    Publication Year: 1996, Page(s):167 - 170
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    With the ever-increasing complexity, circuit verification at the full-chip level is a major bottleneck in the design of VLSI circuits. This paper presents procedures that verify a given CMOS/BiCMOS VLSI circuit for its compliance to a set of pre-defined rules or design styles. Predefined rules range from simple connectivity and sizing rules to specific circuit topologies ensuring acceptable circui... View full abstract»

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  • An alternative view on weighted random pattern testing

    Publication Year: 1996, Page(s):251 - 254
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    This paper describes a new and highly efficient approach for weighted random test pattern generation. In contrast to the state-of-the-art approaches, where input specific weights are computed, the proposed self-test method is tuned on the computation of global, pattern oriented weights: with each weight the generation of the related random test patterns is uniquely specified. The proposed self-tes... View full abstract»

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  • Hardware module selection for real time pipeline architectures using probabilistic cost estimation

    Publication Year: 1996, Page(s):147 - 150
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Module selection is a basic task of architectural synthesis which aims to optimize the cost of dedicated circuits. However, this task remains unresolved in the case of synthesizing pipeline architectures under real time constraint using a complex library exploiting multifunctional, pipeline, and multi-delay operators. This paper presents a new formalization and implementation of module selection i... View full abstract»

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  • Multichip module placement with heat consideration

    Publication Year: 1996, Page(s):175 - 178
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    A new algorithm for multichip module placement, MPH, using a combined quad-partitioning, genetic search and simulated annealing approach is presented here. In addition to minimizing wire length and vias, the algorithm places chips so that heat is evenly distributed over the substrate. The proposed algorithm obtains better solutions in less time than the simulated annealing and min-cut algorithms o... View full abstract»

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  • A new approach for Boolean function minimization

    Publication Year: 1996, Page(s):155 - 158
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    In this paper we present a new approach for Boolean function minimization. We introduce a new representation for sum of two terms that can be used to perform traditional Boolean minimization (ex. AB+AB¯=A) as well as terms of the type ABC+A¯B¯C¯. We call these terms as CTERMs. We introduce rules to combine CTERMS that would lead to new minimization algorithm. Since the minimiza... View full abstract»

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  • New architecture for high throughput-rate real-time 2-D DCT and the VLSI design

    Publication Year: 1996, Page(s):219 - 222
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and is of great necessity to meet the requirement of high speed. In this paper, a new architecture for the VLSI design of 2-D DCT has been developed. This architecture contains the following features: (1) using the programmable logic array (PL... View full abstract»

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  • An analytical approach to fine tuning in CMOS wave-pipelining

    Publication Year: 1996, Page(s):205 - 208
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Fine tuning is an integral part of a wave-pipelined design process to achieve maximum clock speed. In this paper we present analytical approaches to two main components of the fine tuning process for CMOS designs, the computation of effective load capacitance at gate outputs and the transistor sizing of the driving gates to achieve equal rise and fall delay. Comparisons with Spice simulation resul... View full abstract»

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  • Sampling based design verification using design error models

    Publication Year: 1996, Page(s):197 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A new simulation based design verification system employing design error models and statistical sampling techniques, is developed. It provides a simulation coverage which can be used as a guide in the verification process, and estimates the coverage quickly using sampling techniques. The simulation results demonstrate the effectiveness of this approach. This system can be used as an efficient desi... View full abstract»

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  • A 400 megasample per second digital receiver ASIC

    Publication Year: 1996, Page(s):235 - 238
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    An application specific integrated circuit has been designed to perform digital quadrature demodulation and other signal processing functions on digitized IF data in electronic warfare receivers. A fully pipelined, parallel architecture implemented on a GaAs gate array permits a nominal sampling rate of 400 megasamples per second. At this sampling rate the -3 dB bandwidth exceeds 80 MHz View full abstract»

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  • Low power design of two-dimensional DCT

    Publication Year: 1996, Page(s):309 - 312
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    This paper discusses several techniques used in reducing power for a two-dimensional discrete cosine transform (2D DCT) design. These techniques include removal of circuit blocks that computes the DCT coefficients which will be quantized to zeros, re-ordering of operations in constant-multipliers to reduce transition probability, and re-designing cells for low-voltage operation. An 8×8 2D DC... View full abstract»

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  • Ramp input response of RC tree networks

    Publication Year: 1996, Page(s):63 - 66
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Closed form expressions are presented to accurately describe the delay characteristics of RC tree networks. The Penfield-Rubinstein-Horowitz approach to estimating the step function response of RC trees has been extended to consider ramp inputs. This improves timing accuracy by considering the shape of the input waveform driving each individual interconnect tree while maintaining computational sim... View full abstract»

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