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Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

23-27 Sept. 1996

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  • Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit [front matter]

    Publication Year: 1996, Page(s):I - IX
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    Freely Available from IEEE
  • Author index

    Publication Year: 1996, Page(s):325 - 326
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    Freely Available from IEEE
  • An integrated, wireless microinstrument for monitoring skin temperature

    Publication Year: 1996, Page(s):107 - 110
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    This paper describes the initial design, construction and testing of an integrated, wireless, temperature microsensor designed to monitor skin temperature and transmit the information to a local receiver using a 350 MHz carrier frequency. The sensor chip measures 4.6 mm by 6.8 mm and is fully self-contained, incorporating the sensing circuitry as well as a microantenna on chip. The chip is fabrica... View full abstract»

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  • Optimal circuit design for low power CMOS GSI

    Publication Year: 1996, Page(s):313 - 316
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel data... View full abstract»

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  • Circuit design compliance checking in VLSI circuits

    Publication Year: 1996, Page(s):167 - 170
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    With the ever-increasing complexity, circuit verification at the full-chip level is a major bottleneck in the design of VLSI circuits. This paper presents procedures that verify a given CMOS/BiCMOS VLSI circuit for its compliance to a set of pre-defined rules or design styles. Predefined rules range from simple connectivity and sizing rules to specific circuit topologies ensuring acceptable circui... View full abstract»

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  • A moment matching based methodology for crosstalk analysis

    Publication Year: 1996, Page(s):67 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    A new fast and accurate methodology for the crosstalk analysis of large VLSI IC interconnects is presented. The proposed approach finds a reduced order approximation of the original interconnect network using an extended moment matching technique. Subsequently, an analytical model of the crosstalk voltage in the time domain is obtained, and a compact model for the crosstalk peak amplitude is deriv... View full abstract»

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  • Low complexity GSM modulator for integrated circuit implementations

    Publication Year: 1996, Page(s):103 - 106
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Reduced complexity Integrated Circuit (IC) design architecture for constant envelope modulation is presented. This method is demonstrated on the globally standardized Gaussian Minimum Shift Keying (GMSK) for the “Global System for Mobile Communications” (GSM). The in-phase and quadrature signals are generated directly from the input binary data, bypassing the separate steps of integrat... View full abstract»

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  • Low power design of two-dimensional DCT

    Publication Year: 1996, Page(s):309 - 312
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    This paper discusses several techniques used in reducing power for a two-dimensional discrete cosine transform (2D DCT) design. These techniques include removal of circuit blocks that computes the DCT coefficients which will be quantized to zeros, re-ordering of operations in constant-multipliers to reduce transition probability, and re-designing cells for low-voltage operation. An 8×8 2D DC... View full abstract»

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  • Verification of ASIC designs in VHDL using computer-aided reasoning

    Publication Year: 1996, Page(s):163 - 166
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The paper describes verification of a 32-bit processor chip using formal reasoning. The VHSIC Hardware Description Language (VHDL) code for the processor and its components have been proven to meet the formal specification which uncovered interesting specification ambiguities and design errors. The paper provides an early evaluation of the role of formal reasoning in the verification of VHDL desig... View full abstract»

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  • Ramp input response of RC tree networks

    Publication Year: 1996, Page(s):63 - 66
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Closed form expressions are presented to accurately describe the delay characteristics of RC tree networks. The Penfield-Rubinstein-Horowitz approach to estimating the step function response of RC trees has been extended to consider ramp inputs. This improves timing accuracy by considering the shape of the input waveform driving each individual interconnect tree while maintaining computational sim... View full abstract»

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  • Format converter IC for field sequential color display

    Publication Year: 1996, Page(s):23 - 26
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper describes a field sequential color display controller (FSCDC) applied to format conversion of conventional video signals into field sequential format. With a special frame memory design, we attain a low cost system implement using conventional available DRAMs. High resolution and high contrast ratio color display system are thus acquired benefiting from FSCDC. With a built-in 100 Mhz DA... View full abstract»

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  • Performance optimization and system clock determination for synthesis of DSP cores targeting FPGAs

    Publication Year: 1996, Page(s):151 - 154
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    In this paper, we present details of an integer linear programming (ILP) formulation for synthesis of high performance digital signal processing architectures targeting FPGA implementation. The formulation allows general multi-level chaining of operations in conjunction with multicycle and deeply pipelined function units. This novel ILP formulation simultaneously performs scheduling and binding wh... View full abstract»

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  • Requirements for specification of embedded systems

    Publication Year: 1996, Page(s):133 - 137
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    With the increasing acceptance of automation of the lower-level design tasks, designers are increasingly focusing their efforts at the more abstract stages of the system-design process. In this paper, we examine some of the issues related to specification of embedded systems. We first introduce the notion of a conceptual model as being the first step of system specification. We demonstrate the nee... View full abstract»

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  • Sampling based design verification using design error models

    Publication Year: 1996, Page(s):197 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A new simulation based design verification system employing design error models and statistical sampling techniques, is developed. It provides a simulation coverage which can be used as a guide in the verification process, and estimates the coverage quickly using sampling techniques. The simulation results demonstrate the effectiveness of this approach. This system can be used as an efficient desi... View full abstract»

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  • Differential PSK detector ASIC design for direct sequence spread spectrum radio

    Publication Year: 1996, Page(s):97 - 101
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    In this paper we present an optimized architecture for differential PSK detection which effectively minimizes the required logic complexity for ASIC implementation. This complexity reduction is obtained by carrying out intelligent truncation of the detector input words and by utilizing a bit-serial/word-parallel structure. We also show that this can be done without degrading the performance in ter... View full abstract»

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  • Reducing power dissipation in low voltage flash memories

    Publication Year: 1996, Page(s):305 - 308
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A new low voltage flash circuit model is presented. This SPICE model is used to identify techniques for reducing the average power dissipated in a flash memory during a programming cycle. The AND flash memory cell is used in this analysis. For a selected bitcell in a NOR block, the power dissipated is dominated by a band-to-band transient current. SPICE simulations show that this power can be redu... View full abstract»

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  • Real-time implementation of speech recognition using RISC processor core

    Publication Year: 1996, Page(s):231 - 234
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    A general application processor with analog interface, based on a RISC processor core, for speech recognition applications has been designed and implemented. The system, designed for large vocabulary applications, integrates speech analysis, feature extraction and pattern recognition, to achieve high recognition performance at low cost. Other speech processing can also utilize the flexible archite... View full abstract»

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  • VLSI design of the reassembly management for ATM/AAL

    Publication Year: 1996, Page(s):115 - 118
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The reassembly management is one of the key components in the ATM receiving function. To achieve high memory efficiency, we adopt a shared memory approach with the linked-list structure to support the ATM/AAL reassembly management. The chip with the die size 6570×6490 μm 2 and packaged in a 144-pin CQFP is fabricated by using TSMC 0.8 μm SPDM N-well CMOS technology. The desi... View full abstract»

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  • Computer design strategy for MCM-D/flip-chip technology

    Publication Year: 1996, Page(s):35 - 39
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    A compelling case is made for using MCM-D (thin film MultiChip Module) flip-chip technology to build a `MegaChip' CPU consisting of an Instruction Fetch Unit and Execution Unit. By building part of the Instruction Fetch Unit in an optimized SRAM process, significant performance/cost gains are made. We also address the following important `implementation' (1) Partitioning high speed paths across th... View full abstract»

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  • Use of binary decision diagrams in the modelling and synthesis of binary multipliers

    Publication Year: 1996, Page(s):159 - 162
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Previous research has proved that the size of binary decision diagrams (BDD) which model the outputs of a binary multiplier grows exponentially with the number of multiplier inputs. This paper presents a method of partitioning the multiplier in a manner which restricts the complexity to the carry bits, which results in BDD's which grow no faster than the square of the number of inputs. These carry... View full abstract»

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  • Testing in a mixed-signal world

    Publication Year: 1996, Page(s):241 - 244
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Wide differences in test signals used for analog and digital circuits make a common test for a mixed-signal device difficult. A divide and conquer strategy partitions the circuit into three types of blocks: analog, digital logic and memory. A design for testability structure using boundary scan and analog test bus allows very effective test application. With this design, separate specialized tests... View full abstract»

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  • High-performance crossbar interconnect for a VLIW video signal processor

    Publication Year: 1996, Page(s):45 - 49
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A programmable Very Long Instruction Word (VLIW) Video Signal Processor (VSP) Chip is currently under development. The design of this chip provides some unique VLSI tradeoffs. The architecture requires flexible, high-bandwidth interconnect at fast cycle times. The design targets 32-64 operations per cycle at clock rates in excess of 500 MHz. A high-performance crossbar interconnect has been design... View full abstract»

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  • On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits

    Publication Year: 1996, Page(s):57 - 60
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Circuits designed with CMOS wave pipelined logic gates are not fully reliable, even after careful design and tuning, due to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths. This paper addresses the need for on-line correction of these faults. It presents a delay fault sensing technique for CMOS wave pipelining and the results for a des... View full abstract»

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  • Pixel cache architecture with FIFO implemented within an ASIC

    Publication Year: 1996, Page(s):19 - 22
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Implementation technology for 3D pixel cache and performance evaluation of a graphics processor Truga001, with 12 embedded processors within a single chip, are described. The chip can render 4 million vectors/s (10 pixels/vector) or 1.2 million triangle polygons/s (100 pixels/polygon) with Phong shading, texture mapping and hidden surface removal. A pixel-array configured with 8(x)×4(y)&time... View full abstract»

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  • An efficient path-delay fault simulator for mixed level circuits

    Publication Year: 1996, Page(s):263 - 266
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results pr... View full abstract»

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