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Photovoltaic Energy Conversion, Conference Record of the 2006 IEEE 4th World Conference on

Date 7-12 May 2006

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  • Conference Record of the 2006 IEEE 4th World Conference on Photovoltaic Energy Conversion

    Page(s): nil1
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    Freely Available from IEEE
  • [Copyright notice]

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    Freely Available from IEEE
  • Table of contents

    Page(s): nil3 - nil32
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  • High-Efficiency Multi-Crystalline Silicon Solar Cells Using Screen-Printed Electrode and Wet Etching Textured Surface

    Page(s): 1259 - 1262
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    The enhancement of the conversion efficiency of multi-crystalline silicon (mc-Si) solar cells using screen-printed electrode (SPE) on wet-etching textured surface (WETS) was examined. SPE of Ag paste of 50mum width realized the narrow interval of the finger pattern without increasing shadowing area. The reduction of both contact resistance and finger interval permits doubling the sheet resistance and increases the quantum efficiency of n-layer at front surface. Consequently, the conversion efficiency of 17.4% was obtained for a mc-Si solar cell 100mm square View full abstract»

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  • Optimization of Interface Properties in a-Si:H/c-Si Heterojunction Solar Cells

    Page(s): 1263 - 1266
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    We report on the optimization of hydrogenated amorphous silicon/crystalline silicon (a-Si:H/c-Si) heterojunction solar cells which were completely processed at temperatures below 230degC. Efficient solar cells based on both n-type and on p-type c-Si substrates were performed. In contrast to the approach from Sanyo no additional a-Si:H(i) buffer layer was used. Instead the conditions of the amorphous silicon preparation by conventional plasma enhanced chemical vapor deposition (PECVD) were optimized and several wet- or plasma chemical treatments were applied to improve the interface properties. The highest efficiencies so far are 17.4 % on p-type c-Si wafers and 19.8 % on n-type c-Si wafers View full abstract»

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  • Solar Light-Induced Opacity of Mind Cells

    Page(s): 1267 - 1270
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    Multi-interface solar cells exhibit a dramatically low UV- and blue-spectrum photovoltaic performance independently of the electronic quality of their surface. A paradox can even be observed, the better the electronic passivation the poorer the conversion efficiency. The effect can be explained by solar light-induced opacity, which reduces considerably or even totally the photon penetration, into the device bulk. This opacity results from a feedback occasioned by the free-carrier absorption: better surface passivation, higher free-carrier density, stronger surface dead zone absorptance. Particularly, the total energy of the incident short wavelength beam can be absorbed in front of a carrier collection limit buried in the emitter. This limit acts simultaneously on the electronic performance, blocking free-carriers, and on the optical performance, being at the origin of an enhancement of the absorptance. As a consequence, a thin surface stratum dominates the optical functions of MIND cells through the free-carrier gas confined inside it. The main characterization methods used were reflectivity and spectral response with a varying intensity incident beam. The investigation allows modification of the free-carrier confinement using different device architectures. The results demonstrate the domination of the free-carrier optical functions on the multi-interface cell conversion View full abstract»

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  • Investigation of the Surface Passivation of P+-Type Si Emitters by PECVD Silicon Carbide Films

    Page(s): 1271 - 1274
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    The surface passivation of an industrial applicable (e.g. screen printing) 60 Omegasq/ p+ boron emitter on Cz n-type c-Si wafers by amorphous SiCx films is investigated. A partial optimization of the deposition conditions of the SiCx films was performed resulting in an improved passivation quality of the SiCx films which also serves as anti-reflection coating. Passivation quality is determined by measuring the injection level dependency of the effective minority carrier lifetime using the quasi-steady state photoconductance method. Combining the information form the boron diffusion profile measured by SIMS and injection level dependent lifetime curves it can be concluded that a boron depletion layer formed during in-situ drive-in and oxidation has a detrimental effect on the passivation quality. Changing the diffusion conditions to prepare an improved boron profile with a similar sheet resistance should result in a further improvement of the passivation quality. This could include a reduction or a removal of the boron depletion layer at the emitter surface View full abstract»

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  • Industrial Rear Sin-Passivated Multicrystalline Silicon Solar Cells

    Page(s): 1275 - 1278
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    The utilisation of progressively thinner wafers for solar cells leads to an increasing importance of rear surface passivation. In this work we investigate different solar cell processes for industrial rear side passivated solar cells using silicon nitride (SiN) on both sides and screen printed contacts. All solar cells were made by phosphorus emitter diffusion on p-type wafers. For a sufficient rear surface passivation, a parasitic rear emitter must be avoided. Therefore, we carefully compared different processes comprising rear SiN as barrier during phosphorus diffusion as well as parasitic emitter removal by etching after phosphorus diffusion. Furthermore two processes for rear side contacting through a silicon nitride layer were tested. The first process is firing of a screen printed aluminium grid through the backside SiN. The second process uses laser ablation to open a thick rear SiN followed by a full area screen printed rear contact. Additionally, a possible degradation of the SiN due to firing of aluminium contact fingers through the SiN layer was investigated using minority carrier lifetime topography before and after firing of the wafers. Efficiencies of up to 14.7 % were obtained on 200 mum thick wafers using SiN layers on both sides. However, these processes are still excelled by the conventional solar cell process using a screen printed full area aluminium rear contact, which lead to an efficiency of 15.3 % on a 200 mum thick neighbouring wafer View full abstract»

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  • Precise Performance Measurement of High-Efficiency Crystalline Silicon Solar Cells

    Page(s): 1279 - 1282
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    The effect of the sweep speed and direction on the I-V measurement of state-of-the-art high-efficiency c-Si cells and modules such as HIT and backside-contact technologies is investigated, in order to clarify the precise characterization techniques for those devices. The Pmax and FF of these devices with conversion efficiencies of ~20% show significant dependence on the sweep conditions by 5-10% or more, when the sweep speed is less than 50-100 msec. Their I-V measurements should be carried out in the conditions where the result is independent on both the sweep direction and speed View full abstract»

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  • Effect of Process Parameter Variation in Deposited Emitter and Buffer Layers on the Performance of Silicon Heterojunction Solar Cells

    Page(s): 1283 - 1286
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    Heterostuctures of amorphous silicon (a-Si:H) and n-type crystalline silicon (c-Si) were investigated with special emphasis on the effect of emitter [p (a-Si:H)] and buffer layer [i (a-Si:H)] processing conditions. Boron (B)-doping in emitter layer sensitively affects performance of heterojunction solar cells without a buffer layer and controls valence band offset (DeltaEV) at the hetero-interface. Insertion of 10 nm buffer layers passivate c-Si surface very efficiently albeit with an increased DeltaEV and poor carrier transport across the heterojunction. Consequently, an open circuit voltage (Voc) of 700 mV was achieved with low fill factor (FF). Buffer layers deposited at high H2/SiH4 ratio (R=40) and/or at higher temperature (300degC) improve FF (77%) but lead to lower Voc (638 mV). Therefore, the emitter and the buffer layer process parameters play important roles to determine the band alignment and carrier transport across the a-Si:H / c-Si hetero-interface View full abstract»

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  • Characteristic Evaluation of SiNx: H Films Passivation Effect on Ga-doped Multi-crystalline Silicon Wafers

    Page(s): 1287 - 1290
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (201 KB) |  | HTML iconHTML  

    This paper presents the effect of silicon nitride (SiNx:H) films formed by plasma-enhanced chemical vapor deposition (PECVD) method on Ga-doped multi-crystalline silicon (mc-Si) wafers including the passivation quality and carrier lifetime improvement after hydrogenation. The FT-IR spectra of SiNx:H films deposited at different SiH4/NH3 gas flow ratios in PECVD are used to calculated the hydrogen concentrations and bond densities of Si-Hn, N-H and Si-N were calculated. Furthermore, the effect of forming gas annealing (FGA) on the effective lifetime of passivated wafers by PECVD is investigated at different temperatures View full abstract»

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  • Impact of Rear-Surface Passivation on MWT Performances

    Page(s): 1291 - 1294
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    Back-contact metal-wrap-through (MWT) solar cells are very attractive for implementation into industrial production lines. They combine the advantages of back-contact cells and the potential of easy integration into the production lines of standard cells. Nonetheless, they tend to show lower fill factors and open-circuit voltages than conventional cells. This is attributed to a non-linear shunt behavior under the emitter busbars and is believed to arise from a too-deep penetration of the silver paste printed on the emitter region on the rear during the firing step. In order to improve the MWT solar cells performances, we propose to deposit on the rear-surface a full coverage layer of a dielectric material. This layer is used first to protect the emitter during the firing step; but if it is smartly chosen, it can also be used as passivating layer for the base surface. In this work, we have processed 12.5times12.5 cm2 mc-Si wafers into 220-mum-thick MWT cells, including the deposition of a passivating dielectric layer on the rear surface. By means of dark lock-in thermography measurements, we observe that the shunting effect in the resulting cells is greatly reduced compared to neighboring cells processed into MWT with an Al-BSF rear-surface passivation. The dielectric plays in addition its role of surface passivation, according to the nearly 7 mV increase observed on the open-circuit voltage even on thick wafers. We also observe a 1.4% FF absolute increase, resulting in a 0.6% absolute efficiency increase View full abstract»

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  • Carrier Lifetime as a Developmental and Diagnostic Tool in Silicon Heterojunction Solar Cells

    Page(s): 1295 - 1298
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    Minority carrier lifetime measurements were used to optimize processes for amorphous/crystalline silicon heterojunction solar cells. A blue filter highlights surface lifetime and is used to determine the interaction between the front and rear depositions. On n-type substrates, depositing the front p-type layer first led to contamination of the rear surface such that a subsequent n-type deposition on the rear intended as a back surface field had no passivating quality and giving cells with low open-circuit voltages only 580 mV. Switching the order of deposition and depositing the rear n-layer first, improved the quality of the rear passivation and subsequently increased open circuit voltages to over 620 mV; without intrinsic buffer layers. Depositions of intrinsic material resulted in lifetimes of 2.4 ms, and wafer cleaning was found to have a significant impact on measured lifetime. Finally, immersion in hydrofluoric acid was found to be the easiest way to measure substrate lifetime above 1 ms View full abstract»

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  • Two-Dimensional Modeling of EWT Multicrystalline Silicon Solar Cells and Comparison with the IBC Solar Cell

    Page(s): 1299 - 1303
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (322 KB) |  | HTML iconHTML  

    In this study two-dimensional (2D) computer simulations of the n +pn+ emitter-wrap-through (EWT) cell structure with industrially relevant parameters is performed and a comparison is made with p-type substrate interdigitated back contact (IBC) cells. Our simulation results show that the EWT cell is particularly suited for low bulk lifetimes and thin substrates. Simulation results indicate that achieving a lifetime of around 45 mus will be sufficient to realize very high-efficiency EWT cells. The effect of different cell parameters (e.g., surface recombination velocities, thickness, bulk resistivity, bulk lifetime, cell geometry, etc.) is explored. The EWT cell shows much higher robustness to poor material lifetime as well as surface passivation compared to the IBC cell. While a 1 ms lifetime IBC cell drops to efficiencies less than 14.5% for an intrinsic surface recombination velocity (SRV) of 10,000 cm/s, the EWT cell can maintain efficiencies above 15% at a much lower bulk lifetime of 30 mus and higher SRV of 300,000 cm/s View full abstract»

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  • Two-Step Liquid Phase Epitaxy Growth of Silicon on Patterned Silicon Substrates in Ar Atmosphere

    Page(s): 1304 - 1307
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    This paper presents the results of the investigation on the liquid phase epitaxy growth of silicon thin films carried out in one-step and two-step modes. The new approach to the process of LPE growth has been applied, based on the fact that the saturation and growth occur in the separate steps under Ar atmosphere, i.e. the sample substrate is introduced into the tube after the saturation step and cooling the apparatus to the room temperature. The results show that ELO layers of the maximum value of the aspect ratio were obtained in case of the application of 0.5degC/min cooling rate and supercooling equal DeltaT=60degC in two-step mode of growth. The defect density of the ELO layers determined by Secco etching was smaller approximately by the factor of 10 than the defect density of the Si substrates used, reaching 1.95middot104 cm-2 View full abstract»

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  • Investigation of the Effect of Resistivity and Thickness on the Performance of Cast Multicrystalline Silicon Solar Cells

    Page(s): 1308 - 1311
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    A low resistivity of 0.2-0.3 Omegacm has been shown to be optimum for high quality single crystal silicon for solar cells. However, for lower quality cast mc-Si, this optimum resistivity increases owing to a dopant-defect interaction, which reduces the bulk lifetime at lower resistivities. In this study, solar cells fabricated on 225 mum thick cast multicrystalline silicon wafers showed very little or no enhancement in efficiency with the decrease in resistivity. However, Voc enhancement was observed for the lower resistivity cells despite significantly lower bulk lifetimes compared to higher resistivity cells. After gettering (during P diffusion) and hydrogenation (from SiNx) steps used in cell fabrication, the bulk lifetime in 225 mum thick wafers from the middle of the ingot decreased from 253 mus to 135 mus when the resistivity was lowered from 1.5 Omegacm to 0.6 Omegacm. This paper shows that solar cells fabricated on 175 mum thick, 1.5 Omegacm, wafers showed no appreciable loss in the cell performance when compared to the 225 mum thick cells, consistent with PC1D modeling View full abstract»

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  • Low Light Performance of Mono-Crystalline Silicon Solar Cells

    Page(s): 1312 - 1314
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    This paper reports on low light performance results of solar cells manufactured by SunPower Corporation. We have investigated the effect of shunt resistance on low light performance of solar cells. We present I-V curves and measured cell efficiencies over irradiance levels from 1 to 0.001 Suns at AM1.5g spectrum, standard test conditions. A comparison with a theoretical model including the effect of shunt resistance and diode ideality factor is presented. We have also investigated the power density generated by our standard A-300 cells at various low light conditions. We infer from the results the possibility to use SunPower solar cells for PV powered products for low light applications View full abstract»

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  • Determining Components of Series Resistance from Measurements on a Finished Cell

    Page(s): 1315 - 1318
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    Detailed expressions are given for computing the components of series resistance for a cell with a common contact pattern of parallel, equally-spaced gridlines which are perpendicular to two or more busbars. Front busbars and gridlines, contact resistance, emitter sheet, substrate, back metal and back busbars are all considered. No detailed thickness profiles are needed for any feature, only basic lengths and separations along with four-point resistance measurements. Results are given for a two-bus 15 cm square multicrystalline silicon cell having an efficiency of 15.0%. The total series resistance is 1.04 Omega-cm2, dominated by the gridline contribution. The addition of a third busbar is calculated to result in an increase in FF of 0.018, corresponding to an increase of 0.36% in absolute efficiency. A method for providing a coarse map of pseudo contact resistance for a finished cell, using only a four-point probe, is also introduced View full abstract»

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  • A Systematic Approach to Reduce Process-Induced Shunts in Back-Contacted MC-Si Solar Cells

    Page(s): 1319 - 1322
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (693 KB) |  | HTML iconHTML  

    One of the main reasons why back-contact (PUM) cells stay somewhat behind in efficiency is because of their lower shunt resistance. A simple method was developed to determine the shunt resistance of the individual process-induced shunt paths. These contributions have led to an electrical model describing the process-induced shunt paths. Individual shunt paths were analysed in detail. Changes in processing were introduced to eliminate the shunting problems. These changes resulted in the shunt resistances beyond 5 kOmegacm2 on 225 cm2 cells with industrial processing View full abstract»

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  • Diffusion Paste Development for Printable IBC and Bifacial Silicon Solar Cells

    Page(s): 1323 - 1325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    Increasing cell efficiency and lowering the cost of solar cell manufacturing is a continuous challenge in solar cell industries. Higher efficiency concepts like interdigitated back contact (IBC), and bifacial cells, with using thinner silicon solar cells are ways to reduce the total solar cell manufacturing cost. Typically the high efficiency concepts require costly extra processing steps. Developing the proper paste for printing application of high efficiency concepts could make these designs cost effective and easily manufactured. These pastes can be printable in a continuous manner using processes like screen printing or ink jet printing. This paper describes newly developed low cost phosphorous, boron, and diffusion barrier pastes. It shows the characterization of the newly developed phosphorous paste (99-038), boron paste (99-033), and diffusion barrier paste (99-001). These low cost pastes can easily be printed and make high efficiency concept cell designs a low cost reality. Characteristic features of sheet resistance, junction depth and minority carrier lifetime is discussed View full abstract»

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  • 18% Large Area Screen-Printed Solar Cells on Textured MCZ Silicon with High Sheet Resistance Emitter

    Page(s): 1326 - 1329
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    In this paper we report on high efficiency screen-printed 49 cm2 solar cells fabricated on randomly textured float zone (1.2 ¿-cm) and magnetic Czochralski (MCZ) silicon with resistivities of 1.2 and 4.8 ¿-cm, respectively. A simple process involving POCl3 diffused emitters, low frequency PECVD silicon nitride deposition, Al back contact print, Ag front grid print followed by co-firing of the contacts and forming gas anneal produced efficiencies of 17.6% on 1.2 ¿-cm textured float Zone Si, 17.9% on 1.2 ¿-cm MCZ Si and 18.0% on 4.8 ¿-cm MCZ Si. A combination of high sheet resistance emitter (~95 ¿-/¿) and the surface texturing resulted in a short circuit current density of 37.8 mA/cm2 in the 4.8 ¿-cm MCZ cell, 37.0 mA/cm2 in the 1.2 ¿-cm2 MCZ cell and 36.5 mA/cm2 in the 1.2 ¿-cm2 float zone cell. The open circuit voltages were consistent with the base resistivities of the two materials. The fill factors were in the range of 0.760-0.770 indicating there is considerable room for improvement. Detailed modeling and analysis is performed to explain the cell performance and provide guidelines for achieving 20% efficient screen-printed cells on MCZ Si. View full abstract»

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  • Ribbon Growth on Substrate and Molded Wafer-Two Low Cost Silicon Ribbon Materials for PV

    Page(s): 1330 - 1333
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    This paper focuses on two very promising silicon ribbon materials currently produced for research: ribbon growth on substrate (RGS) by ECN solar energy and molded wafer (MW) by GE Energy. Both materials are investigated in terms of solar cell processing and characterisation. First cell results of large area 10times10 cm2 RGS cells are presented as well as results from 5times5 cm2 cells processed from 8times12 cm2 RGS and 12.5times12.5 cm2 MW wafers View full abstract»

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  • Fabrication of μc-3C-SiC/c-Si Heterojunction Solar Cell by Hot Wire CVD System

    Page(s): 1334 - 1337
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    N-type microcrystalline 3C-SiC:H films are deposited by hot wire chemical vapor deposition (HWCVD) at a low substrate temperature (~300degC). Heterojunction silicon based photovoltaic devices are fabricated by depositing wide band gap n-type muc-3C-SiC thin films on p-type Si wafer, whose thickness and resistivity are 200 mum and 1-10 Omega-cm respectively. The silicon wafers were textured by alkaline etchent prior to the device fabrication. The photovoltaic parameters of a typical device are found to be Voc=560 mV, Jsc=35.0 mA/cm2, F.F.=0.724, eta=14.20%. Numerical analysis has been performed by using AFORS-HET, one dimensional device simulator to find out the probable cause of the change in device parameters before and after ageing of the filament View full abstract»

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  • Investigation of Modified Screen-Printing Al Pastes for Local Back Surface Field Formation

    Page(s): 1338 - 1341
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    This paper reports on a low-cost screen-printing process to form a self-aligned local back surface field (LBSF) through dielectric rear surface passivation. The process involved formation of local openings through a dielectric (SiNx or stacked SiO2/SiNx) prior to full area Al screen-printing and a rapid firing. Conventional Al paste with glass frit degraded the SiNx surface passivation quality because of glass frit induced pinholes and etching of SiNx layer, and led to very thin LBSF regions. The same process with a fritless Al paste maintained the passivation quality of the SiNx, but did not provide an acceptably thick and uniform LBSF. Al pastes containing appropriate additives gave better LBSF because of the formation of a thicker and more uniform Al-BSF region. However, they exhibited somewhat lower internal back surface reflectance (<90%) compared to conventional Al paste on SiNx. More insight on these competing effects is provided by fabrication and analysis of complete solar cells View full abstract»

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  • Low-Cost Multicystalline Silicon Wafers by Purifying Metallurgical Grade Silicon with Tin Solution

    Page(s): 1342 - 1345
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    The PV industry is currently facing serious difficulty in finding silicon feedstock to shore up their expansion plan to meet the rapid growth of the solar cell market. The work reported here is an effort to tackle the severe problem of silicon shortage for PV industry, and to bring down the cost for solar wafer production. A single-step process of producing silicon wafers directly from metallurgical grade silicon (MGSi) is being developed in GT Equipment Technologies, Inc (GTi). In this process, tin is used as a solvent to dissolve both silicon and impurities in the MGSi, and to retain most of the impurities during silicon crystallization. By applying the shaped crystal growth technology, silicon ribbons are pulled out of the Si-Sn melt. The thin silicon ribbons can be used directly as solar wafers. The final goal of this project is to obtain silicon ribbon that can be used directly as wafers for solar cells with targeting efficiency of no less than 14%. The preliminary objectives of the current research phase is to obtain 2" wide silicon ribbons, to analyze the purity of the grown ribbons, to characterize the electrical properties of the ribbon, and to develop a prototype puller for growing 5 to 6 inch wide silicon ribbons out of the Si-Sn solution. The experimental work on the single-step silicon wafer from MG-Si so far has demonstrated that silicon ribbons can be pulled from the MG-Si and Sn solution. Significant reduction of concentration in the grown ribbons has been observed for most of the metallic impurities. The reduction effect results from partitioning of impurities into tin. However, the reduction of both boron and phosphorus is not significant. Also, the obtained samples contain large amount of tin (several hundred ppm to 1%). The measured lifetime of the obtained wafer is still low (0.1 to 1.0 microsecond). Further reduction in boron and phosphorus level is required and the effect the tin inclusion needs to be investigated View full abstract»

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