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Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on

2-4 Oct. 1995

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Displaying Results 1 - 25 of 106
  • Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors

    Publication Year: 1995
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    Freely Available from IEEE
  • Testing-what's missing? An incomplete list of challenges

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    Summary form only given. As the testing area becomes mature, the challenges it poses shift. We describe some of these challenges and how they are addressed in recent works in various areas of testing. In recent years, the formulations of testing problems have changed from "given a problem, find a solution" to "given a problem and quality measures, find a high-quality solution". Quality guarantees ... View full abstract»

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  • Index of authors

    Publication Year: 1995
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    Freely Available from IEEE
  • Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors

    Publication Year: 1995, Page(s):532 - 537
    Cited by:  Papers (23)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    Simulation is still the primary, although inadequate, resource for verifying the conformity of a design to its functional specification. Fortunately, most errors in the early stages of design involve only the control flow in the circuit. We define the functional coverage of a given sequence of verification vectors as the amount of control behavior exercised by them. We present a novel technique fo... View full abstract»

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  • Verification of a subtractive radix-2 square root algorithm and implementation

    Publication Year: 1995, Page(s):526 - 531
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    Many modern microprocessors implement floating point square root hardware using subtractive algorithms. Such processors include the HP PA7200, the MIPS R4400, and the Intel Pentium. The Intel Pentium division bug highlights the importance of verifying such implementations. In this paper we discuss the verification of a radix-2 square root unit similar to that used in the MIPS R4400. The verificati... View full abstract»

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  • Interrupt-based hardware support for profiling memory system performance

    Publication Year: 1995, Page(s):518 - 523
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    Fueled by higher clock rates and superscalar technologies, growth in processor speed continues to outpace improvement in memory system performance. Reflecting this trend, architects are developing increasingly complex memory hierarchies to mask the speed gap, compiler writers are adding locality enhancing transformations to better utilize complex memory hierarchies, and applications programmers ar... View full abstract»

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  • Reducing data access penalty using intelligent opcode-driven cache prefetching

    Publication Year: 1995, Page(s):512 - 517
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    In the latest processor architectures such as IBM PowerPC and HP Precision Architecture (PA), it is found that certain important compound opcodes such as LOAD-UPDATE and LOAD-MODIFY contain accurate information about how data will be referenced in the near future. Furthermore, these opcodes have been fully utilized by the compiler in the program code generation. With the migration of data cache on... View full abstract»

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  • Write buffer design for cache-coherent shared-memory multiprocessors

    Publication Year: 1995, Page(s):506 - 511
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    We evaluate the performance impact of two different write-buffer configurations (one word per buffer entry and one block per buffer entry) and two different write policies (write-through and write-back), when using the partial block invalidation coherence mechanism in a shared-memory multiprocessor. Using an execution-driven simulator, we find that the one word per entry buffer configuration with ... View full abstract»

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  • Multi-dimensional interleaving for time-and-memory design optimization

    Publication Year: 1995, Page(s):440 - 445
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper presents a novel optimization technique for the design of application specific integrated circuits dedicated to perform iterative or recursive time-critical sections of multi-dimensional problems, such as image processing applications. These sections are modeled as cyclic multi-dimensional data flow graphs (MDFGs). This new technique, called multi-dimensional interleaving consists of an... View full abstract»

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  • A coprocessor for accurate and reliable numerical computations

    Publication Year: 1995, Page(s):686 - 691
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    This paper presents the architecture and hardware design of a special-purpose coprocessor that performs variable-precision, interval arithmetic. Variable-precision arithmetic allows the precision of the computation to be specified, based on the problem to be solved and the required accuracy of the results. Interval arithmetic produces two values for each result, such that the true result is guaran... View full abstract»

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  • Asynchronous 2-D discrete cosine transform core processor

    Publication Year: 1995, Page(s):380 - 385
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    To lend additional insight into the reality of self-timed design, this paper proposes a large-scale, application specific, asynchronous design-a CCITT compatible asynchronous DCT/IDCT processor. The prototype DCT/IDCT processor uses two-phase transition signaling and a bounded delay approach to implement a modified version of Sutherland's micropipeline. The layout of the core processor was designe... View full abstract»

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  • VLSI issues in memory-system design for video signal processors

    Publication Year: 1995, Page(s):498 - 503
    Cited by:  Papers (4)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    This paper addresses the design of memory-system architectures for video signal processors. The memory subsystem is the bottleneck of most video computing systems and demands a careful analysis of the design tradeoffs related to area, cycle time, and utilization. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture, particularly that o... View full abstract»

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  • DART: delay and routability driven technology mapping for LUT based FPGAs

    Publication Year: 1995, Page(s):409 - 414
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    A two-phased approach for routability directed delay-optimal mapping of LUT based FPGAs is presented based on the results of stochastic routability analysis. First, delay-optimal mapping is performed which simultaneously minimizes area and delay. Then, the mapped circuits are restructured to alleviate the potential routing congestions. Experimental results indicate that the first phase creates des... View full abstract»

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  • Analysis of conditional resource sharing using a guard-based control representation

    Publication Year: 1995, Page(s):434 - 439
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of throughput is desired. In this paper, an exact and efficient conditional resource sharing analysis using a guardbased control representation is presented. The analysis is transparent to a scheduler implementation. The proposed te... View full abstract»

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  • EPNR: an energy-efficient automated layout synthesis package

    Publication Year: 1995, Page(s):224 - 229
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    This paper reports our experiences with incorporating energy (or switched capacitance) based algorithms into an automated layout synthesis system based on standard cells. Our experimental results show an average savings of 18.5% in interconnect energy at a cost of about 6.2% area increase relative to area-minimized layouts on MCNC Logic Synthesis '93 benchmarks. The basic premise is that the wires... View full abstract»

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  • Efficient testability enhancement for combinational circuit

    Publication Year: 1995, Page(s):168 - 172
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    We propose a novel testability enhancement scheme based on XOR Chain Structure. The structure is effective for improving both controllability and observability. The insertion points are selected by fast testability analysis and random pattern resistant node source tracking. Experiments with ISCAS85 benchmark circuits show that the scheme is effective. The incurred hardware overhead and performance... View full abstract»

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  • Concurrent timing optimization of latch-based digital systems

    Publication Year: 1995, Page(s):680 - 685
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    Many techniques have been proposed to optimize digital system timing. Each technique can be advantageous in particular applications, however they are most often applied individually rather than concurrently. The framework presented here allows for concurrent timing optimization using retiming, intentional clock skew, and wave pipelining for latch-based designed systems with single or multi-phase c... View full abstract»

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  • FPGA global routing based on a new congestion metric

    Publication Year: 1995, Page(s):372 - 378
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    Unlike traditional ASIC routing, the feasibility of routing in FPGAs is constrained not only by the available space within a routing region, but also by the routing capacity of a switch block. Recent work has established the switch-block capacity as a superior congestion-control metric for FPGA global routing. However, the work has two deficiencies: (1) its algorithm for computing the switch-block... View full abstract»

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  • VLSI design of densely-connected array processors

    Publication Year: 1995, Page(s):492 - 497
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Paralleled array processors based on cellular neural networks (CNNs) are very useful in high-speed, real-time signal and image processing because of its simplicity for problem mapping and high potential computational bandwidth. Local interconnection and simple synaptic operators are the most attractive features of the cellular neural network (CNN) for VLSI implementation. A computing architecture ... View full abstract»

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  • Performance assessment of embedded Hw/Sw systems

    Publication Year: 1995, Page(s):52 - 57
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    Performance assessment of embedded Hw/Sw systems built with various types of VLSI components, i.e. heterogeneous multi-processor architectures, is important to help the development of complex real-time applications. To design such a tool, two issues are to be solved, relevant information gathered simultaneously on several components without disturbing the application behavior, and the display of t... View full abstract»

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  • Simultaneous area and delay minimum K-LUT mapping for K-exact networks

    Publication Year: 1995, Page(s):402 - 408
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    We address the technology mapping problem for lookup table FPGAs. The area minimization problem for mapping K-bounded networks, consisting of nodes with at most K inputs using K-input lookup tables is known to be NP-complete for K⩾5. The complexity was unknown for K=2, 3, and 4. The corresponding delay minimization problem (under the constant delay model) was solved in polynomial time by the f... View full abstract»

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  • Multiprocessor design verification for the PowerPC 620 microprocessor

    Publication Year: 1995, Page(s):188 - 195
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    Multiprocessor design verification for the PowerPC 620 microprocessor was challenging due to the 620 Bus protocol complexity. The highly concurrent bus and level 2 (LS) cache interfaces, and the extensive system configurability. In order to verify this functionality, a combination of random and deterministic approaches were used. The Random Test Program Generator (RTPG) and the newly developed Sto... View full abstract»

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  • Incas: a cycle accurate model of UltraSPARC

    Publication Year: 1995, Page(s):130 - 135
    Cited by:  Papers (6)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    This paper describes a cycle accurate model of the UltraSPARC processor. The model is written in C++, and is built on top of a powerful programming framework with a built-in message-passing mechanism and a timing discipline for simulating concurrent modules. The goal was to help verify the processor by cross checking the RTL model at run time, as well as to provide accurate performance estimates. ... View full abstract»

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  • Adaptive routing in Clos networks

    Publication Year: 1995, Page(s):266 - 270
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    We describe a method of controlling a three-stage Clos nonblocking switch where “speculative” self-routing over the Clos fabric is augmented with reservations over a control network that connects controllers in the input and output stages of the switch. The effect is that most connections succeed over the speculative path while those subject to contention are processed over the control... View full abstract»

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  • Thermal placement for high-performance multichip modules

    Publication Year: 1995, Page(s):218 - 223
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A placement scheme that considers both electrical performance requirements and thermal behavior for the high-performance multichip modules is described in this paper. Practical thermal models are used for placement of high-speed chips in multichip module packages under two different cooling environments: conduction cooling and convection cooling. Placement methods are modified to optimize conventi... View full abstract»

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