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Test Conference, 1995. Proceedings., International

Date 21-25 Oct. 1995

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Displaying Results 1 - 25 of 137
  • Proceedings of 1995 IEEE International Test Conference (ITC)

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    Freely Available from IEEE
  • Author index

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    Freely Available from IEEE
  • Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits

    Page(s): 683 - 692
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    In this work, we present a new approach for the pseudo-exhaustive BIST of synchronous sequential circuits. We first give a characterization of the flip-flops that cause the unbalanced structure of the acyclic circuit using peripheral retiming techniques, and, consequently, both logic optimization and balancing problem are considered and solved in the same phase. Second, the balancing solution is considered as a first step of the partitioning problem. For the remaining balanced circuit, the segmentation edges are selected such that there is a retiming minimizing the number of segmentation cells in the retimed circuit. Experimental results show that our approach significantly reduces the hardware overhead relative to the existing approaches View full abstract»

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  • User application of statistical process monitor techniques to ASIC critical parameters

    Page(s): 233 - 241
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    The collection of meaningful data is important in understanding sources of variation in the IC manufacturing process, leading to continuous improvement and thus reduced variation and waste. The results of applying SPM to 5 ASICs revealed the following: (1) The IC manufacturing processes based on the process parameters that were measured are reasonably well controlled and capable. Several parameters (Ratio P/N and P/N Strength) exhibited process shifts for early lots of devices received but settled-down in subsequent lots. (2) The process models accurately reflect the process. (3) The design model/library matches the process. There is good correlation between (a) fault coverage based on the SSAF model and the defective ppm levels measured at 100% incoming inspection test and, (b) SPM data taken and 100% incoming functional test results. (5) Due to the small process variation and low ppm levels incurred at incoming inspection test, it was decided to: (a) reduce the critical parameter sample size from 100 to 18 and, (b) reduce 100% functional incoming inspection testing of each lot to skip lot testing (100% of each fifth lot). There was no significant discernible difference between the results from 100 sample lot size SPM tests and 18 sample size SPM tests View full abstract»

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  • Integration of IEEE STD.11149.1 and mixed-signal test architectures

    Page(s): 569 - 576
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    It is shown that the TMS pin of IEEE Std. 1149.1 can also be-used for providing stimulus during analog measurements using the architectures of [Park93] and [Lu94]. This results in the saving of one test pin for these architectures. Simulation results show that mixed-signal testing can be safely performed using the new approach without compromising the effectiveness of the approaches of [Park93] and [Lu94] View full abstract»

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  • A secure data transmission scheme for 1149.1 backplane test bus

    Page(s): 789 - 796
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    The four (five) wires defined in IEEE Std 1149.1 can be extended to the backplane to form a test bus that provides a linkage between 1149.1 boards and the backplane environment. This test architecture has many advantages. However, one of the disadvantages is its inability to detect errors that may occur during backplane data transmission and to protect the boards-under-test from unsafe corrupted data. In this paper, we propose a novel scheme to address these issues. The concept is first described, then followed by implementation examples. As a result of its simplicity and flexibility, the proposed scheme can be implemented in different ways to suit specific application needs View full abstract»

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  • Two new techniques for identifying opens on printed circuit boards: analog junction test, and radio frequency induction test

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    The author describes the principles, implementation, strengths, weaknesses and applications of two vectorless test techniques developed by Teradyne. Examples drawn from users' experience demonstrate how unpowered testing can dramatically reduce test cost and cycle time while maintaining or improving fault coverage. Analog junction test (AJT) and RF induction test (RFIT) form part of Teradyne's vectorless test toolset. AJT uses simple analog characterization of pin pairs on the device, relying on the protection or parasitic diode in most devices to produce the signal that indicates correct board assembly. RFIT uses RF induction into the device-under-test from an overhead inducer. Detection of the induced AC signal on the device pins via the standard bed-of-nails fixture indicates good board assembly. Both AJT and RFIT offer entirely new capability to the test engineer in that they can detect resistive cold solder joints. These faults would otherwise pass a traditional vector test or even a functional test, while risking field failures View full abstract»

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  • An efficient and economic partitioning approach for testability

    Page(s): 403 - 412
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    This paper presents an RT level partitioning approach for sequential circuits described as data path and control part. The data path of a circuit is partitioned at some hard-to-test points detected by an RT level testability analysis algorithm. These points are then made directly accessible by DFT techniques. The control part is also modified to control the circuit in normal mode and test mode. In the normal mode, the circuit is controlled to perform its function, while in the test mode, all partitions are controlled independently. As a result, test quality is improved by independent test generation and test application for every partition. The partitioning complexity is reduced by the use of testability analysis results and the area overhead is lower than that of full scan designs for most benchmarks we used. Experiments show results of the approach as compared with no scan, partial scan and full scan schemes View full abstract»

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  • High-level test generation using symbolic scheduling

    Page(s): 586 - 595
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    A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74 X-series, ISCAS-85 and ISCAS-89 circuits. SWIFT produces test sequences that cover all gate-level stuck-at-faults. Surprisingly, although they are derived from a high-level functional description of the circuit under test, most of these test sequences are of provably minimal or near-minimal size View full abstract»

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  • Production IDDQ testing with passive current compensation

    Page(s): 490 - 497
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    In an ideal world, all test vectors selected as IDDQ test vectors would have very low measurement current. In many circumstances, however, a complete set of tests cannot be defined when relying on zero-current considerations. IDDQ test vectors selected from existing test sets must be capable of compensating for passive currents. The identification of valid test vectors, and the magnitude of the passive current, can be predicted in the ASIC environment via macrocell-specific information. This paper presents one methodology to support this test generation using digital simulation, including the selection of multiple IDDQ test vectors View full abstract»

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  • Low-complexity fault simulation under the multiple observation time testing approach

    Page(s): 272 - 281
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    The use of three-value logic for fault simulation of synchronous sequential circuits may incur a loss of accuracy that would cause the fault coverage to be underestimated. In addition, loss of fault coverage may occur due to the test strategy employed. These problems were previously alleviated at the cost of high computational complexity. We present an observation that allows us to alleviate loss of fault coverage in many cases, at a computational cost similar to conventional three-value fault simulation. The proposed simulation procedure is compared to a previously proposed one to demonstrate its effectiveness View full abstract»

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  • Is high level test synthesis just design for test?

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    High level synthesis (HLS) is defined as a topdown translation from the behavioral domain to the structural domain where the circuit is represented by a set of connected storage elements and functional units for the datapath and a logic level specification of the corresponding control unit. Testing is a bottom up approach process aiming at detecting realistic faults. Realistic faults depend on the physical domain, the technology process data and on the geometry of inner structures (inductive fault analysis). HLS cannot solve all the testing problems, but it may facilitate solutions by providing easier control or observation of internal units. Furthermore, the so produced designs exhibit less area and speed penalties than those obtained by applying a posteriori DFT techniques on synthetized gate level descriptions View full abstract»

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  • A comparative analysis of input stimuli for testing mixed-signal LSIs based on current testing

    Page(s): 71 - 77
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    This paper describes the comparison of input stimuli as a means of testing mixed-signal circuits. Current testing that measures the integral of the power supply current in the time-domain is used to detect faults. The main objective is to achieve real-time testing in which there is no need to analyze the results of testing. Simulation results show that a step-voltage input stimulus is effective for detection of bridging and breaking faults in an A/D converter. Since this input signal allows the current to be measured at discrete time intervals, it is applicable for real-time current testing and can be used for built-in test and production test View full abstract»

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  • High-performance circuit testing with slow-speed testers

    Page(s): 302 - 310
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    We propose a method of testing high-speed digital devices whose clock frequency exceeds the capability of the test equipment. The circuit is designed such that a controllable delay is introduced in the timing paths during test. With the added delay, the maximum operating frequency is lowered to a rate which is within the capability of the ATE. The delay circuit is so designed that its function is also testable. In an illustrative design with single clock, the controllable delay is incorporated within a master-slave flip-flop. The control of delay is then achieved by manipulation of the duty-cycle of the clock waveform. In a two-clock system, no modification of the flip-flop is required and the delay is varied by skewing one clock signal with respect to the other View full abstract»

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  • Capacitive leadframe testing

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    Pin-level diagnosis of open solder joints allows manufacturers to tune SMT process for maximum output. Repair time and repair-induced damage are both significantly reduced with pin-level diagnostics. Detection of misoriented capacitors prevents expensive and reputation-damaging field failures. Ability to test both sides of PCB's allows maximum fault coverage View full abstract»

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  • A new method for partial scan design based on propagation and justification requirements of faults

    Page(s): 413 - 422
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    Scan design can be viewed as scanning flip-flops, so that faults, otherwise aborted, are detected by meeting propagation and justification requirements. In this paper, we propose a new method which identifies justification and propagation requirements of aborted faults through combinational test generation and selects flip-flops to meet the requirements. Two procedures, optimal and heuristic, were considered in the process. We implemented the heuristic procedure in a program called BELLONA. BELLONA selects flip-flops progressively to lead to high fault efficiency. Our experimental results show that BELLONA achieves 100% fault efficiency for all circuits experimented with, on average, 19% of flip-flops selected View full abstract»

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  • A gate-array-based 666 MHz VLSI test system

    Page(s): 451 - 458
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    A 666 MHz VLSI test system with a dedicated memory test pattern generator was developed. A loose-timing data transfer scheme was employed for better integration of a shared-resource unit into the per-pin tester-architecture, Timing control resolution of 12.5 ps was achieved within a normal framework of a gate array LSI. A simple and low-cost timing calibration-technique was developed to offer accurate test timings. Parallel operation of the memory test pattern generators was used to realize a non-interrupted pattern generation at the maximum speed View full abstract»

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  • End-to-end performance measurement for interactive multimedia television

    Page(s): 979 - 985
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    A system which measures the throughput and latency of ADSL-based interactive video delivery systems has been designed and deployed in a Northern Virginia market trial. In addition to providing quantitative analysis of the Set Top Box, video dial tone signalling subnetwork, and video server system performance, the experiences yielded insight into the design of equipment for deployment at both the headed and customer premises View full abstract»

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  • Cost-effective system-level test strategies

    Page(s): 807 - 813
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    This paper describes a system level test strategy planning process. The key factors are described using strategy templates. Analyses of relative costs indicate that a test strategy may have a limited range of applications View full abstract»

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  • Test generation and design for test for a large multiprocessing DSP

    Page(s): 149 - 156
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    The TMS320C80 is a programmable, parallel processing DSP. The test approach was an engineering mix of design for testability, test view creation, and verification. This mixture facilitated timely test generation and had other important benefits. We document the overall test methodology and the benefits derived therein View full abstract»

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  • Hierarchical functional fault simulation for high-level synthesis

    Page(s): 596 - 605
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    A novel highly efficient fault simulation technique targeted for circuits produced through high-level synthesis is presented. The technique combines hierarchical and functional fault simulation of commonly used building blocks that have regular structures. Comparison with gate-level simulation demonstrates the advantage of using this technique for this class of circuits View full abstract»

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  • On efficiently and reliably achieving low defective part levels

    Page(s): 616 - 625
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    How can we guarantee that a testing method will stably and efficiently achieve a very low defective part level? Traditional testing methods rely upon faults to model all defects. As technology advances, this approach becomes increasingly questionable. If only a subset of defects are modeled as faults, then as fault coverage approaches 100%, the tests mill be more and more biased in favor of fault detection. Unfortunately, this reduces the testing efficiency for defects and limits the quality level that we can achieve. In this paper, we propose models for the testing process and suggest a solution which we call “unbiased test generation”. We define two types of testing bias, and these new metrics can be used to compare and evaluate test generation methods in practice View full abstract»

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  • On combining design for testability techniques

    Page(s): 423 - 429
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    In this paper, we present a testability-based method to combine three different DFT techniques: partial reset, partial observation, and partial scan. This approach combines the complementary strengths of the DFT techniques taking advantage of their different cost/benefit trade-offs, and results in more testable circuits with reduced design penalty View full abstract»

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  • Performance driven BIST technique for random logic

    Page(s): 524 - 533
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    Performance degradation due to insertion of BIST logic into high-speed designs has been analyzed. A framework to introduce BIST into random logic circuits, without causing timing violations has been proposed. Various heuristics for selecting flip-flops for BIST have been developed and studied in detail. Experimental results indicate an improvement in performance while optimizing fault coverage and area overhead View full abstract»

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  • Arbitrary-precision signal generation for bandlimited mixed-signal testing

    Page(s): 78 - 86
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    This paper presents significant improvements in the generation of analog signals for on-chip analog circuit testing. In particular the novel oscillators proposed here can achieve signal-to-noise ratios far greater than previous designs, while remaining area-efficient. One particular example illustrates a 30 dB improvement in the SNR. Alternatively, signals can be generated with the same SNR as with older designs but over a wider range of frequencies. Multitone signal generation is enhanced in the same fashion. Prototypes were built and satisfactorily tested on FPGA technology View full abstract»

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