Proceedings of 1995 IEEE International Test Conference (ITC)

21-25 Oct. 1995

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  • Proceedings of 1995 IEEE International Test Conference (ITC)

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (622 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (155 KB)
    Freely Available from IEEE
  • Evaluating waveform generation capabilities of VLSI test systems

    Publication Year: 1995, Page(s):469 - 478
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    This paper presents a means of evaluating the waveform generation capabilities of VLSI test systems. It presents a series of equations that can be used to determine the maximum frequency at which a timing system can produce a specific set of waveforms as a function of that timing system's capabilities and restrictions View full abstract»

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  • SiProbe-a new technology for wafer probing

    Publication Year: 1995, Page(s):106 - 112
    Cited by:  Papers (2)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    This paper will describe a new wafer probing technology that is particularly applicable to the simultaneous probing of multiple die and high pin-count devices that cannot be probed using conventional needle probing cards. Inherent in the design of this product is the capability for high density area array probing at grid densities as high as 50×150 microns and at probe pointing accuracies ap... View full abstract»

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  • STIL from the users perspective

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    The author discusses the strong motivations for a standard test language. The capabilities of the Standard Test Interface Language (STIL) are examined and compared with other test standards which go too far into additional aspects of test View full abstract»

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  • A low-cost high-performance CMOS timing vernier for ATE

    Publication Year: 1995, Page(s):459 - 468
    Cited by:  Papers (4)  |  Patents (83)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    Current conditions within the test industry impose a difficult combination of design requirements for the next generation of General Purpose Automatic Test Equipment: faster devices require higher tester bandwidth, higher data rates, and higher timing edge accuracy; yet, lower device selling prices and industry economics require lower ATE acquistion and maintenance costs. Emitter Coupled Logic (EC... View full abstract»

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  • A general purpose ATE based IDDQ measurement circuit

    Publication Year: 1995, Page(s):97 - 105
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    Previously published measurement circuits offered good solutions for measuring IDDQ on a fairly narrow range of part types. Most of these solutions have required adding circuitry either to the DUT board or to the DUT itself. In this paper we describe a general purpose, ATE Pin Electronics Card based, IDDQ measurement circuit. It gives good results over a very wide range of de... View full abstract»

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  • Required-a portable test standard

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    The need exists today to define a portable test strategy that encompasses the testing of all phases of a product's life cycle. Using a combination of new and existing standards, a family of standards could be developed to meet the industry's need View full abstract»

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  • A gate-array-based 666 MHz VLSI test system

    Publication Year: 1995, Page(s):451 - 458
    Cited by:  Papers (2)  |  Patents (59)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    A 666 MHz VLSI test system with a dedicated memory test pattern generator was developed. A loose-timing data transfer scheme was employed for better integration of a shared-resource unit into the per-pin tester-architecture, Timing control resolution of 12.5 ps was achieved within a normal framework of a gate array LSI. A simple and low-cost timing calibration-technique was developed to offer accu... View full abstract»

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  • Visualizing quality

    Publication Year: 1995, Page(s):87 - 96
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    ATE systems have many instruments with many ranges. System quality is difficult to manage. Two visualization algorithms for viewing system instrument stabilities are described. A previously derived traceability algorithm is enhanced. Typical results are described View full abstract»

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  • Optimal space compaction of test responses

    Publication Year: 1995, Page(s):834 - 843
    Cited by:  Papers (19)  |  Patents (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (856 KB)

    Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q≪k, a process termed space compaction. The effectiveness of a compaction method can be measured by its compaction ratio c=k/q. However, a high compaction ratio can introduce aliasing, which occurs when a faulty test response maps to the fault-free signature. We investigat... View full abstract»

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  • Electrical troubleshooting, diagnostics, and repair of multichip modules

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    Discusses techniques for detecting and diagnosing interconnect faults in MCM substrates. The methods use stimuli to measure the attenuation and phase variations resulting from interconnect defects such as opens, shorts and high resistance connections. The processes are compared to alternative techniques and provide better resolution in resistance measurement View full abstract»

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  • High-performance circuit testing with slow-speed testers

    Publication Year: 1995, Page(s):302 - 310
    Cited by:  Papers (33)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    We propose a method of testing high-speed digital devices whose clock frequency exceeds the capability of the test equipment. The circuit is designed such that a controllable delay is introduced in the timing paths during test. With the added delay, the maximum operating frequency is lowered to a rate which is within the capability of the ATE. The delay circuit is so designed that its function is ... View full abstract»

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  • Automated 1.5 GHz SONET characterization

    Publication Year: 1995, Page(s):957 - 965
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    While functional, D.C. parametric and limited at-speed testing of integrated circuits is typically done on commercially available test systems, these systems are not rated for SONET frequencies and do not lend themselves well to product characterization. This paper describes a test methodology and system designed specifically to address at-speed SONET characterization requirements View full abstract»

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  • The P1149.4 Mixed Signal Test Bus: costs and benefits

    Publication Year: 1995, Page(s):444 - 450
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper summarizes key elements of the proposed IEEE P1149.4 Mixed-Signal Test Bus Standard, examines costs and benefits in detail, and includes specific circuit examples. The significant costs are silicon area and pins. Benefits include test cost reduction, diagnosability, and unique capabilities. Changes proposed since ITC'93 and areas of controversy are noted for this un-released standard View full abstract»

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  • The many faces of test synthesis

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    One of the problems of the use of the term “test synthesis” is that it is so general that almost any aspect of test automation can be claimed to fall under its umbrella. Because of the popularity of the term, and the unpopularity (particularly with CAD vendors) of having a system which does NQT carry out test synthesis, it is tempting to interpret the term as something equivalent to &l... View full abstract»

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  • Arbitrary-precision signal generation for bandlimited mixed-signal testing

    Publication Year: 1995, Page(s):78 - 86
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    This paper presents significant improvements in the generation of analog signals for on-chip analog circuit testing. In particular the novel oscillators proposed here can achieve signal-to-noise ratios far greater than previous designs, while remaining area-efficient. One particular example illustrates a 30 dB improvement in the SNR. Alternatively, signals can be generated with the same SNR as wit... View full abstract»

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  • Exact aliasing computation for RAM BIST

    Publication Year: 1995, Page(s):13 - 22
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    In this paper we illustrate that exact aliasing computation in RAM BIST can be achieved with respect to accurate RAM fault models including single and multiple stuck-at, transition and coupling cell-array faults and decoder stuck-at faults View full abstract»

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  • An effective BIST scheme for Booth multipliers

    Publication Year: 1995, Page(s):824 - 833
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    Booth multipliers are widely used in both general purpose datapath structures and specialized Digital Signal Processors. Such multipliers when embedded in complex ICs have low controllability and observability, so the use of a suitable BIST scheme is a necessity. No Such BIST schemes for Booth multipliers are available to our knowledge in the open literature. A very effective BIST scheme for Booth... View full abstract»

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  • Report on a pilot project successfully implementing a design-to-test methodology

    Publication Year: 1995, Page(s):771 - 780
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    Concurrent development of new device designs and test packages is recognized as essential to bringing new products to market faster This paper describes a series of software tools which, when used in concert, make implementation of this methodology feasible. The paper also reports on a pilot project that successfully used this implementation on a new device design and test package. An analysis of ... View full abstract»

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  • Solving known good die (and substrate) test issues

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    A qualification process for MCM technologies used in military applications does not exist. The opportunities for failure resulting from material interactions in MCM's will remain if an understanding of failure mechanisms is not taken into account. For example, corrosion and stress voiding (cracking) of metal and interlayer materials is a concern for ICs in a stockpile. More research needs to be co... View full abstract»

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  • Improving DSP-based measurements with spectral interpolation

    Publication Year: 1995, Page(s):355 - 363
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    Spectral interpolation is a simple mathematical process that removes certain types of non-coherent interference from coherent DSP-based measurements. A common example of non-coherent interference is exponential decay resulting from inadequate settling time in an AC-coupled measurement. Asynchronous 60 Hz power hum is another common example familiar to test and measurement professionals. Either typ... View full abstract»

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  • Test quality: required stuck-at fault coverage with the use of I DDQ testing

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    Users of integrated circuits requiring very high quality are forced to generate specifications that contain quality metrics that are universally understood and applied by all the suppliers of integrated circuits. Stuck-at fault coverage has been classically used as such a metric. However, innumerable reports question the validity of the SAF model as the best metric for insuring CMOS circuit qualit... View full abstract»

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  • Testing a switching memory in a telecommunication system

    Publication Year: 1995, Page(s):947 - 956
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    The paper describes the approach followed for testing a real circuit produced by Italtel. Both on-line and off-line testing are considered and the performance and area overheads are taken into account to meet the constraints imposed by the circuit customers. BIST is adopted to test some embedded memories, and boundary scan is exploited to activate the test and gather the results. Particular care i... View full abstract»

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  • Inductive contamination analysis (ICA) with SRAM application

    Publication Year: 1995, Page(s):552 - 560
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1288 KB)

    This paper proposes a new simulation-based fault modeling methodology. The methodology-an extension of Inductive Fault Analysis-uses the contamination-defect-fault simulator CODEF to directly relate effects of process-induced contamination to circuit-level malfunctions. The application of this methodology (called Inductive Contamination Analysis) is demonstrated by development of SRAM fault models View full abstract»

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