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Test Conference, 1995. Proceedings., International

Date 21-25 Oct. 1995

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Displaying Results 1 - 25 of 137
  • Proceedings of 1995 IEEE International Test Conference (ITC)

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (622 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (155 KB)
    Freely Available from IEEE
  • Exact aliasing computation for RAM BIST

    Publication Year: 1995, Page(s):13 - 22
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    In this paper we illustrate that exact aliasing computation in RAM BIST can be achieved with respect to accurate RAM fault models including single and multiple stuck-at, transition and coupling cell-array faults and decoder stuck-at faults View full abstract»

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  • DFT & ATPG: together again

    Publication Year: 1995, Page(s):262 - 271
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    A system which adds DFT and generates test vectors for the enhanced circuit is described. Partial reset, observability enhancement and partial scan are employed. A dynamic partial reset flip-flop selection method is described utilizing a fast genetic algorithm based sequential test generator. This system trades off various parameters to obtain high fault coverage, low test application times, low h... View full abstract»

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  • Coping with re-usability using sequential ATPG: a practical case study

    Publication Year: 1995, Page(s):252 - 261
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    To be able to manage increasing chip complexity, the re-use of already designed functional modules has become a standard design practise in state-of-the-art ASIC design. In this paper, the impact of these re-used modules on the testability of the entire chip has been investigated. For this purpose, a complex telecom ASIC with re-used interface logic running at 155 MHz, used in an ATM (Asynchronous... View full abstract»

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  • Optimizing product profitability-the test way

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    The competitive drive to reduce product development costs has led to a surge of interest in test methods that attempt to reduce costs. However, reducing test costs may not always result in the lowest product costs. Rather than attempting to reduce test costs as much as possible, the goal should be to maximize product profitability by finding the optimum test strategy that results in the quality le... View full abstract»

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  • MCM quality and cost analysis using economics models

    Publication Year: 1995, Page(s):430 - 437
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    This paper presents an economics modelling tool for the analysis of MCM test and known good die strategies. The model calculates actual financial cost in parallel with quality at each stage from die manufacture to MCM assembly, test and rework, resulting in a powerful predictive tool for the evaluation of MCM test strategies. The spectrum of possible analyses which can be performed ranges from the... View full abstract»

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  • High-performance circuit testing with slow-speed testers

    Publication Year: 1995, Page(s):302 - 310
    Cited by:  Papers (32)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    We propose a method of testing high-speed digital devices whose clock frequency exceeds the capability of the test equipment. The circuit is designed such that a controllable delay is introduced in the timing paths during test. With the added delay, the maximum operating frequency is lowered to a rate which is within the capability of the ATE. The delay circuit is so designed that its function is ... View full abstract»

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  • A test data collection system for uniform data analysis

    Publication Year: 1995, Page(s):242 - 251
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    This paper describes a system that concentrates on data collection to provide uniform data analysis. The result is an integrated data collection and analysis system designed for semiconductor manufacturers. It includes automatic data insertion programs using distributed databases for data storage. It has a statistical analysis package designed with a graphical user interface. The system provides d... View full abstract»

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  • Cutting the cost of test; the value-added way

    Publication Year: 1995
    Cited by:  Papers (2)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    Given some level of test capability requirement, there are ways to reduce the cost of providing that test capability in the overall life-cycle. One guiding principle to improving efficiency and reducing cost is to fulfil the test requirement as close to the expertise as possible. A more difficult thing to implement is the treatment of the test elements of a product as a value-added process. Here, ... View full abstract»

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  • On combining design for testability techniques

    Publication Year: 1995, Page(s):423 - 429
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    In this paper, we present a testability-based method to combine three different DFT techniques: partial reset, partial observation, and partial scan. This approach combines the complementary strengths of the DFT techniques taking advantage of their different cost/benefit trade-offs, and results in more testable circuits with reduced design penalty View full abstract»

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  • The many faces of test synthesis

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    One of the problems of the use of the term “test synthesis” is that it is so general that almost any aspect of test automation can be claimed to fall under its umbrella. Because of the popularity of the term, and the unpopularity (particularly with CAD vendors) of having a system which does NQT carry out test synthesis, it is tempting to interpret the term as something equivalent to &l... View full abstract»

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  • Test quality: required stuck-at fault coverage with the use of I DDQ testing

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    Users of integrated circuits requiring very high quality are forced to generate specifications that contain quality metrics that are universally understood and applied by all the suppliers of integrated circuits. Stuck-at fault coverage has been classically used as such a metric. However, innumerable reports question the validity of the SAF model as the best metric for insuring CMOS circuit qualit... View full abstract»

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  • User application of statistical process monitor techniques to ASIC critical parameters

    Publication Year: 1995, Page(s):233 - 241
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The collection of meaningful data is important in understanding sources of variation in the IC manufacturing process, leading to continuous improvement and thus reduced variation and waste. The results of applying SPM to 5 ASICs revealed the following: (1) The IC manufacturing processes based on the process parameters that were measured are reasonably well controlled and capable. Several parameter... View full abstract»

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  • Visualizing quality

    Publication Year: 1995, Page(s):87 - 96
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    ATE systems have many instruments with many ranges. System quality is difficult to manage. Two visualization algorithms for viewing system instrument stabilities are described. A previously derived traceability algorithm is enhanced. Typical results are described View full abstract»

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  • Testing a switching memory in a telecommunication system

    Publication Year: 1995, Page(s):947 - 956
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    The paper describes the approach followed for testing a real circuit produced by Italtel. Both on-line and off-line testing are considered and the performance and area overheads are taken into account to meet the constraints imposed by the circuit customers. BIST is adopted to test some embedded memories, and boundary scan is exploited to activate the test and gather the results. Particular care i... View full abstract»

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  • It's DFT, boundary scan and life cycle benefits

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    Testing is a necessary, but non-value-added operation. Test methods that are internal, and can reduce the capital required to produce a specified level of quality will be critical to reducing the cost of test. As such, methods such as internal scan, boundary scan, and BIST will reduce the requirements for capital intensive external test equipment, and evidence and experience have shown can reduce ... View full abstract»

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  • A gate-array-based 666 MHz VLSI test system

    Publication Year: 1995, Page(s):451 - 458
    Cited by:  Papers (2)  |  Patents (59)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    A 666 MHz VLSI test system with a dedicated memory test pattern generator was developed. A loose-timing data transfer scheme was employed for better integration of a shared-resource unit into the per-pin tester-architecture, Timing control resolution of 12.5 ps was achieved within a normal framework of a gate array LSI. A simple and low-cost timing calibration-technique was developed to offer accu... View full abstract»

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  • Supplying known good die for MCM applications using low cost embedded testing

    Publication Year: 1995, Page(s):328 - 335
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    A ready supply of high quality Known Good Die (KGD) is essential for obtaining acceptable Multi-Chip Module (MCM) yields and reducing costs. Unfortunately, the testers needed for testing and screening VLSI chips to supply high quality KGD are quite expensive, especially for high speed or high pin count ICs. In addition, there are issues connected with testing accuracy-the tester environment may li... View full abstract»

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  • Improving DSP-based measurements with spectral interpolation

    Publication Year: 1995, Page(s):355 - 363
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    Spectral interpolation is a simple mathematical process that removes certain types of non-coherent interference from coherent DSP-based measurements. A common example of non-coherent interference is exponential decay resulting from inadequate settling time in an AC-coupled measurement. Asynchronous 60 Hz power hum is another common example familiar to test and measurement professionals. Either typ... View full abstract»

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  • A new method for partial scan design based on propagation and justification requirements of faults

    Publication Year: 1995, Page(s):413 - 422
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    Scan design can be viewed as scanning flip-flops, so that faults, otherwise aborted, are detected by meeting propagation and justification requirements. In this paper, we propose a new method which identifies justification and propagation requirements of aborted faults through combinational test generation and selects flip-flops to meet the requirements. Two procedures, optimal and heuristic, were... View full abstract»

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  • Is high level test synthesis just design for test?

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    High level synthesis (HLS) is defined as a topdown translation from the behavioral domain to the structural domain where the circuit is represented by a set of connected storage elements and functional units for the datapath and a logic level specification of the corresponding control unit. Testing is a bottom up approach process aiming at detecting realistic faults. Realistic faults depend on the... View full abstract»

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  • The final barriers to widespread use of IDDQ testing

    Publication Year: 1995
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    IDDQ testing is required for high quality products. Several barriers to IDDQ testing have fallen. This is due to the rising importance of testing, quality, and CAD tool integration of design and test. Both theory and practice have demonstrated the value of IDDQ testing methodologies. Three key issues still hinder widespread utilization of IDDQ. The first... View full abstract»

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  • Inductive contamination analysis (ICA) with SRAM application

    Publication Year: 1995, Page(s):552 - 560
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1288 KB)

    This paper proposes a new simulation-based fault modeling methodology. The methodology-an extension of Inductive Fault Analysis-uses the contamination-defect-fault simulator CODEF to directly relate effects of process-induced contamination to circuit-level malfunctions. The application of this methodology (called Inductive Contamination Analysis) is demonstrated by development of SRAM fault models View full abstract»

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  • Test SPC: a process to improve test system integrity

    Publication Year: 1995, Page(s):224 - 232
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    A proposal to improve and control the final test of integrated circuits is presented. The objective is to improve the productivity of VLSI equipment by using a statistical process to reduce downtime and eliminate test escapes. Goals, developments, and implementation of this process are reviewed View full abstract»

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