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Proceedings of 1995 IEEE International Test Conference (ITC)

21-25 Oct. 1995

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Displaying Results 1 - 25 of 137
  • Proceedings of 1995 IEEE International Test Conference (ITC)

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (622 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (155 KB)
    Freely Available from IEEE
  • Software test data generation using the chaining approach

    Publication Year: 1995, Page(s):703 - 709
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    Software testing, specifically, test data generation is very labor-intensive and expensive. As a result, it accounts for a significant portion of software system development cost. In this paper we present a chaining approach for automated software test data generation. The chaining approach uses data dependence analysis to guide the test data generation process. The experiments have shown that the... View full abstract»

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  • Test synthesis in the behavioral domain

    Publication Year: 1995, Page(s):693 - 702
    Cited by:  Papers (29)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    A method for test synthesis in the behavioral domain is described. The approach is based on the addition of test behavior, which is the behavior of the design in test mode. The normal-mode design behavior and test-mode test behavior are combined and synthesized together to produce a testable design with inserted BIST structures. Derivation of an appropriate test behavior uses analysis based on met... View full abstract»

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  • Report on a pilot project successfully implementing a design-to-test methodology

    Publication Year: 1995, Page(s):771 - 780
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    Concurrent development of new device designs and test packages is recognized as essential to bringing new products to market faster This paper describes a series of software tools which, when used in concert, make implementation of this methodology feasible. The paper also reports on a pilot project that successfully used this implementation on a new device design and test package. An analysis of ... View full abstract»

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  • THD and SNR tests using the simplified Volterra series with adaptive algorithms

    Publication Year: 1995, Page(s):364 - 369
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    A test technique for the total harmonic distortion (THD) and signal to noise ratio (SNR) is proposed. A modified Volterra series using harmonics in place of powers of the sinusoidal input is used to model the nonlinear characteristic of the device under test (DUT). The least-mean square (LMS) adaptive algorithm is used to identify the DUT model. While maintaining comparable accuracy this technique... View full abstract»

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  • Development of an ATE test station for mixed CATV/TELCO products

    Publication Year: 1995, Page(s):966 - 972
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    This paper summarizes the development of a manufacturing ATE station for the testing of digital headend cable television (CATV) products, which utilize telecommunications transport protocols and RF pass-band architectures to deliver interactive video services View full abstract»

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  • Matching models to real life for defect reduction

    Publication Year: 1995, Page(s):217 - 223
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    This paper describes a method for quantitatively linking easily measurable parameters [defectivity in parts per million (PPM), test effectiveness (TE), failures in time rates (FIT)] with both customer and producer valued metrics. It describes a process by which test data derived from assembled printed circuit board (PCB) test and the determination of process capability are quantitatively linked. H... View full abstract»

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  • A new hardware fault insertion scheme for system diagnostics verification

    Publication Year: 1995, Page(s):994 - 1002
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    A new fault insertion method to help debug diagnostic software of telecommunications systems is described. The method makes use of boundary scan to inject multiple and un-correlated faults in a telecom system carrying traffic. Both hardware and software implementation aspects are discussed. The new method allows the use of structural test as part of diagnostics software to locate faults View full abstract»

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  • Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits

    Publication Year: 1995, Page(s):683 - 692
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    In this work, we present a new approach for the pseudo-exhaustive BIST of synchronous sequential circuits. We first give a characterization of the flip-flops that cause the unbalanced structure of the acyclic circuit using peripheral retiming techniques, and, consequently, both logic optimization and balancing problem are considered and solved in the same phase. Second, the balancing solution is c... View full abstract»

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  • It's DFT, boundary scan and life cycle benefits

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    Testing is a necessary, but non-value-added operation. Test methods that are internal, and can reduce the capital required to produce a specified level of quality will be critical to reducing the cost of test. As such, methods such as internal scan, boundary scan, and BIST will reduce the requirements for capital intensive external test equipment, and evidence and experience have shown can reduce ... View full abstract»

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  • A general purpose ATE based IDDQ measurement circuit

    Publication Year: 1995, Page(s):97 - 105
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    Previously published measurement circuits offered good solutions for measuring IDDQ on a fairly narrow range of part types. Most of these solutions have required adding circuitry either to the DUT board or to the DUT itself. In this paper we describe a general purpose, ATE Pin Electronics Card based, IDDQ measurement circuit. It gives good results over a very wide range of de... View full abstract»

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  • Dynamic test emulation for EDA-based mixed-signal test development automation

    Publication Year: 1995, Page(s):761 - 770
    Cited by:  Papers (6)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    This paper presents the analysis and development of an Electronic Design Automation (EDA)-based Test Development Automation (TDA) system. We explore the need for such a system and provide a real example of the system at work. The focus of the paper is the concept of dynamic test emulation which understands that a mixed-signal test often consists of obtaining information from a large number of meas... View full abstract»

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  • Improving DSP-based measurements with spectral interpolation

    Publication Year: 1995, Page(s):355 - 363
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    Spectral interpolation is a simple mathematical process that removes certain types of non-coherent interference from coherent DSP-based measurements. A common example of non-coherent interference is exponential decay resulting from inadequate settling time in an AC-coupled measurement. Asynchronous 60 Hz power hum is another common example familiar to test and measurement professionals. Either typ... View full abstract»

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  • An experimental chip to evaluate test techniques: chip and experiment design

    Publication Year: 1995, Page(s):653 - 662
    Cited by:  Papers (27)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25 k gate CMOS Test Chip has been designed, manufactured (5491 devices),and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs View full abstract»

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  • Automated 1.5 GHz SONET characterization

    Publication Year: 1995, Page(s):957 - 965
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    While functional, D.C. parametric and limited at-speed testing of integrated circuits is typically done on commercially available test systems, these systems are not rated for SONET frequencies and do not lend themselves well to product characterization. This paper describes a test methodology and system designed specifically to address at-speed SONET characterization requirements View full abstract»

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  • Distributed probabilistic diagnosis of MCMs on large area substrates

    Publication Year: 1995, Page(s):208 - 216
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    This paper addresses the issue of testing MCMs on large-area substrates. The cost of testing each MCM may be as high as 40% of the total manufacturing cost. It is critical that the test process be parallelized in order that multiple MCMs may be tested for the cost of testing one MCM. With this objective in mind, we propose a distributed probabilistic diagnosis algorithm for MCMs on large-area subs... View full abstract»

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  • Linking diagnostic software to hardware self test in telecom systems

    Publication Year: 1995, Page(s):986 - 993
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    A novel approach that links hardware structural testing to telecom system failure diagnostics software is presented. Issues related to accessing die hardware test features on the system are discussed and two access architectures are described. Linking the BIST to diagnostic software reduces the software complexity and at the same time increases the diagnostics accuracy. This technique has been imp... View full abstract»

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  • Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST

    Publication Year: 1995, Page(s):674 - 682
    Cited by:  Papers (49)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new technique for synthesizing combinational mapping logic to transform the set of patterns that are generated. The goal is to satisfy test length and fault coverage requirements while minimizing area overhead. For a given ps... View full abstract»

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  • STIL from the users perspective

    Publication Year: 1995
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    The author discusses the strong motivations for a standard test language. The capabilities of the Standard Test Interface Language (STIL) are examined and compared with other test standards which go too far into additional aspects of test View full abstract»

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  • Avoiding unknown states when scanning mutually exclusive latches

    Publication Year: 1995, Page(s):311 - 318
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Many modern circuits contain logic which must be controlled with mutually exclusive (one-out-of-n) control signals. Common examples include controls to 3-state buses and pass-gate multiplexers. If these control signals are allowed to attain any value combination other than one-out-of-n, the controlled logic may produce an unknown (X) state. In a scan based design, these mutually exclusive signals ... View full abstract»

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  • Performance driven BIST technique for random logic

    Publication Year: 1995, Page(s):524 - 533
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB)

    Performance degradation due to insertion of BIST logic into high-speed designs has been analyzed. A framework to introduce BIST into random logic circuits, without causing timing violations has been proposed. Various heuristics for selecting flip-flops for BIST have been developed and studied in detail. Experimental results indicate an improvement in performance while optimizing fault coverage and... View full abstract»

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  • An efficient and economic partitioning approach for testability

    Publication Year: 1995, Page(s):403 - 412
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    This paper presents an RT level partitioning approach for sequential circuits described as data path and control part. The data path of a circuit is partitioned at some hard-to-test points detected by an RT level testability analysis algorithm. These points are then made directly accessible by DFT techniques. The control part is also modified to control the circuit in normal mode and test mode. In... View full abstract»

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  • Visualizing quality

    Publication Year: 1995, Page(s):87 - 96
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    ATE systems have many instruments with many ranges. System quality is difficult to manage. Two visualization algorithms for viewing system instrument stabilities are described. A previously derived traceability algorithm is enhanced. Typical results are described View full abstract»

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  • IntegraTEST: the new wave in mixed-signal test

    Publication Year: 1995, Page(s):750 - 760
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1820 KB)

    The paper describes a novel method for automated mixed-signal testing using a comprehensive, user friendly software environment, including a multitude of virtual instrumentation, advanced limiter functions, sequencers, true mixed-signal waveform editing tools and an easy-to-use interface to mixed signal design environments. Flexibility and simplicity-in-use are virtues of the new test approach in ... View full abstract»

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