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Electronic Computers, IEEE Transactions on

Issue 3 • Date June 1964

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Displaying Results 1 - 25 of 53
  • [Front cover]

    Publication Year: 1964 , Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Group

    Publication Year: 1964 , Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 1964 , Page(s): nil1
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    Freely Available from IEEE
  • Keith W. Uncapher New Chairman of the IEEE Computer Group

    Publication Year: 1964 , Page(s): 183
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    Freely Available from IEEE
  • Message from the New Chairman

    Publication Year: 1964 , Page(s): 184
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    Freely Available from IEEE
  • New Officers and Members of the Board

    Publication Year: 1964 , Page(s): 185 - 192
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  • Secondary State Assignment for Sequential Machines

    Publication Year: 1964 , Page(s): 193 - 203
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1852 KB)  

    One of the most important and complicated problems in the synthesis of a sequential machine described by a state diagram or table is the assignment of the states of the secondary variables to the states of the machine. The secondary assignment for a given machine varies in accordance with the requirements of the design. It has already been shown that the partition with the substitution property an... View full abstract»

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  • On the Convergence and Ultimate Reliability of Iterated Neural Nets

    Publication Year: 1964 , Page(s): 204 - 225
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3304 KB)  

    The organization and reliability of large redundant nets of formal neurons are investigated. Each neuron has m inputs and n outputs and is capable of performing at any one time any member of any prescribed subset of the total possible set of 22m·n functions. Various methods for obtaining large nets of predictable structure and function through the medium of element reproduction are dis... View full abstract»

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  • Analysis of Linear Sequential Circuits by Confluence Sets

    Publication Year: 1964 , Page(s): 226 - 231
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1051 KB)  

    In this paper the group-theoretical concept of ``confluence sets'' is introduced as a valuable tool in the analysis of linear sequential circuits (LSC's). Using this concept, a scheme is formulated for producing state graphs of autonomous LSC's which, in the ``singular'' case, is superior to currently known schemes. Singular LSC's, which are of potential interest in error correction systems, are s... View full abstract»

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  • A Method for Testing and Realization of Threshold Functions

    Publication Year: 1964 , Page(s): 232 - 239
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1317 KB)  

    A standard method for testing and realizing a threshold function is to solve a set of linear inequalities in which the unknowns are the n weights to be assigned to the n variables. In this paper a simple method of solving this set of inequalities is presented. Instead of using the weights themselves as the unknowns, a set of n new unknowns, the incremental weights ¿a1, ¿a2,... View full abstract»

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  • DONUT: A Threshold Gate Computer

    Publication Year: 1964 , Page(s): 240 - 247
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2091 KB)  

    During the past few years there has been a considerable amount of literature concerned with the realization of threshold logic. However, there are a number of questions concerning such factors as sensitivity and component savings which cannot be completely answered by such theoretical studies. DONUT (Digitally Operated Network Using Thresholds) is a small general purpose digital computer which was... View full abstract»

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  • The CSX-l Computer

    Publication Year: 1964 , Page(s): 247 - 250
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (703 KB)  

    A brief description of the logical structure and the instruction repertoire of a short word length (16 bits) computer is given. The unorthodox features which are discussed are 1) a variable-length addressing procedure, 2) a common multi-accumulator and index register structure, and 3) the identical processing of data and addresses. View full abstract»

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  • A Quantising Encoder

    Publication Year: 1964 , Page(s): 250 - 254
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (966 KB)  

    A device is described that converts voltages to digital form by means of a strategy basically faster than that used in the conventional trial encoder. A voltage corresponding to the contents of a 2n-bit register is obtained from the output of the digital-voltage decoder. The error between this voltage and the input voltage is quantized to the nearest power of two and subtracted from the contents o... View full abstract»

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  • High-Density Binary Recording Using Nonsaturation Techniques

    Publication Year: 1964 , Page(s): 255 - 261
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2223 KB)  

    Commercially available magnetic tape units have longitudinal recording densities of up to 2000 bits per inch, whereas analog instrumentation recorders are capable of recording up to 10,000 cycles per inch. These figures contrast with a theoretical recording density limitation for iron oxide of 250,000 bits per inch, and the reasons for this discrepancy are analyzed. Two experimental systems having... View full abstract»

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  • Cylindrical Film Memory Device Characteristics

    Publication Year: 1964 , Page(s): 261 - 268
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2328 KB)  

    This device is a single-bit storage element consisting of a 100-mil piece of 25-mil glass tubing with a 6000-A nickel-iron film coating. This paper describes those properties of the device which pertain to its operation in high-speed linear-word-selection memories. The device is used in the orthogonal mode, with an axial word field. The circumferential bit (digit) field coincides with the easy axi... View full abstract»

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  • Tunnel Diode Delay-Line Memory

    Publication Year: 1964 , Page(s): 269 - 272
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    This paper describes a memory system wherein bits of information are stored serially in time on electrical delay lines, The simplicity and speed of the basic storage cell makes large high-speed stores of this sort feasible. The paper stresses the basic principles of operation. A brief description of one such system model built to demonstrate these principles is included. View full abstract»

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  • Flux Divison in a Saturable Multipath Core

    Publication Year: 1964 , Page(s): 272 - 277
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    An mmf drive NI is applied to the major leg of asaturable ferrite core whose three legs are initially at negative saturation. The resulting ¿¿ in the driven leg divides into the other two (minor) legs, one of which is loaded by a resistive load. This division of flux is analyzed, using for each leg the parabolic inelastic switching model ¿ = ¿peak (F) [1-(¿/¿sat)... View full abstract»

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  • Exploitation of Initial Conditions to Achieve Flux Gain and Nondestructive Readout in Balanced Magnetic Circuits

    Publication Year: 1964 , Page(s): 278 - 284
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1300 KB)  

    A simple experiment on a magnetically-balanced circuit, consisting of a flux source and two equal-length parallel paths is outlined. It is observed that if a controlling signal causes one of the parallel paths to be preferred and this controlling signal is removed before switching is completed, the parallel path originally preferred continues to be preferred. The core equivalent of a balanced circ... View full abstract»

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  • DC Accuracy in a Fast Boxcar Circuit Via a Comparator

    Publication Year: 1964 , Page(s): 285 - 288
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (699 KB)  

    A capacitor-storage boxcar (i.e., zero-order hold) circuit is described, which has a one-half ¿sec sampling time and a 0-to 6-volt dynamic range, with less than 10-mv absolute error for a hold time of one second or less. No operational amplifier is used. In the new boxcar, feedback is applied via a difference amplifier comparator during sampling to make the readout voltage, not the voltage actual... View full abstract»

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  • Transistorized Multiplier and Divider and Its Applications

    Publication Year: 1964 , Page(s): 288 - 295
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    The inverse pair of logarithmic and exponential functions obtained from current voltage characteristics of junction transistors have been combined here to devise a direct method of analog multiplication and division which has an inherent tendency of self-compensation for the effects of temperature variation and also of mutual cancellation of nonlinear distortion arising in the individual stages. E... View full abstract»

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  • Synthesis of Practical Three-Input Majority Logic Networks

    Publication Year: 1964 , Page(s): 296 - 299
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (942 KB)  

    This paper deals with a method of realizing switching functions with three-input majority gates, utilizing a modification of the theory of Akers [1]. This approach attempts to minimize the total number of elements used for both gating and delay. The method derived is suitable for implementation on a digital computer and a program was written for the Burroughs 220 computer which produces excellent ... View full abstract»

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  • The Generation of Minimal Threshold Nets by an Integer Program

    Publication Year: 1964 , Page(s): 299 - 302
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (791 KB)  

    This paper deals with the problem of generating a combinatorial network of threshold gates capable of evaluating a partially specified Boolean function. With the additional restriction that the network is to be cycle-free, the procedure described is designed to generate a network of minimum complexity in the sense that it is comprised of the smallest possible number of threshold elements. The esse... View full abstract»

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  • A Self-Organizing Drum

    Publication Year: 1964 , Page(s): 302
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (228 KB)  

    First Page of the Article
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  • On Signal Deterioration in Digital Computers

    Publication Year: 1964 , Page(s): 303
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (261 KB)  

    First Page of the Article
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  • Protecting Core Memory Circuits with Error Correcting Cyclic Codes

    Publication Year: 1964 , Page(s): 303 - 304
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    First Page of the Article
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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope