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Test Conference, 1994. Proceedings., International

Date 2-6 Oct. 1994

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Displaying Results 1 - 25 of 131
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  • B-algorithm: a behavioral test generation algorithm

    Page(s): 968 - 979
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    A behavioral test generation algorithm (called the B-algorithm) is presented which generates tests directly from behavioral VHDL circuit descriptions using three types of behavioral faults (behavioral stuck-at faults, behavioral stuck-open faults, and micro-operation faults). Behavioral faults are defined by perturbing VHDL constructs. In particular, behavioral stuck-at faults are defined for virtual signals corresponding to expressions as well as for normal signals. The B-algorithm generates tests using three basic test generation operations (activation, propagation, and justification), which are systematically executed by manipulating three data structures (B-frontier, J-frontier, and A-queue). Rules for the test generation operations are defined using the concepts of two-phase activation and two-phase propagation. The B-algorithm has two unique features. First, it can generate tests for behavioral stuck-open faults, which in fact can detect some gate level transition faults. Second, it incorporates the concept of two-phase testing, a testing strategy where a fault is detected using two consecutive test sequences View full abstract»

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  • Transforming behavioral specifications to facilitate synthesis of testable designs

    Page(s): 184 - 193
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    Recently, several high level synthesis approaches have been proposed to synthesize testable data paths from behavioral specifications. This paper introduces a novel technique to transform behavioral specifications, such that an existing behavioral test synthesis system can generate area-efficient, testable designs with significantly lower partial scan overhead. Experimental results demonstrate the significant savings in partial scan overhead when the transformation is applied before using the behavioral test synthesis system to synthesize 100% test-efficient designs View full abstract»

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  • On path delay testing in a standard scan environment

    Page(s): 164 - 173
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    This paper discusses delay fault test generation methodologies that avoid the area and performance overhead of enhanced scan elements by the use of scan and functional justification techniques. Issues with the use of scan justification and functional justification in a standard edge-triggered single clock scan environment are discussed. A functional justification based path delay test generator for circuits designed using standard scan elements is described. This test generator uses a calculus that allows circuits containing internal tri-state elements and bi-directional ports to be supported. Clock suppression techniques are employed to minimize state justification requirements View full abstract»

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  • Techniques for characterizing DRAMs with a 500 MHz interface

    Page(s): 516 - 525
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    The advent of high-bandwidth DRAMs poses a number of new challenges for test and characterization. This paper describes a collection of techniques that were used in the design and characterization of a new DRAM architecture with 500 MHz I/O signals. Methods of fixturing and calibration are presented for achieving system accuracies of better than 100 ps. Laboratory techniques for measuring critical circuit parameters such as path delay, clock jitter, current source strength, and pin capacitances are shown as well. These techniques, along with on-chip test logic, which allows the DRAM core to be tested using conventional low-speed memory test equipment, enable full characterization of high bandwidth memories View full abstract»

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  • ATPG for heat dissipation minimization during test application

    Page(s): 250 - 258
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    A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application. The objective is to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds. Three new functions, namely transition controllability, observability and test generation costs, have been defined. It has been shown that the transition test generation cost is the minimum number of transitions required to test the corresponding stuck-at fault in fanout free circuits. This cost function is used for target fault selection while the other two functions are used to guide the backtrace and objective selection procedures of PODEM. The tests generated by the proposed ATPG decrease heat dissipation during test application by a factor of 2-23 for benchmark circuits View full abstract»

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  • On synthesizing circuits with implicit testability constraints

    Page(s): 989 - 998
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    The goal of test synthesis is to create a circuit which is completely testable under a design-for-test (DFT) methodology while meeting performance and area requirements. It includes such steps as testability design rule checking and automated repair of identified violations. Potential violations include clock and asynchronous circuitry which do not operate in a manner consistent with the chosen methodology and tools. Repair is performed by transforming the network through the insertion of additional logic to perform test functions (a scan chain, for example) and mapping this logic into the implementation technology, without affecting the original, system mode operation of the network. This paper discusses the concept of test synthesis constraints which embody the conditions under which the circuit must operate in order to be fully testable. Based on the constraints, the circuit is transformed using algorithms similar to those of automatic test pattern generation. Rather than adding entirely new hardware, existing system logic and connectivity is used to implement test functions wherever possible. Results produced by a prototype implementation indicate that test logic can be inserted into a network with very little performance or area overhead View full abstract»

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  • Automatic failure analysis system for high density DRAM

    Page(s): 526 - 530
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    In this paper, the automatic failure analysis method based on the random bit failure causing the major yield drop in DRAM and the analysis system named “SEC FAILURE ANALYSIS SYSTEM” are discussed. This system is developed for the accurate and rapid electrical analysis of the failure in a statistical manner in order to make a quick feedback to the manufacturing process View full abstract»

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  • Sequentially untestable faults identified without search (“simple implications beat exhaustive search!”)

    Page(s): 259 - 266
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    This paper presents a novel fault-independent algorithm for identifying untestable faults in sequential circuits. The algorithm is based on a simple concept that a fault which requires an illegal combination of values as a necessary condition for its detection is untestable. It uses implications to find a subset of such faults whose detection requires conflicts on certain lines in the circuit. No global reset state is assumed and no state transition information is needed. Our fault-independent algorithm identifies untestable faults without any search as opposed to exhaustive search done by fault-oriented test generation algorithms. Results on benchmark and real circuits indicate that we find a large number of untestable faults, much faster (up to 3 orders of magnitude) than a test-generation-based algorithm that targeted the faults identified by our algorithm. Moreover, many faults identified as untestable by our approach were aborted when targeted by a sequential test generator View full abstract»

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  • Testability features of the MC68060 microprocessor

    Page(s): 60 - 69
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    This report describes the testability design goals, constraints, and strategies used in the development of the MC68060 microprocessor. It explores the design choices that were made and the considerations that led to those choices. It presents the architectures and methodologies used to implement the design choices, and ends by describing the successes, failures, and future refinements of the test methodologies and architectures View full abstract»

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  • Low power mode and IEEE 1149.1 compliance: a low power solution

    Page(s): 660 - 669
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    The requirements of a low power mode, built into complex VLSI IC's such as microprocessors, seem to conflict with the IEEE 1149.1 Standard (JTAG). The perception that the TAP Pins-T¯R¯S¯T¯, TMS, and TDI-must be equipped with power-consuming pullup resistors or that low power and 1149.1 modes of operation are mutually exclusive is erroneous. Certain techniques can be used during the design and implementation of the TAP and the TAP controller that will allow the IC to enter low power mode without interference or unnecessary power consumption from the JTAG logic and will allow JTAG operations during low power mode while maintaining full compliance to the 1149.1 standard View full abstract»

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  • A simulation-based protocol-driven scan test design rule checker

    Page(s): 999 - 1006
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    The test protocol for a serial scan design comprises the serial scan-in, parallel measure & capture, and serial scan-our operations. Through symbolic simulation of the protocol, compliance with scan design rules can be verified. For example, simulation of the scan-in operation should establish an arbitrary known state in all sequential cells within the design. A cell whose state is not controllable represents a design rule violation. This approach is both more flexible and more robust than previous work, and addresses current issues with the integration of internal scan and boundary scan. Further, the approach links the tasks of design rule checking and the formatting of the output of Automatic Test Pattern Generation (ATPG) into a scan test program. This approach has been applied successfully to a wide variety of designs, up to 700 K gates View full abstract»

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  • Feasibility study of smart substrate multichip modules

    Page(s): 41 - 49
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    This paper analyzes the feasibility of MCMs using active silicon substrates with built-in resting circuitry. It identifies the domain of applicability of such MCMs and points to limitations of the “Known Good Die” approach View full abstract»

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  • Detection and correction of systematic type I test errors through concurrent engineering

    Page(s): 531 - 538
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    Systematic Type I test errors in the integrated circuit production test environment are analyzed with an emphasis on wafer level test problems. Effective use of concurrent engineering procedures is shown to be a critical factor in the rapid detection and solution of these problems View full abstract»

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  • Reduced scan shift: a new testing method for sequential circuits

    Page(s): 624 - 630
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    This paper presents a new testing method for sequential circuits, called reduced scan shift, which generates short test sequences. In this method, only part of flip-flops close to the scan input line are controlled and another part of flip-flops close to the scan output line are observed by scan shift operations as small as possible. For the purpose of reducing scan shift operations, the following points are considered: (1) how to decide target faults which each test vector should detects, (2) how to arrange flip-flops in the scan chain, (3) how to decide the order of test vectors. Experimental results for ISCAS'89 benchmark circuits are given to show the effectiveness of this method View full abstract»

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  • Observations on the 1149.x family of standards

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    Five years of experience with the IEEE 1149.1 standard are discussed. It has been widely accepted across the electronics industry. It has made major contributions to board level testability. However, the advancement of the 1149.1 standard has not been as rapid as one might have imagined and there are some outstanding problems that it does not well address. As a member of the 1149.1 and P1149.4 working groups, as well as a developer of software for ATE systems, the author is interested in what one can learn from the 1149 and discusses his experiences in this field View full abstract»

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  • Designing “dual personality” IEEE 1149.1 compliant multi-chip modules

    Page(s): 446 - 455
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    The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture Standard can be used at many different levels in the integration hierarchy of a product. However there is one level where using the standard poses some difficulty. This is multi-chip modules (MCM). This paper explores the problem and proposes a set of solutions for different classes of MCMs View full abstract»

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  • An IDDQ based built-in concurrent test technique for interconnects in a boundary scan environment

    Page(s): 670 - 676
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    An IDDQ based scheme has been presented for concurrent built-in self-test of MCM interconnects. The scheme detects interconnect faults while the system is on-line View full abstract»

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  • Testability strategy of the Alpha AXP 21164 microprocessor

    Page(s): 50 - 59
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    This paper describes the testability strategy and design-for-test features of the Alpha AXP 21164 microprocessor. It discusses the specific testability and manufacturability issues of the chip and the innovative solutions employed to solve them View full abstract»

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  • Generating march tests automatically

    Page(s): 870 - 878
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    Many memory tests have been designed in the past, one class of tests which has been proven to be very efficient in terms of fault coverage as well as test time, is the class of march tests. Designing march tests is a tedious, manual task. This paper presents a method which can, given a set of fault models, automatically generate the required march tests. It has been implemented in the programming language C and shown to be effective View full abstract»

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  • Simulation results of an efficient defect analysis procedure

    Page(s): 729 - 738
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    For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavior. In this paper, a method is presented for computing the occurrence probabilities of certain defects and the realistic fault coverage for test sets. The method is highly efficient as a pre-processing step is used for partitioning the layout and extracting the defects ranked in the order of their occurrence probabilities. The method was applied to a public domain library where defects causing a complex faulty behavior are possible. The occurrence probability of these faults was computed, and the defect coverage for different test sets was determined View full abstract»

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  • Configuring flip-flops to BIST registers

    Page(s): 939 - 948
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    Built-in self-test test registers must segment a circuit such that there exists a feasible test schedule. If a register transfer description is used for selecting the positions of test registers, the space for optimizations is small. In this paper, 1-bit test cells are inserted at gate level, and an initial test schedule is constructed. Based on the information of this schedule, test cells that can be controlled in the same way are assembled to test registers. Finally, a test schedule at RT level is constructed and a minimal set of test control signals is determined. The presented approach can reduce both BIST hardware overhead and test application time. It is applicable to control units and circuits produced by control oriented synthesis where an RT description is not available. Considerable gains can also be obtained if existing RT structures are reconfigured for self-testing in the described way View full abstract»

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  • Defects, fault coverage, yield and cost, in board manufacturing

    Page(s): 539 - 547
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    An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate component functional defect rate and test coverage. A new yield model which accounts for the clustering of solder defects is introduced and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given View full abstract»

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  • An integrated approach for analog circuit testing with a minimum number of detected parameters

    Page(s): 631 - 640
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    A technique for multifrequency test vector generation using testability analysis and output response detection by adding a translation built-in self test (T-BIST) is presented. We study the testability of analog circuits in the frequency domain by introducing the analog fault observability concept. This testability evaluation will be helpful in generating the test vectors and for selecting test nodes for the various types of faults. In the proposed approach test vector generation and test point selection allow a significant reduction in the number of measured output parameters necessary for testing (to one or two parameters) without a loss in fault coverage. The T-BIST approach consists of verifying whether or not the tested parameters for the given test vector are within the acceptance range. This technique is based on the conversion of each detected parameter to a DC voltage. Results are presented for different practical filters for which a complete test solution was achieved View full abstract»

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  • Optimizing boundary scan in a proprietary environment

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    Boundary scan provides test engineers with a powerful tool for detecting both board-level and chip-level faults. The benefits of boundary scan can be diminished, however, when commonly used design and test generation tools are tied to a specific implementation (standard) of boundary scan. By requiring a specific implementation, test tools may limit a designer's ability to design an optimal product. A “higher” level standard is required which abstracts the concept of accessibility to device I/O from specific implementation details. Abstracting information required for tool developers from implementation details should allow tools to become more flexible, enabling designers to optimize their specific boundary scan implementation without losing the benefit of the tools themselves View full abstract»

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