Proceedings., International Test Conference

2-6 Oct. 1994

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Displaying Results 1 - 25 of 131
  • An improved method of ADC jitter measurement

    Publication Year: 1994, Page(s):763 - 770
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (402 KB)

    This paper describes an original and highly accurate method for measuring analog to digital converters jitter. Previous works cover the "locked" histogram test which is generally used to estimate aperture uncertainty. This new method uses substraction techniques in a dual-channel sampling system. Synthesizers phase noise, voltage noise and ADC nonlinearities are removed to give the sum of both ADC... View full abstract»

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  • Author index

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (154 KB)
    Freely Available from IEEE
  • The effect on quality of non-uniform fault coverage and fault probability

    Publication Year: 1994, Page(s):739 - 746
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. The first part addresses the issue of non-uniform distribution of detected faults. It is shown that there is a large difference in final quality between covering the chip all over and leaving parts relatively untested, even if the coverage is the same in both cases. The second par... View full abstract»

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  • Concurrent engineering with DFT in the digital system: a parallel process

    Publication Year: 1994, Page(s):879 - 886
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    A highly parallel design process is a means to minimize the system design cycle time. Concurrent engineering principles applied to design and test attain dramatic cycle time reduction in systems with structurally tested ICs View full abstract»

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  • MCM test trade-offs

    Publication Year: 1994
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    The cost of design-for-test is a key factor when determining whether or not to use MCM technology. Higher-end MCMs must be designed-for-test (DFT) since not implementing DFT is more expensive in the long run. This may not be the case for lower-cost, lower performance MCMs. Among other advantages, MCM technology can offer smaller size, better performance, and lower weight. But the cost of poor DFT ... View full abstract»

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  • Analogue fault simulation based on layout dependent fault models

    Publication Year: 1994, Page(s):641 - 649
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    A testability analysis procedure for complex analogue circuits is presented based on layout dependent fault models extracted from process defect statistics. The technique has been applied to a mixed-signal phase locked loop circuit and a number of test methodologies have been evaluated including the existing production test. It is concluded that the fault coverage achieved by this test can be impr... View full abstract»

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  • Modeling for structured system interconnect test

    Publication Year: 1994, Page(s):127 - 133
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    With the acceptance of test standards such as IEEE 1149.1, the potential for structured methods for system test is growing rapidly. In particular, interconnect testing based on standardized boundary scan structures will be an important component of a future structured system test methodology. A strategy based on building an interconnect topology model of the system under test and using that model ... View full abstract»

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  • Behavioral test generation using mixed integer nonlinear programming

    Publication Year: 1994, Page(s):958 - 967
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (868 KB)

    This paper describes a novel technique to generate test vectors for single stuck-at faults using the behavioral description of the circuit function and the mapping from the behavior into the hardware that implements it. The test vector generation problem is formulated as a mixed integer nonlinear programming (MINLP) problem, and the test vectors are obtained by solving a series of MINLPs. The tech... View full abstract»

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  • Simulation results of an efficient defect analysis procedure

    Publication Year: 1994, Page(s):729 - 738
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavior. In this paper, a method is presented for computing the occurrence probabilities of certain defects and the realistic fault coverage for test sets. The method is highly efficient as a pre-processing step is used for pa... View full abstract»

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  • Testing issues on high speed synchronous DRAMs

    Publication Year: 1994
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB)

    The test programming becomes very much complicated due to functionality and special features implemented in SDRAMs. Considering the combination of speed variations and operational modes, the number of the test items would easily exceed beyond the acceptable limit. The SDRAM testing issues are listed as follows: high speed tests with a slow production tester; load board and load circuit design for ... View full abstract»

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  • Generating march tests automatically

    Publication Year: 1994, Page(s):870 - 878
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    Many memory tests have been designed in the past, one class of tests which has been proven to be very efficient in terms of fault coverage as well as test time, is the class of march tests. Designing march tests is a tedious, manual task. This paper presents a method which can, given a set of fault models, automatically generate the required march tests. It has been implemented in the programming ... View full abstract»

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  • Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O

    Publication Year: 1994, Page(s):604 - 613
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    Industrial circuit designs commonly contain three-state elements, such as buses and drivers, transmission gates, and bidirectional I/O. A 5-valued fast fault simulation method and a 4-valued parallel pattern version that can handle these circuits are presented. Results demonstrate the effectiveness of the proposed methods in the presence of three-state elements, and show but a small performance de... View full abstract»

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  • A generic test and maintenance node for embedded system test

    Publication Year: 1994, Page(s):143 - 153
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    In order to build high performance embedded test systems, a Digital Test and Maintenance ASIC (DTMA) with embedded microprocessor, test bus port, and test network communication ports has been conceived. This DTMA “node” and 2 companion analog data acquisition devices form the basis of a structured, system level design-for-test (DFT) methodology which is applicable to medium or high per... View full abstract»

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  • Manufacturing test simulator: a concurrent engineering tool for boards and MCMs

    Publication Year: 1994, Page(s):903 - 910
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    A board and multi-chip module (MCM) manufacturing test simulator (MTSIM) is described, MTSIM is a concurrent engineering tool used to simulate the manufacturing test and repair aspects of boards and MCMs from design concept through manufacturing release. MTSIM helps designers select assembly process, specify, design for test (DFT) features, select board test coverage specify ASIC defect level goal... View full abstract»

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  • Multichip module testing methodologies: what's in; what's not

    Publication Year: 1994
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    The multichip module (MCM) is rapidly finding its way into the design of commercial electronic systems. The MCM offers this market opportunities for increasing performance, lowering size and weight, lowering power requirements, lowering costs, and improving the functionality per unit area. These characteristics are much too attractive to pass up and thus has begun a headlong rush to create designs... View full abstract»

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  • An integrated approach for analog circuit testing with a minimum number of detected parameters

    Publication Year: 1994, Page(s):631 - 640
    Cited by:  Papers (48)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (996 KB)

    A technique for multifrequency test vector generation using testability analysis and output response detection by adding a translation built-in self test (T-BIST) is presented. We study the testability of analog circuits in the frequency domain by introducing the analog fault observability concept. This testability evaluation will be helpful in generating the test vectors and for selecting test no... View full abstract»

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  • 3B21D BIST/Boundary-Scan system diagnostic test story

    Publication Year: 1994, Page(s):120 - 126
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The 3B21D BIST and Boundary-Scan Design, based on the ANSI/IEEE Std 1149.1-1990, has given the 3B21D System Diagnostic Test Strategy an excellent set of tests at all levels of product assembly View full abstract»

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  • Making the circular self-test path technique effective for real circuits

    Publication Year: 1994, Page(s):949 - 957
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    The paper assesses the effectiveness of the circular self-test path BIST technique from an experimental point of view and proposes an algorithm to overcome the low fault coverage that often arises when real circuits are examined. Several fault simulation experiments have been performed on the ISCAS89 benchmark set, as well as on a set of industrial circuits: in contrast to the theoretical analysis... View full abstract»

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  • ASIC test cost/strategy trade-offs

    Publication Year: 1994, Page(s):93 - 102
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    Supplying cost effective testing for large application specific integrated circuits (ASICs) is one of the key challenges facing the semiconductor industry. Projections suggest that it will not be cost effective to continue in the current test direction. ASIC suppliers must be able to offer a flexible, cost-effective set of test solutions that will meet a variety of customer requirements. This pape... View full abstract»

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  • Back annotation of physical defects into gate-level, realistic faults in digital ICs

    Publication Year: 1994, Page(s):720 - 728
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    IC complexity moves the design activity upwards, into higher levels of abstraction. Product quality requires the move of test activity downwards, down to IC physical level. High quality test requires the ability to cover physical defects. However, circuit complexity makes test preparation, at transistor level, prohibitive. A methodology for back annotation of physical defects into gate level reali... View full abstract»

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  • Built-in system test and fault location

    Publication Year: 1994, Page(s):291 - 299
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    In their purest form, BIST, BScan and Scan do not lend themselves to in-service test-compromises and extensions are required. We describe the experience of implementing built-in fault detection and location in a large digital system View full abstract»

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  • Practical test methods for verification of the EDRAM

    Publication Year: 1994
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    The Ramtron EDRAM is a 4 Mb dynamic RAM with 2 Kb static RAM cache. It is designed for 35 ns random access times, 15 ns cache cycle times with 5 ns pulse widths and includes logic functions not found on standard DRAM's. The simple solution to testing the part is a 67 to 100 MHz machine, but a more creative solution requires the use of only slightly more creative techniques. The EDRAM, while having... View full abstract»

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  • Transparent memory testing for pattern sensitive faults

    Publication Year: 1994, Page(s):860 - 869
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    This paper presents a new methodology for RAM testing based on PS(n, k) fault model (the k out of n pattern sensitive fault model). According to the model the contents of any memory cell which belongs to an n-bit memory block, or ability to change the contents, is influenced by the contents of any k-1 cells from this block. This paper includes the investigation of memory testing approaches based o... View full abstract»

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  • Defect classes-an overdue paradigm for CMOS IC testing

    Publication Year: 1994, Page(s):413 - 425
    Cited by:  Papers (137)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB)

    The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest strategy match the defec... View full abstract»

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  • ATPG for heat dissipation minimization during test application

    Publication Year: 1994, Page(s):250 - 258
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application. The objective is to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds. Three new functions, namely transition controllability, observability and test gen... View full abstract»

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