By Topic

Test Conference, 1994. Proceedings., International

Date 2-6 Oct. 1994

Filter Results

Displaying Results 1 - 25 of 131
  • Author index

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (154 KB)
    Freely Available from IEEE
  • An IDDQ based built-in concurrent test technique for interconnects in a boundary scan environment

    Publication Year: 1994, Page(s):670 - 676
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    An IDDQ based scheme has been presented for concurrent built-in self-test of MCM interconnects. The scheme detects interconnect faults while the system is on-line View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Benchmarking

    Publication Year: 1994
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    The importance of determining the role and influence of the test tool when integrated into the "existing" design and test methodology of the user, and then formulating the benchmark process, is emphasised. This can affect shorter benchmark cycles. The focus of an evaluation process should be more of which tool offers the most productive way of using existing techniques to yield successful results"... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low power mode and IEEE 1149.1 compliance: a low power solution

    Publication Year: 1994, Page(s):660 - 669
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    The requirements of a low power mode, built into complex VLSI IC's such as microprocessors, seem to conflict with the IEEE 1149.1 Standard (JTAG). The perception that the TAP Pins-T¯R¯S¯T¯, TMS, and TDI-must be equipped with power-consuming pullup resistors or that low power and 1149.1 modes of operation are mutually exclusive is erroneous. Certain techniques can be used during... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An approach to accelerate scan testing in IEEE 1149.1 architectures

    Publication Year: 1994, Page(s):314 - 322
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    This paper describes an approach which can accelerate scan testing of combinational and sequential circuits within IEEE 1149.1 architectures. The approach can be used at both IC and system test levels, however most of the test time reduction benefits of this approach are seen at the system level View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 1149.1 scan control transport levels

    Publication Year: 1994
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    1149.1 scan constitutes the most general standard of electronic hardware test control available today. Delivery of an 1149.1 scan service from maintenance processors to system components constitutes a universal challenge to systems designers, and a major opportunity for venders in the chip and scan software business. A largely neglected level of scan transport may rapidly become important to syste... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testing issues on high speed synchronous DRAMs

    Publication Year: 1994
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB)

    The test programming becomes very much complicated due to functionality and special features implemented in SDRAMs. Considering the combination of speed variations and operational modes, the number of the test items would easily exceed beyond the acceptable limit. The SDRAM testing issues are listed as follows: high speed tests with a slow production tester; load board and load circuit design for ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An analog multi-tone signal generator for built-in-self-test applications

    Publication Year: 1994, Page(s):650 - 659
    Cited by:  Papers (40)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    This paper presents the design of an analog oscillator capable of generating multi-tone signals by encoding the information in an oversampled delta-sigma modulated bit-stream. With the exception of an imprecise lowpass filter, the proposed design is completely digital allowing accurate control of the amplitude, frequency, and phase of all sinusoids making up the multi-tone signal. Simulations and ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A hybrid fault simulator for synchronous sequential circuits

    Publication Year: 1994, Page(s):614 - 623
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information available about the initial state of the circuit. In this case, an unknown initial state is assumed which is usually handled by introducing a three-valued logic. It is known that fault simulation based upon this logic only determines a lower bound for ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Configuring flip-flops to BIST registers

    Publication Year: 1994, Page(s):939 - 948
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    Built-in self-test test registers must segment a circuit such that there exists a feasible test schedule. If a register transfer description is used for selecting the positions of test registers, the space for optimizations is small. In this paper, 1-bit test cells are inserted at gate level, and an initial test schedule is constructed. Based on the information of this schedule, test cells that ca... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Environmental Stress Testing with Boundary-Scan

    Publication Year: 1994, Page(s):307 - 313
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Environmental Stress Testing (EST) enhances product quality and reliability by detecting latent or marginal defects in a product. For EST to be effective, testing of a product must achieve a high fault coverage so that as many EST-induced defects can be detected. By utilizing Boundary-Scan (IEEE Std 1149.1-1990), EST can achieve a high fault coverage and at the same time, minimize test cost. The p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Backplane test bus selection criteria

    Publication Year: 1994
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    The author discusses the architecture of the IEEE 1149.1 Standard, its applications and selection criteria. Although the evaluation and selection of a multi-drop addressable 1149.1 architecture are completed, the hardware has been designed such that alternative architectures could be implemented, if warranted, without a complete redesign of the payload digital electronics. The primary advantage of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Practical test methods for verification of the EDRAM

    Publication Year: 1994
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    The Ramtron EDRAM is a 4 Mb dynamic RAM with 2 Kb static RAM cache. It is designed for 35 ns random access times, 15 ns cache cycle times with 5 ns pulse widths and includes logic functions not found on standard DRAM's. The simple solution to testing the part is a 67 to 100 MHz machine, but a more creative solution requires the use of only slightly more creative techniques. The EDRAM, while having... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analogue fault simulation based on layout dependent fault models

    Publication Year: 1994, Page(s):641 - 649
    Cited by:  Papers (35)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    A testability analysis procedure for complex analogue circuits is presented based on layout dependent fault models extracted from process defect statistics. The technique has been applied to a mixed-signal phase locked loop circuit and a number of test methodologies have been evaluated including the existing production test. It is concluded that the fault coverage achieved by this test can be impr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient test response compression for multiple-output circuits

    Publication Year: 1994, Page(s):501 - 510
    Cited by:  Papers (22)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    A major obstacle to achieving high fault coverage in built-in self testing (BIST) methods that employ response compression is aliasing, which occurs when a faulty circuit's signature maps to the fault-free signature. Another problem with many compression methods is that they are inefficient for multiple-output circuits. We present data showing that in most cases, faults are sensitized to an odd nu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A test methodology to support an ASEM MCM foundry

    Publication Year: 1994, Page(s):426 - 435
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (856 KB)

    MCM testing can be challenging enough when the chip, substrate, and MCM design are within the control of the same company. In the foundry environment, however, even more robust strategies must be adopted. In this paper a test methodology is described which consolidates the various MCM test stages to form a flexible, low-cost, quick turn-around-time test flow View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of a solution for achieving known-good-die

    Publication Year: 1994, Page(s):15 - 21
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB)

    A major problem curtailing the growth of the multichip module market is the IC manufacturer's inability to provide known-good-die. To address this, a cost-effective process to burn-in and test at the die level is in development View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O

    Publication Year: 1994, Page(s):604 - 613
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    Industrial circuit designs commonly contain three-state elements, such as buses and drivers, transmission gates, and bidirectional I/O. A 5-valued fast fault simulation method and a 4-valued parallel pattern version that can handle these circuits are presented. Results demonstrate the effectiveness of the proposed methods in the presence of three-state elements, and show but a small performance de... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The effect on quality of non-uniform fault coverage and fault probability

    Publication Year: 1994, Page(s):739 - 746
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. The first part addresses the issue of non-uniform distribution of detected faults. It is shown that there is a large difference in final quality between covering the chip all over and leaving parts relatively untested, even if the coverage is the same in both cases. The second par... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits

    Publication Year: 1994, Page(s):929 - 938
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB)

    In this paper we present a new test per clock BIST technique that provides 100% fault coverage of detectable single stuck-at faults for random pattern resistant circuits with low test application time and limited hardware overhead. The technique uses selective bit-fixing plus biased pseudorandom patterns and is referred to as fixed-biased pseudorandom BIST. An automatic design tool (FBIST) specifi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ensuring system traceability to international standards

    Publication Year: 1994, Page(s):471 - 480
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    ATE Systems have many instruments with many ranges. Testers can have >12,000 specifications which must be traceable to international standards. The described algorithm reduces calibration down time, and guarantees traceable testing View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testability features of the MC68060 microprocessor

    Publication Year: 1994, Page(s):60 - 69
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (988 KB)

    This report describes the testability design goals, constraints, and strategies used in the development of the MC68060 microprocessor. It explores the design choices that were made and the considerations that led to those choices. It presents the architectures and methodologies used to implement the design choices, and ends by describing the successes, failures, and future refinements of the test ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testing CMOS logic gates for: realistic shorts

    Publication Year: 1994, Page(s):395 - 402
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    It is assumed that tests generated using the single stuck-at fault model will implicitly detect the vast majority of fault-causing defects within logic elements. This may not be the case. In this paper we characterize the possible shorts in the combinational cells in a standard cell library. The characterization includes errors on the cell outputs, errors on the cell inputs, and excessive quiescen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Residual charge on the faulty floating gate CMOS transistor

    Publication Year: 1994, Page(s):555 - 561
    Cited by:  Papers (38)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    A common defect that can occur in CMOS integrated circuits is a break in a signal track. The effect of this defect is strongly dependent on the amount of charge trapped on the isolated MOS transistor gate. Results of measurements on test structures are presented which reveal a range of values for the trapped charge. This causes the resulting fault to have a widely varying effect on circuit perform... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Roadmap for extending IEEE 1149.1 for hierarchical control of locally-stored, standardized command set, test programs

    Publication Year: 1994, Page(s):300 - 306
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    This paper proposes a roadmap for an embedded system test strategy that uses IEEE Standard 1149.1 as a multidrop, addressable backplane test bus to provide test access by a central diagnostic processor to local diagnostics contained in flash memory chips located on each module. This proposal is an 1149.1 extension based upon the SCAN Bridge which in turn was based on Bhavsar's paper (1991) which e... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.