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Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on

Date 4-6 Oct. 2006

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Displaying Results 1 - 25 of 67
  • 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Cover

    Page(s): c1
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  • 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Title

    Page(s): i - iii
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  • 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Copyright

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  • 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - TOC

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  • Message from the Symposium Chair

    Page(s): xi - xii
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  • Adaptive Design for Performance-Optimized Robustness

    Page(s): 3 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (166 KB) |  | HTML iconHTML  

    We present adaptive design techniques that compensate for manufacturing induced process variations in deep sub-micron (DSM) integrated circuits. Process variations have a significant impact on parametric behavior of modern chips, and adaptive design techniques that make a chip self-configuring to work optimally across process corners are fast evolving as a potential solution to this problem. Such schemes have two main components, a mechanism for sensing process perturbations, and one or more process compensation schemes that are driven by this mechanism. The adaptive design schemes presented in this paper are simple, low overhead techniques for noise tolerance in DSM CMOS circuits, to enhance their manufacturing yield. The process perturbation sensing scheme is based on on-chip delay measurement with a performance based bound on adaptation, which enables performance optimized robustness to noise in the face of process variations View full abstract»

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  • Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration

    Page(s): 12 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    In this paper, a new adaptive PLL is implemented. This PLL employs a simple yet effective jitter test circuit to monitor the PLL jitter performance. Additionally, it uses a digital control unit to dynamically adjust the switched loop filter to suppress the jitter. By using this structure, the trade-off between the PLL locking speed and jitter performance can be balanced View full abstract»

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  • Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates

    Page(s): 20 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    This paper presents simulations of 3 different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo simulations. The simulations clearly favors the minority-3 mirrored gate, and a gate-level redundancy scheme, where identical circuits with the same input drive the same output-node, is further explored as a means of increasing fault- and defect-tolerance. Important tradeoffs between supply voltage, redundancy and yield are revealed, and VDD = 175 mV is suggested as a minimum useful operating voltage, combined with a redundancy factor of 2 View full abstract»

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  • Gate Failures Effectively Shape Multiplexing

    Page(s): 29 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (203 KB) |  | HTML iconHTML  

    This paper investigates the behavior of multiplexing (MUX) schemes in combination with the elementary gates. The two schemes under investigation are majority (MAJ) and NAND MUX. The simulation results presented here are for single-electron technology, but could easily be extended to CMOS. The components of the gates have been subjected only to geometric variations. Firstly, the gates and the two MUX schemes are analyzed theoretically. Secondly, simulations using probability transfer matrices (PTM) allow evaluating both MUX schemes at a redundancy factor R = 6. Finally, the gates are compared in terms of their intrinsic probability of failure (with respect to geometric variations), and the two MUX schemes are weighted against the reliability enhancements they are bringing into the system. By comparing the simulation results from PTM with the ones based on (geometric) variations, this study gives deeper insights into the behavior of MUX schemes, and show that the gates play a major role, strongly affecting MUX systems View full abstract»

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  • Test Generation for Open Defects in CMOS Circuits

    Page(s): 41 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB) |  | HTML iconHTML  

    Open defects in CMOS circuits require two-pattern tests for detection. Traditionally, the only two-pattern tests included in manufacturing test are those targeting transition delay faults. Such tests, however, do not provide complete coverage of all the open defects. In this paper we propose the use of a unified test set that detects all inline resistance faults which model interconnect open defects and all transistor stuck-open faults which model intra-gate open defects in order to obtain a comprehensive coverage of open defects. We also describe a method of generating the proposed test set using an ATPG program for transition delay faults whose sizes are comparable to transition delay fault based test set View full abstract»

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  • Implicit Critical PDF Test Generation with Maximal Test Efficiency

    Page(s): 50 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    A new framework for generating test sets with high test efficiency (TE) for critical path delay faults (PDFs) is presented. TE is defined as the number of new critical PDFs detected by a generated test. The proposed method accepts as input a set of potentially critical PDFs and generates a compact test set for only the critical PDFs (i.e., non-sensitizable PDFs are effectively dropped from consideration), whilst avoiding any path or segment enumeration. This is done by exploiting the properties of the ISOPs/ZBDD data structure, which is shown to efficiently represent a set of critical paths along with all their associated sensitization test cubes. The experimental results demonstrate that the proposed method is scalable in terms of test efficiency and can generate very compact test sets for critical PDFs View full abstract»

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  • Selecting High-Quality Delay Tests for Manufacturing Test and Debug

    Page(s): 59 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (161 KB) |  | HTML iconHTML  

    The process of debugging timing failures requires the selection of a small set of high-quality tests which can excite critical paths and cause a circuit to fail at as low a frequency as possible. Since the primary source of such vectors are functional vectors which can run into millions of cycles, a cost-effective methodology for selecting high quality delay tests should not require an excessive computational effort and should guarantee reasonable accuracy. We propose two metrics for estimating the delay under a given test to aid in ranking tests in order of their ability to excite critical delays. The first metric is path-based, i.e., it estimates delays of excited paths, and associates the worst-case delay over all the excited paths with the test. The second metric is cone-based, i.e., it estimates the worst-case delay for the logic cone of every output without considering paths explicitly, and associates the largest delay over all the cones with the test. For each of these two metrics, we evaluate the correlation between the metric and the delay computed by circuit simulation. Results on combinational benchmark circuits demonstrate that the metrics achieve reasonable accuracy in test selection at a significantly lower computation time than circuit simulation View full abstract»

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  • Testing Reversible 1D Arrays for Molecular QCA

    Page(s): 71 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. As the bijective nature of reversibility makes testing significantly easier than in the general case, testing of the reversible gates is pursued in detail. C-testability of a 1D array is investigated for single cell fault as well multiple cell faults. Defect analysis of the reversible gates is pursued under a single missing/additional cell assumption View full abstract»

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  • Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design

    Page(s): 80 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (695 KB) |  | HTML iconHTML  

    The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges. The most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This issue is commonly referred to as the "layout =timing" problem. To circumvent the problem, a novel self-timed circuit design technique referred to as the locally synchronous, globally asynchronous design for QCA has been recently proposed. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design is be possible. Also, the proposed technique is more scalable in designing large-scale systems. Since a less number of cells is used, the overall area is smaller and the manufacturability is better. In this paper, numerous multi-bit adder designs are considered to demonstrate the layout efficiency and robustness of the proposed globally asynchronous QCA design technique View full abstract»

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  • Error Tolerance of DNA Self-Assembly by Monomer Concentration Control

    Page(s): 89 - 97
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB) |  | HTML iconHTML  

    This paper proposes the control of monomer concentration as a novel improvement of the kinetic tile assembly model (kTAM) to reduce the error rate in DNA self-assembly. Tolerance to errors in this process is very important for manufacturing highly dense ICs; the proposed technique significantly decreases error rates (i.e. it increases error tolerance) by controlling the concentration of monomers. A stochastic analysis based on a new state model is presented. Error rates reductions of at least 10% are found by evaluating the proposed scheme comparing to a scheme with constant concentration. One of the significant advantages of the proposed scheme is that it doesn't entail an overhead such as increase in size and a slow growth, while still achieving a significant reduction in error rate View full abstract»

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  • Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects

    Page(s): 98 - 106
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the photolithography. Various reconfigurable architectures have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density systems consisting of nanometer-scale elements are likely to have many imperfections and variations; thus, defect-tolerance is considered as one of the most exigent challenges. In this paper, we evaluate three different logic mapping algorithms with defect avoidance to circumvent clustered defective crosspoints in nanowire reconfigurable crossbar architectures. The effectiveness of inherited redundancy and configurability utilization is demonstrated through extensive parametric simulations View full abstract»

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  • A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices

    Page(s): 107 - 118
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    In this paper, a novel defect tolerance and test method is proposed for highly defect prone reconfigurable nanoscale devices. The method is based on searching for a fault-free implementation of functions in each configurable nanoblock. The proposed method has the advantage of not relying on defect location information (defect map). It also removes the requirement of per chip placement and routing. A simulation tool is developed and several experiments are performed on MCNC benchmarks to evaluate defect tolerance and yield achievable by the proposed method. A greedy search algorithm is also developed in this simulation program that finds a fault-free configuration of each function of an application on a nanoblock of the device. The experiments are performed for different defect rates and under different values of redundancy provided for the device model. The results show that the proposed method can achieve high yields in acceptable amount of test and reconfiguration time under very high defect densities and with minimum amount of redundancy provided in the device View full abstract»

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  • Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor

    Page(s): 119 - 127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (161 KB) |  | HTML iconHTML  

    As today's process technologies are combined with steadily increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities in combination with the smaller feature sizes requires that we now address defect mechanisms that safely could be more or less ignored in earlier technology nodes. Scan based delay fault testing (AC-scan) fills a large gap in defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in (Rajski, et al.,2003). Our scheme is very diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Stanojevic et al., 2005 and Leininger et al., 2005). Yet, the compactor has comparable performance to other schemes (Rajski et., 2003) when it comes to 'X' tolerance and aliasing View full abstract»

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  • A Novel Methodology for Functional Test Data Compression

    Page(s): 128 - 135
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (159 KB) |  | HTML iconHTML  

    This paper presents a novel approach for compressing functional test data in automatic test equipment (ATE). A practical technique is presented for 2 dimensional (2D) reordering of test data in which additionally to test vector reordering, column reordering is also applied. An ATE based approach to extract the original test vectors from the 2D ordered data is presented. The advantage of the approach is substantiated using the figure of merit of entropy for the 2D ordered test data of ISCAS benchmark circuits View full abstract»

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  • Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters

    Page(s): 136 - 144
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (166 KB) |  | HTML iconHTML  

    A fixing-shifting encoding (FSE) method is proposed to reduce test cost of IP cores. The FSE method reduces test cost by supporting multiple-mode loading test data, i.e., parallel loading, left-direction, and right-direction serial loading for each test slice data. Furthermore, the FSE that utilizes only two test channels can support a large number of internal scan chains and achieve further reduction in test cost by combining with scan chain clustering method. As a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is applicable to IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT. Experimental results for some large ISCAS 89 benchmarks and an industry ASIC design have proven the efficiency of the proposed approach View full abstract»

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  • An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint

    Page(s): 145 - 156
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB) |  | HTML iconHTML  

    A proposed scan chain partitioning scheme considers reduction of test set and test time, and the optimal routing inside each partitioned scan chain. First, two compatible scan cells are searched in input test set. One group of compatible scan cells is included in one partitioned scan chain, while the other group is in the other scan chain. In finding these compatible scan cells, the group-based approach is employed since it provides more optimal routing solution among the compatible scan cells in each of these two scan chains. After these two scan chains are filled with compatible scan cells, they are able to share one of two compatible columns in input test set only during the shift-in process. Therefore, one of two compatible columns can be omitted from input test set and the scan operation. Results with ISCAS'89 benchmark circuits show that proposed method could reduce test data volume by 25-33% compared with a normal multiple scan design View full abstract»

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  • Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC

    Page(s): 157 - 165
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    This paper discusses a defect tolerant and energy economized computing array for the DSP plane of a 3D heterogeneous system on a chip. We present the J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. The advantages of this approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. Moreover, many of the advanced algorithms, including the independent component analysis, can be systolically mapped to it. The paper discusses these coarse-grain cells in light of a new concept, namely multi-granularity, which simultaneously facilitates defect tolerance and reconfigurability. In particular, it is shown that the multipliers in these J-platform cells can benefit from an innovative block. Called multiplier building block (MBB), it can be used for defect tolerance as well as for configuring larger multipliers, thereby enhancing the yield and computational flexibility. An application example relating to defect tolerant visible sensors is described. We also discuss energy economization through the use of sleep transistor networks and multi-hop communication. The ultimate goal is to build such 3D heterogeneous sensor nodes with integrated processing and communications capability, and with provision for defect tolerance on the sensor plane as well as the multiple processing planes View full abstract»

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  • Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost

    Page(s): 166 - 174
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (162 KB) |  | HTML iconHTML  

    Embedded memory yield dominates manufacturing yield of the chip and yield enhancement techniques for embedded memories are important for entire SoC yield increases. Lasers fuses and anti fuses are two commonly used mechanisms for hard repair and they consume a lot of area. Analysis based upon yield prediction methods as well as silicon yield database shows that putting fuse to repair all the memories on the chip is not worth the expense, when only few fuse bits are needed. In this paper, the authors present the background for fuse reduction (cost analysis) and propose methodology to compress total number of fuses to repair the memories such that cost reduction through hard repair circuitry is maximized. The idea is to take into consideration factors like memory yield, fuse yield and repair logic yield, together with the number of memories on chip, to finally decide the fuse compression ratio View full abstract»

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  • Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems

    Page(s): 175 - 183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (187 KB) |  | HTML iconHTML  

    Unlike conventional disk array systems such as redundant arrays of independent disks (RAID), distributed storage systems do not require a central controller for a group of disk drive. This decentralized structure avoids a single point of failure as well as bottlenecks in data transfers. The structure should therefore be suitable for dependable, large-scale storage systems. This paper proposes new distributed erasure correction algorithms suitable for the distributed storage systems, and also proposes new classes of triple-erasure correcting codes designed using combinatorial theory such as the Steiner triple system. The authors briefly evaluate the proposed coding method in terms of the number of check disks, the number of disk accesses, and the mean time to data loss (MTTDL). The evaluation demonstrates that the proposed codes require fewer check disks than those in disk mirroring. The proposed erasure correction algorithms also require fewer disk accesses than erasure correction using Reed-Solomon codes. For a large storage system with 400 information disks, the proposed coding method with 37 check disks increases the MTTDL from 0.10 years to 167 years View full abstract»

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  • Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique

    Page(s): 184 - 196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB) |  | HTML iconHTML  

    Two modified triple modular redundancy (TMR) structures based on asynchronous circuit technique are proposed in this paper. Double modular redundancy (DMR) structure uses asynchronous C element to output and keep the correct value of two redundant storage cells. Temporal spatial triple modular redundancy structure with DCTREG (TSTMR-D) uses explicit separated master and slave latch structure of de-synchronous pipeline. Three soft error tolerant 8051 cores with DMR, TMR and TSTMR-D respectively are implemented in SMIC 0.35mum process. Fault injection experiments are also included. The experiment results indicate that DMR structure has a relatively low overhead on both area and latency than TMR, while tolerances SEUs in sequential logic. TSTMR-D structures can tolerance soft errors in both sequential logic and combinational logic with reasonable area and latency overhead View full abstract»

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