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Electronics Manufacturing Technology Symposium, 1995. 'Manufacturing Technologies - Present and Future', Seventeenth IEEE/CPMT International

2-4 Oct. 1995

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Displaying Results 1 - 25 of 86
  • Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (456 KB)
    Freely Available from IEEE
  • Manufacturing ownership through process re-engineering

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    Summary form only given. This paper explains the process being used at the IBM electronic card and test facility in Austin, Texas to gain ownership and commitment through the involvement of manufacturing personnel in process re-engineering. The approach is simple and straight-forward, encompassing shared vision and values, organization, staffing, roles and responsibilities, measurements and the ma... View full abstract»

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  • Electrical performance trade-offs in ball grid array package designs

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB)

    Summary form only given, as follows. Many new types of ball grid array packages have been introduced or proposed in the last year as alternatives to PQFPs and PGAs. These include single and multilayer configurations for both plastic and metal BGAs based on a variety of material and process technologies. A commonly claimed advantage of all these BGAs is improved electrical performance. With continu... View full abstract»

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  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (145 KB)
    Freely Available from IEEE
  • Properties of thin layers of Sn62Pb36Ag2

    Publication Year: 1995, Page(s):502 - 507
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    The increasing miniaturisation of surface mount devices(SMD) reveals some new questions concerning the reliability of solder joints. The components become larger and the solder joints smaller. Especially the thickness mainly influences the mean lifetime of surface mount technology (SMT) solder joints, where micro-fracture and damage evolve under thermomechanical cycling. When the electrical power ... View full abstract»

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  • Technology/strategy management issues for semiconductor technology

    Publication Year: 1995, Page(s):495 - 501
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    For more than forty years continuous improvements in semiconductor technology have driven major performance and value for money improvements into a broad range of industries. In particular both sold state memory and microprocessors have been major benefactors from design and process improvements and contributors to this widespread success and penetration of microelectronics into our lives. The res... View full abstract»

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  • The impact of single-wafer processing on fab cycle time

    Publication Year: 1995, Page(s):488 - 494
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    Rapid thermal processing is already the convention for processes such as silicide annealing, and is being studied as an alternative for virtually every other thermal process in modern CMOS process flows. Single-wafer cleaning is also a broad area of research and development, both in industry and academia, although single-wafer cleaning is not as mature a technology as rapid thermal processing. Thi... View full abstract»

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  • Laser micromachining of through via interconnects in active die for 3D multichip module

    Publication Year: 1995, Page(s):120 - 126
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB)

    One method to increase density in integrated circuits (IC) is to stack die to create a 3D multichip module (MCM). In the past, special post wafer processing was done to bring interconnects out to the edge of the die. The die were sawed, glued, and stacked. Special processing was done to create interconnects on the edge to provide for interconnects to each of the die. These processes require an IC ... View full abstract»

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  • A novel structure to realize crack-free plastic package during reflow soldering process-development of CSS (chip side support) package

    Publication Year: 1995, Page(s):310 - 317
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    Reports a novel structure of a plastic package without a die-pad whereby adhesion strength is improved and thermal stress reduced. The non-die-pad structure has been realized by the chip side support (CSS) method. Furthermore, this paper describes the derivation of an equation that can be used as a criterion for judging package cracking or delamination by comparing the shear strength with the shea... View full abstract»

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  • Alternative facility layouts for semiconductor wafer fabrication facilities

    Publication Year: 1995, Page(s):384 - 388
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Examines the performance of several different cellular and functional layouts using simulation models of the different facility designs. The performance measure of interest is the mean time in system or cycle time of lots. Our results show that the presence of unreliable machinery causes the performance of cellular layouts to deteriorate, while the presence of significant setup times improves thei... View full abstract»

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  • Batchless factory concept for very short cycle time semiconductor manufacturing

    Publication Year: 1995, Page(s):486 - 487
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    The focus of this paper is a processing concept that moves the thermal processing steps out of the semiconductor fabrication facility, dramatically simplifying the front end of line processing and facilitating single wafer processing to potentially achieve a very short manufacturing process cycle time. In the batchless factory concept wafers would be preprocessed before entering the semiconductor ... View full abstract»

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  • Solder bumping through Super Solder

    Publication Year: 1995, Page(s):1 - 4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    Flip chip mounting technology is currently being considered for use in consumer information equipment, and industry is waiting for the establishment of solder bump forming technology as an essential constituent of flip chip (FC) mounting technology. At the present, however, no bump forming technology offers a combination of simple process and low cost. Furukawa Electric has developed a lattice sub... View full abstract»

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  • Electrical performance analysis of a three-dimensional package

    Publication Year: 1995, Page(s):112 - 119
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Three-dimensional packaging is considered to offer a solution for high packaging density and enhanced electrical performance, which are required for the present and future electronic systems. A new type of three-dimensional package was recently developed. These were named “memory cubes”, in which thin small outline J-leaded packages or thin quad flat J-leaded packages were stacked, and... View full abstract»

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  • Development of 0.5 mm thick small outline packages

    Publication Year: 1995, Page(s):304 - 309
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Two types of 0.5 mm thick UTSOP's (Ultra Thin Small Outline Packages) were developed, a conventional type with die pad, and a LOC(Lead on Chip) type. In both types, the die pad or the backside of the chip is exposed to the bottom of the package. In order to accomplish 0.5 mm thickness of the package, high strength alloy lead frames with 100 μm thickness, and low-loop wire-bonding technology wer... View full abstract»

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  • Flux activity evaluation using the wetting balance

    Publication Year: 1995, Page(s):344 - 350
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    The selection of soldering flux plays a critical role in determining the manufacturing yield and product reliability of printed circuit board assemblies. Fluxes are used to remove oxides and other contaminants on the component leads and the pads on the printed circuit board. They also assist in the transfer of heat. The selection of flux should depend on properties such as its ability to remove th... View full abstract»

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  • Effective modeling of factory throughput times

    Publication Year: 1995, Page(s):377 - 383
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Describes an effective approach to TPT modeling. Though this approach can be used in any factory, our focus here is limited to predicting TPT in a semiconductor wafer fabrication facility. We describe an abstract simulation that runs very quickly on standard PCs and is based on a model that focuses on the factors that have a major influence on TPT. The simple model includes machine assignments and... View full abstract»

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  • Development of integrated process control system utilizing neural network for plasma etching

    Publication Year: 1995, Page(s):218 - 223
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The purpose of this study is to provide the integrated process control system utilizing neural network modeling, to search for the appropriate choice of control input, and to keep the process output within the desired range in the real etch process. Variations in the process output are classified as the drift and the shift. The drift is caused by a natural noise that changes over a period of time ... View full abstract»

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  • Run by run (generalized SPC) control of semiconductor processes on the production floor

    Publication Year: 1995, Page(s):60 - 64
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Multiple linear response surface methodology coupled with run by run (generalized SPC) control has been applied at Delco Electronics to a high volume production epitaxy deposition process. This resulted in nearly a 1.8× improvement in process capability for thickness control. This was achieved by interfacing an IBM compatible 486 computer to Gemini II epi reactors, translating Sun workstatio... View full abstract»

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  • Ericsson's VLSI mini-fab strategy; low volume VLSI fab to ensure short time to market for Ericsson telecom systems and products

    Publication Year: 1995, Page(s):482 - 485
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    Ericsson adopted a rather different approach when it planned a submicron fab at its Kista site in Sweden. Wafer manufacturing volumes were less important than time factors, since the principal role of the fab is to reduce the design and manufacturing lead times for the complex ASICs needed in the company's telecommunications products and systems. In this paper, the author describes Ericsson's rath... View full abstract»

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  • Reliability of soldered silicon devices on copper alloys

    Publication Year: 1995, Page(s):148 - 157
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5952 KB)

    Functional reliability of power ICs is dependent on the integrity of IC/heat transfer joint area. Any major reactions during soldering on the heat-spreader and transport of reaction products to the silicon/metal interface have an adverse effect on the IC performance. The robustness of silicon backside metallization and the selection of metallization scheme can prevent the solder reactions at the s... View full abstract»

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  • Laser ablation forward deposition of metal lines for electrical interconnect repair

    Publication Year: 1995, Page(s):176 - 178
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    Flat-panel display interconnect repair requires an open air (vacuum-system-free), environmentally friendly, dry process with a minimum number of steps. The Laser Ablation Forward Deposition (LAFD) approach described in this paper offers such advantages with the potential for low cost. The Laser Ablation Forward Deposition technique transfers metallic film from a glass support to a nearby substrate... View full abstract»

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  • Applying DFM in the semiconductor industry

    Publication Year: 1995, Page(s):438 - 441
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    In many industries, design for manufacture (DFM) has become a central concept for survival in increasingly competitive global markets. One of the important lessons of DFM is that consideration of manufacturing issues early in the design phase can reap substantial benefits. These include savings in set-up and production costs, reduction of lead times required to bring a new product to market, reduc... View full abstract»

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  • High-density build-up wiring boards using conventional printed wiring boards process

    Publication Year: 1995, Page(s):96 - 102
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1640 KB)

    To keep pace with the downsizing of electronic communication equipment and acceleration of transmission speed, the printed wiring board (PWB) must have finer wiring and thinner plating. While various means have been developed to produce these high density boards, we have also developed a process that enables the production of upper and lower surface conductor interconnections on Build-Up substrate... View full abstract»

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  • Utilizing production data to increase factory capacity

    Publication Year: 1995, Page(s):292 - 294
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The amount of data that is captured by any semiconductor manufacturing shop floor control system is massive. Unfortunately, much of the production data that is collected is rarely used. One way to determine a factory's capacity is to determine the capacity of the factory's bottleneck tools. If the capacity of the bottleneck tools can be increased, then the factory's capacity will also increase. Th... View full abstract»

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  • Laser-diode based soldering system with vision capabilities

    Publication Year: 1995, Page(s):324 - 328
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Describes the design and construction of an experimental prototype laser soldering workstation. The key components of this system are a 15-watt fiber-coupled laser diode array, and a PC vision system. The vision system is used for alignment of the part to be soldered and for observation of the laser-induced reflow. First, the paper describes the major components of the prototype soldering workstat... View full abstract»

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