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Electronics Manufacturing Technology Symposium, 1995. 'Manufacturing Technologies - Present and Future', Seventeenth IEEE/CPMT International

Date 2-4 Oct. 1995

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  • Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'

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    Freely Available from IEEE
  • Lead free interconnect materials for the electronics industry

    Page(s): 238 - 244
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    Considerable development and research has been conducted over the last 25 years by many areas of manufacturing to reduce the use of lead and to limit human exposure to lead and products containing lead. Small levels of lead can damage the nervous system of children. Major sources of lead are ingested paint, 75%, and drinking water, 20%. The elimination of lead from all manufacturing products, whether through legislation or through tax incentives, will have a significant impact on the electronic interconnect technologies. In 1993 the National Center for Manufacturing Sciences (NCMS), a not-for-profit cooperative research consortium of more than 215 U.S. North American manufacturers, established multi-year programs. Lead Free Solder Project (LFSP) and Conductive Polymer Interconnect Project (CPIP) involving participants from industry, academia, and national laboratories. The objective of these programs is to identify lead free solder alternative replacement(s) and conductive polymeric materials for lead bearing solders in the electronics industry. The new materials must meet the interconnect performance requirements at operating environments ranging from-55 to +180 degrees centigrade. Numerous lead free alloy solders, each exhibiting unique properties, have been used by electronic manufacturers in specific applications. The major usage of conductive adhesives has been in consumer electronics and children's toys. Before any of these new lead free materials can be applied to the widely diverse electronics industry considerable research and development is required. The NCMS programs involve a study of the material properties, manufacturability, modeling and reliability predictions, economic impact, and toxicological properties View full abstract»

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  • A robust metric for measuring within-wafer uniformity

    Page(s): 396 - 401
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    A robust metric for measuring within-wafer uniformity has been developed and compared to the traditional SNR metric. The new statistic, referred to as the integration statistic, is based on the integration of the volumetric error between the target and the actual surfaces. Comparison with the traditional SNR uniformity metric indicates that the integration statistic provides a more consistent estimate of the uniformity for different numbers of measurements and different orientations of those measurements to the uniformity pattern View full abstract»

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  • Run by run control of chemical-mechanical polishing

    Page(s): 81 - 87
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    A prototype hardware/software system has been developed and applied to the control of single wafer chemical-mechanical polishing (CMP) processes. The control methodology consists of experimental design to build response surface and linearized control models of the process, and the use of feedback control to change recipe parameters (machine settings) on a lot by lot basis. Acceptable regression models were constructed for average removal rate and nonuniformity, which are calculated based on film thickness measurement at nine points on 8" blanket oxide wafers. For control, an exponentially weighted moving average model adaptation strategy was used, coupled to multivariate recipe generation incorporating user weights on the inputs and outputs, bounds on the input ranges, and discretization in the machine settings. We found that this strategy successfully compensated for substantial drift in the uncontrolled tool's removal rate. It was also found that the equipment model generated during the experimental design was surprisingly robust; the same model was effective across more than one CMP tool, and over a several month period View full abstract»

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  • Thermomechanical stress-strain hysteresis of Sn-Bi eutectic solder alloy

    Page(s): 263 - 268
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    This study details a thermomechanical testing technique, used in an on-going program, to measure stress-strain hysteresis of solder joints. The apparatus closely approximates the mechanical conditions solder joints experience in electronics packages subjected to cyclic temperature changes. The test assembly is composed of a small load frame, an insert of differing thermal expansion coefficient, and a solder joint. Strain gages on the load frame and a calibration procedure conducted prior to testing allow shearing stress and strain in the solder joint to be obtained during testing. Some thermomechanical deformation behavior of SnBi eutectic solder is reported and discussed View full abstract»

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  • LSM vision gage R&R study

    Page(s): 402 - 409
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    The purpose of this study is to assess whether the laser scanning microscope (LSM) is capable of measuring solder paste height. The LSM projects a scanning laser beam onto the PC board which is deflected around the solder paste deposit. The height of the paste was determined by taking the difference between the highest (top) and lowest (bottom) laser deflection points on and surrounding the paste deposit respectively View full abstract»

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  • Area bonding conductive epoxy adhesives for low cost grid array chip carriers

    Page(s): 422 - 427
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    This paper describes a new type of Z axis epoxy film adhesive, called a_rea b_onding c_onductive (ABC) epoxies, to replace solder and solder balls for surface mounting grid array chip carriers. The ABC adhesives are made by a low cost screen printing process, starting from customer-supplied artwork, so that the conductive epoxy regions are located only at the desired bond pad locations. Reliability data, presented for plastic and LTCC packages attached to FR-4 boards with these adhesives, show better resistance to thermal cycling and thermal shock than soldered packages. This paper also describes a new low cost copper lidded pad array chip carrier, called a Cu-PAC. This uses an ABC epoxy for die and for substrate attach. The Cu-PACs have the potential for major cost savings, size reduction and improved heat removal compared to present molded plastic grid array packages View full abstract»

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  • Mounting technology of BGA-P and BGA-T

    Page(s): 417 - 421
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    The BGA is not as easy to inspect or repair as other package formats. The feasibility of its practical application hinges, therefore, on the condition that its bonding rate and solder defect level is superior to that of the QFP. In order to promote the spread of BGAs, there is a pressing need to establish a process for ensuring high bonding reliability. In this report, we present the mounting test on a BGA-P with 225 pins and a BGA-T with 426 pins. We hope that this information will contribute to spurring the adoption of the BGAs View full abstract»

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  • Technology/strategy management issues for semiconductor technology

    Page(s): 495 - 501
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    For more than forty years continuous improvements in semiconductor technology have driven major performance and value for money improvements into a broad range of industries. In particular both sold state memory and microprocessors have been major benefactors from design and process improvements and contributors to this widespread success and penetration of microelectronics into our lives. The resulting smaller device dimensions and larger semiconductor wafers have produced the performance benefits. The rate of device dimension reduction seems to be decreasing as we approach the 0.10 to 0.25 micron range, with capital investments approaching $1 billion dollars per facility for the 200 mm wafers increasingly coming into use. Some industry leaders forecast a $2 billion dollar next generation manufacturing facility cost as we approach the year 2000. These challenges threaten the continued expectation of device cost reduction and may herald the maturation (end) of the optical lithography technology based S-curve “family” progress, or change the size and/or scope of the wafer manufacturing facility need to achieve good economics. This summary paper highlights issues, trends, industry activities and needs View full abstract»

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  • High-density build-up wiring boards using conventional printed wiring boards process

    Page(s): 96 - 102
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    To keep pace with the downsizing of electronic communication equipment and acceleration of transmission speed, the printed wiring board (PWB) must have finer wiring and thinner plating. While various means have been developed to produce these high density boards, we have also developed a process that enables the production of upper and lower surface conductor interconnections on Build-Up substrates using metallic via-posts. The features of the via-post type boards are as follows: (a) it is possible to make them high density, because of the very small via-post developed; (b) Any type of resin can be used; (c) Stacks are possible; that is, mounting a post directly above another post; (d) wirebonding to a pad is possible by use of the via-post. We developed high density, high quality, lower costing, and easier to enable via-post type Build-Up PWBs for Card PCs using conventional PWB equipment. The following is a report on our investigation and the result of trial PWB evaluations View full abstract»

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  • Temperature accelerated life test (ALT) at the circuit board level

    Page(s): 158 - 165
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    The purpose of ALT (Accelerated life test) lies in evaluating the failure rate of an item by obtaining expedient information on the lifetest distribution of a material or product by applying stress levels more severe than those specified by standard conditions, in order to greatly reduce the time needed to observe stress reactions or to magnify such reactions within a given time frame so as to ultimately reduce the time, cost, and effort required to evaluate the item. It is not difficult to determine the failure rate at the component level using ALT. However failure rate prediction at the circuit board level is difficult with ALT, because various electrical parameters at the component level have to be taken into account, and determination of accelerated factors is not so easy. This paper describes temperature ALT conducted for the purpose of estimating failure rates and analyzing forms of failure during operation at the circuit board level of a telecommunication system. In this method, a temperature higher than the operational temperature of an item was applied to it in order to generate failure rate data within a short period of time to estimate the failure rate during actual system operation. We proposed systematically the test temperature, test duration, and the sample size for high temperature ALT of the circuit board of a telecommunication system View full abstract»

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  • Nitrogen reflow ovens: the effect exit temperature has on benzotriazole coated copper boards

    Page(s): 329 - 336
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    Reports on the comparisons made of three nitrogen capable ovens. The ovens range in size and price representative of common market offerings. The ovens compared were forced convection type and oxygen concentrations (02 ppm) were set at comparable levels. All of the ovens have some exit cooling capability (nitrogen contained). Cards exiting the oven may be oxidized to different levels, dependent on the card's temperature. The level of oxidation sustained on the card's second side due to the first reflow operation and/or any intermediate process steps, e.g., misprinted paste strips, should be known. Downstream solderability and/or processability operations may be affected. Results from this work were used to provide process engineering a quantifiable way of making capital expense decisions View full abstract»

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  • Designing response surface model based Run by Run controllers: a new approach

    Page(s): 210 - 217
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    This paper presents a framework for carrying out robust Run by Run (RbR) control via a set-theoretic approach. In particular the RbR controller developed tries to minimize the worst case performance of the plant. This gives us a methodology to handle uncertainty. An interesting consequence of using the set valued approach is that now we can relax the assumptions made on the statistics of the noise. Hence, we can also deal with non-Gaussian and correlated noise. We provide results comparing the performance of the controller to a recursive least squares based controller View full abstract»

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  • Single-wafer processing: opportunities and challenges

    Page(s): 480 - 481
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    As we approach the 0.25-μm technology node and 300-mm wafer manufacturing, the industry is challenged to develop new thermal processing tools to replace traditional large-batch furnaces. The most technically challenging process for practical single-wafer implementation is thick oxidation (e.g., for device isolation). In general, the tradeoff between process uniformity, yield and throughput, for each thermal process, will be reflected in the single-wafer vs. minibatch configuration of these tools. The last bastion of large batch processing will probably be wet immersion cleanups, which are less sensitive to the “device- and wafer-scaling pressures”. However, the migration of thermal processing away from large batches will exert “logistical pressure” on the associated cleanups to follow suit. Additional motivations for single-wafer processing are discussed View full abstract»

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  • Impact of minienvironments on facilities cost

    Page(s): 286 - 291
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    The Strategic Future Fab Study considered minienvironments as an alternative to more traditional “ballroom” full filter ceiling design configurations. The study determined that there were real cost savings associated with implementing minienvironment use. Tangible savings in the area of HVAC equipment first cost, ongoing energy cost reduction, and clean room garment cost saving, were identified and dollar values for the specific facilities under consideration assigned. Additional factors such as facility modification flexibility due to tool isolation, process isolation permitting varied temperature/humidity conditions to be maintained, simplified process tool electrical/piping design and routing, and increased operator safety were identified without assigning dollar values for savings View full abstract»

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  • Electrical performance trade-offs in ball grid array package designs

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    Summary form only given, as follows. Many new types of ball grid array packages have been introduced or proposed in the last year as alternatives to PQFPs and PGAs. These include single and multilayer configurations for both plastic and metal BGAs based on a variety of material and process technologies. A commonly claimed advantage of all these BGAs is improved electrical performance. With continued increases in clock speed and reductions in noise margins due to voltage scaling, electrical performance will become a driving force for introduction of BGAs in many products. A detailed study of the electrical performance of a selected set of single and multilayer BGA packages was completed. The different package models were generated using a field solver and analyzed for their signal integrity characteristics using SPICE. This includes an analysis of how closely the output signals and the input signals match under varying load conditions. The design and performance of the selected BGA packages were then assessed based on initial simulation results, and a set of design guidelines to optimize electrical performance were developed. These design guidelines can then be applied based on product needs. This paper will address the electrical performance and relative complexity and cost factors facing the engineer and suggest optimal choices for the varying load conditions and chip types View full abstract»

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  • A framework for supply chain management in semiconductor manufacturing industry

    Page(s): 47 - 50
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    In this paper, we define the planning problem in semiconductor manufacturing to be that of managing the entire supply chain and discuss the benefits of this global approach as well as the problems associated with implementing it. Finally, we discuss the requirements for a tool that would enable us to manage the entire supply chain. Our approach allows us to model the supply chain as an integrated network and gives us the ability to identify and therefore better manage the constraints in the system, and to understand and model the response and constraint buffers. The benefits of such an approach are the ability to reflect the global (company wide) impact of local decisions, advance warning of potential problems, and the speed of planning and execution View full abstract»

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  • Ericsson's VLSI mini-fab strategy; low volume VLSI fab to ensure short time to market for Ericsson telecom systems and products

    Page(s): 482 - 485
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    Ericsson adopted a rather different approach when it planned a submicron fab at its Kista site in Sweden. Wafer manufacturing volumes were less important than time factors, since the principal role of the fab is to reduce the design and manufacturing lead times for the complex ASICs needed in the company's telecommunications products and systems. In this paper, the author describes Ericsson's rather unusual strategy for microelectronics sourcing View full abstract»

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  • A novel structure to realize crack-free plastic package during reflow soldering process-development of CSS (chip side support) package

    Page(s): 310 - 317
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    Reports a novel structure of a plastic package without a die-pad whereby adhesion strength is improved and thermal stress reduced. The non-die-pad structure has been realized by the chip side support (CSS) method. Furthermore, this paper describes the derivation of an equation that can be used as a criterion for judging package cracking or delamination by comparing the shear strength with the shear stress. The equation for shear stress can be estimated by the finite element method View full abstract»

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  • COB and COC for low cost and high density package

    Page(s): 109 - 111
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    Today, portable electronic devices have many more functions than the same type of nonportable products had a few years ago. As the similitude rules are no longer valid when designers are faced with miniaturization, it is necessary to find and develop new approaches for the packaging and the interconnections of the integrated circuits. By using a well mastered Chip-On-Board (COB) technology in association with a very accurate die attach process, it is possible to offer an inexpensive Chip-On-Chip (COC) solution to the engineers who need a 3D assembly for a higher level of miniaturization View full abstract»

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  • Development of 0.5 mm thick small outline packages

    Page(s): 304 - 309
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    Two types of 0.5 mm thick UTSOP's (Ultra Thin Small Outline Packages) were developed, a conventional type with die pad, and a LOC(Lead on Chip) type. In both types, the die pad or the backside of the chip is exposed to the bottom of the package. In order to accomplish 0.5 mm thickness of the package, high strength alloy lead frames with 100 μm thickness, and low-loop wire-bonding technology were used. The chip thicknesses in the conventional type, and the LOC type were 200 μm and 300 μm, respectively. Because, from the package structural point of view, the top half and the bottom half of the packages were unbalanced in terms of thermal expansion coefficients, the warpage of the packages was an expected problem. However, the warpage was reduced below 40 μm by the material changes and the modification of lead frame design. Various molding compounds with different characteristics, and two kinds of lead frame materials were tried. Package reliability of the UTSOP's were evaluated View full abstract»

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  • Model-based product quantity control

    Page(s): 389 - 395
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    A methodology for building Response Surface Models (RSM) for product quantity control of integrated circuits is presented. A simulation based approach is used to build the models. The work focuses on controlling the number of wafer starts devoted to each product based on in-line, in-situ and Wafer-level Electric Tests (WET). Real-time decisions are made depending on the demand for a particular performance bin View full abstract»

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  • New methodology of dynamic lot dispatching: required turn rate

    Page(s): 187 - 189
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    In a semiconductor manufacturing fab with production-to-order type operation, hundreds of devices and various processes are managed. To provide short cycle time and precise delivery to satisfy customers' expectation is always the major task. The difficulties encountered are complex process and product mix, unscheduled machines down time and equipment arrangement. How to dispatch lots effectively has become a very important topic in handling manufacturing. A dispatching algorithm named “Required Turn Rate (RTR)” is developed. According to the level of current wafers in process (WIP), RTR algorithm revises the due date for every lot to satisfy the demand from Master Production Scheduling (MPS). Further to calculate the required turn rate of each lot based on process flow to fulfill the delivery requirement. RTR algorithm determines not only due date and production priority of each lot, but also provides required turn rate for local dispatching. Therefore, local dispatching systems of each working area will dispatch the lots by using required turn rate to maximize output and machines utilization View full abstract»

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  • Managing for a future [electronics manufacturing]

    Page(s): 36 - 37
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    The manufacturing enterprise is the integration of the functions and activities required to make a product. It bridges from concept to end of life of a product and focuses on requirements related to the interactions among functional parts and ultimately their integration. The new manufacturing enterprise continues to depend on engineering; however, it is increasingly driven by information technology and is highly dependent on effective management. The author considers the factors that managers in manufacturing must take into account: the electronic systems, technology roadmaps, information technology, and the dominant competitive advantage View full abstract»

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