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2006 Formal Methods in Computer Aided Design

12-16 Nov. 2006

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  • Formal Methods in Computer Aided Design [Cover]

    Publication Year: 2006
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  • Formal Methods in Computer Aided Design-Title

    Publication Year: 2006, Page(s):i - iii
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  • Formal Methods in Computer Aided Design-Copyright

    Publication Year: 2006, Page(s): iv
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  • Formal Methods in Computer Aided Design - TOC

    Publication Year: 2006, Page(s):v - vi
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  • Preface

    Publication Year: 2006, Page(s): vii
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  • Organizing Committee

    Publication Year: 2006, Page(s): viii
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  • Program Committee

    Publication Year: 2006, Page(s): viii
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  • Referees

    Publication Year: 2006, Page(s): ix
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  • Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning

    Publication Year: 2006, Page(s):3 - 10
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    Pervasive logic is a broad term applied to the variety of logic present in hardware designs, yet not a part of their primary functionality. Examples of pervasive logic include initialization and self-test logic. Because pervasive logic is intertwined with the functionality of chips, the verification of such logic tends to require very deep sequential analysis of very large slices of the design. Fo... View full abstract»

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  • Post-reboot Equivalence and Compositional Verification of Hardware

    Publication Year: 2006, Page(s):11 - 18
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    We introduce a finer concept of a hardware machine, where the set of post-reboot operation states is explicitly a part of the FSM definition. We formalize an ad-hoc flow of combinational equivalence verification of hardware, the way it was performed over the years in the industry. We define a concept of post-reboot bisimulation, which better suits the hardware machines, and show that a right form ... View full abstract»

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  • Synchronous Elastic Networks

    Publication Year: 2006, Page(s):19 - 30
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (419 KB) | HTML iconHTML

    We formally define - at the stream transformer level - a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove fundamental compositionality results. The paper contributes to bridging the gap between the theory of latency-insensitive systems and the correct implementation of efficient co... View full abstract»

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  • Finite Instantiations for Integer Difference Logic

    Publication Year: 2006, Page(s):31 - 38
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (223 KB) | HTML iconHTML

    The last few years have seen the advent of a new breed of decision procedures for various fragments of first-order logic based on propositional abstraction. A lazy satisfiability checker for a given fragment of first-order logic invokes a theory-specific decision procedure (a theory solver) on (partial) satisfying assignments for the abstraction. If the assignment is found to be consistent in the ... View full abstract»

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  • Tracking MUSes and Strict Inconsistent Covers

    Publication Year: 2006, Page(s):39 - 46
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (259 KB) | HTML iconHTML

    In this paper, a new heuristic-based approach is introduced to extract minimally unsatisfiable subformulas (in short, MUSes) of SAT instances. It is shown that it often outperforms competing methods. Then, the focus is on inconsistent covers, which represent sets of MUSes that cover enough independent sources of infeasibility for the instance to regain satisfiability if they were repaired. As the ... View full abstract»

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  • Ario: A Linear Integer Arithmetic Logic Solver

    Publication Year: 2006, Page(s):47 - 48
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (118 KB) | HTML iconHTML

    In this paper we describe our solver for systems of linear integer arithmetic logic. Such systems are commonly used in design verification applications and are classified under satisfiability modulo theories (SMT) problems. Recognizing the fact that in many such applications the majority of atoms are equalities or integer unit-two-variable inequalities (UTVPIs), we present a framework that integra... View full abstract»

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  • Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis

    Publication Year: 2006, Page(s):49 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (97 KB) | HTML iconHTML

    Despite the many improvements in the speed and robustness of DPLL-based SAT solvers, we still lack a thorough understanding of the working mechanisms and dynamic behaviour of these solvers at run-time. In this paper, we present TIGERDISP, a tool designed to allow researchers to visualize the dynamic behaviour of modern DPLL solvers in terms of time-dependent metrics such as decision depth, implica... View full abstract»

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  • Over-Approximating Boolean Programs with Unbounded Thread Creation

    Publication Year: 2006, Page(s):53 - 59
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (243 KB) | HTML iconHTML

    This paper describes a symbolic algorithm for over-approximating reachability in Boolean programs with unbounded thread creation. The fix-point is detected by projecting the state of the threads to the globally visible parts, which are finite. Our algorithm models recursion by over-approximating the call stack that contains the return locations of recursive function calls, as reachability is undec... View full abstract»

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  • An Improved Distance Heuristic Function for Directed Software Model Checking

    Publication Year: 2006, Page(s):60 - 67
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB) | HTML iconHTML

    State exploration in directed software model checking is guided using a heuristic function to move states near errors to the front of the search queue. Distance heuristic functions rank states based on the number of transitions needed to move the current program state into an error location. Lack of calling context information causes the heuristic function to underestimate the true distance to the... View full abstract»

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  • Liveness and Boundedness of Synchronous Data Flow Graphs

    Publication Year: 2006, Page(s):68 - 75
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (266 KB) | HTML iconHTML

    Synchronous data flow graphs (SDFGs) have proven to be suitable for specifying and analyzing streaming applications that run on single- or multi-processor platforms. Streaming applications essentially continue their execution indefinitely. Therefore, one of the key properties of an SDFG is liveness, i.e., whether all parts of the SDFG can run infinitely often. Another elementary requirement is whe... View full abstract»

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  • Model Checking Data-Dependent Real-Time Properties of the European Train Control System

    Publication Year: 2006, Page(s):76 - 77
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (94 KB) | HTML iconHTML

    The behavior of embedded hardware and software systems is determined by at least three dimensions: control flow, data aspects, and real-time requirements. To specify the different dimensions of a system with the best-suited techniques, the formal language CSP-OZ-DC (Hoenicke and Maier, 2005) integrates communicating sequential processes (CSP) (Hoare, 1985), Object-Z (OZ) (Smith, 2000), and duratio... View full abstract»

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  • Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee

    Publication Year: 2006, Page(s):81 - 88
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    We illustrate how to employ metacircular assume/guarantee reasoning to reduce the verification complexity of finite instances of protocols for safety, using nothing more than an explicit state model checker. The formal underpinnings of our method are based on establishing a simulation relation between the given protocol M, and several overapproximations thereof, Mtilde1,..., Mtilde View full abstract»

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  • Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling

    Publication Year: 2006, Page(s):89 - 96
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (247 KB) | HTML iconHTML

    In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in previous years, we support unbounded model checking based on symbolic representations of characteristic functions. Among others, our method is based on an advanced and-inverter graph (AIG) implementation, quantifier scheduling, an... View full abstract»

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  • Symmetry Reduction for STE Model Checking

    Publication Year: 2006, Page(s):97 - 105
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (815 KB) | HTML iconHTML

    In spite of the tremendous success of STE model checking one cannot verify circuits with arbitrary large number of state holding elements. In this paper we present a methodology of symmetry reduction for STE model checking, using a novel set of STE inference rules. For symmetric circuit models these rules provide a very effective reduction strategy. When used as tactics, rules help decompose a giv... View full abstract»

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  • Thorough Checking Revisited

    Publication Year: 2006, Page(s):106 - 116
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB) | HTML iconHTML

    Previous years have seen a proliferation of 3-valued models for capturing abstractions of systems, since these enable verifying both universal and existential properties. Reasoning about such systems is either inexpensive and imprecise (compositional checking), or expensive and precise (thorough checking). In this paper, we prove that thorough and compositional checks for temporal formulas in thei... View full abstract»

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  • Optimizations for LTL Synthesis

    Publication Year: 2006, Page(s):117 - 124
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (386 KB) | HTML iconHTML

    We present an approach to automatic synthesis of specifications given in linear time logic. The approach is based on a translation through universal co-Buchi tree automata and alternating weak tree automata (O. Kupferman and M. Vardi, 2005). By careful optimization of all intermediate automata, we achieve a major improvement in performance. We present several optimization techniques for alternatin... View full abstract»

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  • From PSL to NBA: a Modular Symbolic Encoding

    Publication Year: 2006, Page(s):125 - 133
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (483 KB) | HTML iconHTML

    The IEEE standard property specification language (PSL) allows to express all omega-regular properties mixing linear temporal logic (LTL) with sequential extended regular expressions (SEREs), and is increasingly used in many phases of the hardware design cycle, from specification to verification. Many verification engines are able to manipulate nondeterministic Buchi automata (NBA), that can repre... View full abstract»

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