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IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)

Date 11-13 Sept. 2006

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  • IEEE 17th International Conference on Application-specific Systems, Architectures and Processors

    Publication Year: 2006, Page(s): c1
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  • IEEE 17th International Conference on Application-specific Systems, Architectures and Processors - Title

    Publication Year: 2006, Page(s):i - iii
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  • IEEE 17th International Conference on Application-specific Systems, Architectures and Processors - Copyright

    Publication Year: 2006, Page(s): iv
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  • IEEE 17th International Conference on Application-specific Systems, Architectures and Processors - Table of contents

    Publication Year: 2006, Page(s):v - ix
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  • Message from the Conference Chairs

    Publication Year: 2006, Page(s): x
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  • Conference organizers

    Publication Year: 2006, Page(s): xii
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  • Program Committee

    Publication Year: 2006, Page(s): xiii
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  • External referees

    Publication Year: 2006, Page(s): xiv
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  • Configurable Computing Platforms - Promises, Promises

    Publication Year: 2006, Page(s):3 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (106 KB) | HTML iconHTML

    For some time now, configurable computing has been hailed as the future for application-specific architectures. The purported advantages are well-known: the increasing NRE cost of chip fab is avoided, the same platform can be used for a variety of applications, and implementations can be fixed or upgraded in the field. But in spite of many attempts to move configurable computing platforms into the... View full abstract»

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  • The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines

    Publication Year: 2006, Page(s):5 - 14
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (223 KB) | HTML iconHTML

    Early FPGA researchers understood that FPGAs made possible the creation of a new, flexible, and powerful class of machine - the configurable computing machine (CCM). The earliest CCMs featured rudimentary but significant integrated design, debug, and runtime environments. This paper reviews those environments as well as more recent work using JHDL, designed to investigate how a symbolic hardware d... View full abstract»

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  • Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip

    Publication Year: 2006, Page(s):15 - 18
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (139 KB) | HTML iconHTML

    Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor platform spans multiple design layers, including the application layer, the system software layer, the architecture layer and the micro-architecture layer. For best results, designers have to consider multiple design layers (... View full abstract»

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  • The Molen FemtoJava Engine

    Publication Year: 2006, Page(s):19 - 22
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (110 KB) | HTML iconHTML

    This paper presents the Molen FemtoJava engine that is extended with concepts taken from the Molen polymorphic processor. This allows for the existing FemtoJava to be augmented with reconfigurable hardware with only a single extension of the bytecodes and thereby but still allowing the implementation of arbitrary hardware implementations. Therefore, computationally intensive functions can be moved... View full abstract»

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  • A Generic Multi-Phase On-Chip Traffic Generation Environment

    Publication Year: 2006, Page(s):23 - 27
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (243 KB) | HTML iconHTML

    In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algori... View full abstract»

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  • Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy

    Publication Year: 2006, Page(s):28 - 32
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algori... View full abstract»

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  • NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm

    Publication Year: 2006, Page(s):33 - 38
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Using this algorithm, which we call AntNet routing algorithm, heavy packet traffics are distributed on the chip minimizing the occurrence of hot spots. To evaluate the efficiency of the scheme, the proposed algorithm was co... View full abstract»

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  • Recent Developments in Configurable and Extensible Processors

    Publication Year: 2006, Page(s):39 - 44
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (115 KB) | HTML iconHTML

    There have been some interesting technology developments in the area of configurable and extensible processors in the last few years. This paper outlines some of the most recent technologies that we have been developing at Tensilica, including the role of fixed implementations, automatic generation of application-oriented configurations, and design methodologies including fast functional simulatio... View full abstract»

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  • Software Configurable Processors

    Publication Year: 2006, Page(s):45 - 49
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (125 KB) | HTML iconHTML

    A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configura... View full abstract»

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  • Reconfigurable Hardware and Software Architectural Constructs for the Enablement of Resilient Computing Systems

    Publication Year: 2006, Page(s):50 - 55
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    This paper introduces the concepts underlying a new digital computational fabric called an Elemental Computing Array (ECA). This computation fabric is designed to implement logic resiliency at the very lowest level of design. Current design practices assume the inherent unreliability of silicon dedicated to memory functions, the inherent unreliability of interconnects at the box, board and IC leve... View full abstract»

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  • Application Specific Processing: A Tools Approach

    Publication Year: 2006, Page(s):56 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (305 KB) | HTML iconHTML

    Increased product design cost and risk have been driving the electronics industry to an increased focus on developing "product platforms." When a product platform requires eighteen months to three years to develop at a cost of as much as $500 million, and the cost is expected to be amortized over as many as 100 derivative products over a period of three to five years, the definition of the hardwar... View full abstract»

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  • Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions

    Publication Year: 2006, Page(s):65 - 72
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (419 KB) | HTML iconHTML

    Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefits from bitoriented instructions. We propose the parallel extract (pex) and parallel deposit (pdep) instructions to accelerate compressing and expanding selections of bits. We show that these instructions can be implement... View full abstract»

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  • A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing

    Publication Year: 2006, Page(s):73 - 80
    Cited by:  Papers (18)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    There is a recent surge of interest in single-chip parallel processors. In such machines, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it relative to metrics such a... View full abstract»

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  • Reconfigurable Shuffle Network Design in LDPC Decoders

    Publication Year: 2006, Page(s):81 - 86
    Cited by:  Papers (10)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (178 KB) | HTML iconHTML

    Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check- node units (CNU) is predetermined and optimized for a specific code. However, the m... View full abstract»

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  • 2D-VLIW: An Architecture Based on the Geometry of Computation

    Publication Year: 2006, Page(s):87 - 94
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of functional units connected by a set of local register spread across the matrix. Experiments using the Mediabench and SPECint00 programs and the Trimaran compiler show performance gains ranging from 5% to 63%, when compar... View full abstract»

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  • An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs

    Publication Year: 2006, Page(s):95 - 98
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (150 KB) | HTML iconHTML

    Finite difference (FD) methods are the most prevalent numerical modelling algorithms for evaluating initial or boundary value problems in scientific and engineering applications. Unfortunately, simulating time evolutions for transient physical phenomenon is computationally demanding and data-intensive. This paper introduces an efficient implementation of FD computing engine on FPGA-based reconfigu... View full abstract»

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  • Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions

    Publication Year: 2006, Page(s):99 - 104
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (205 KB) | HTML iconHTML

    We describe several integer function properties which in combination allow direct lookup tables to be reduced in size and structure to simpler lookup trees. Our principal result is a novel table lookup method based on a mapping of a lookup tree to a row-by-column ROM with pre and post processing logic substantially reducing the table size. Our lookup architecture allows common 16-bit integer funct... View full abstract»

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