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Semiconductor Manufacturing, 1995., IEEE/UCS/SEMI International Symposium on

Date 17-19 Sept. 1995

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Displaying Results 1 - 25 of 69
  • Proceedings of International Symposium on Semiconductor Manufacturing

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    Freely Available from IEEE
  • Requirements for contamination control in the G-bit era

    Page(s): 56 - 59
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    In future G-bit DRAM fabrication, the particle density on wafers will be seriously increased. This is because the deposition velocity of particles smaller than 0.1μm drastically increases, and is further accelerated by the electrostatic potential of wafers. The lower limit of the conventional cleanroom cleanliness will be class 0.1-1 level, by dust generation from people. This fact leads us to the minienvironment fab system with automated I/O. In minienvironment systems, however, organic contamination will be a serious problem. Box material, plasticizer and anti-oxidizing agent must be reexamined from the viewpoint of organic contamination control View full abstract»

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  • Control of fine particulate and gaseous contaminants by UV/photoelectron method

    Page(s): 60 - 63
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    In semiconductor manufacturing processes, surface contamination is a very important issue because it decreases the product yield of the LSI. In this study, a new method to remove fine airborne particles and gaseous contaminants in the wafer stocker using a UV/photoelectron method has been investigated. Two kinds of wafer stockers are used for investigating the efficiency of the UV/photoelectron method for controlling (1) particulate and gaseous contaminants under atmospheric conditions and (2) particulate contaminants under low pressure conditions View full abstract»

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  • Analysis of RF plasma using electrical equivalent circuit

    Page(s): 283 - 286
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    The electrical equivalent circuits of RF plasmas have been obtained by use of the accurate probe measurements and HSPICE simulation. Using the obtained equivalent circuits, the electrical characteristics of SF6 and Ar plasmas have been compared. The SF6 plasma displays sinusoidal waveforms of the plasma potential for the capacitive sheath characteristics. On the other hand, in Ar plasma the displacement current through the grounded electrode sheath is comparable to the conduction current. The plasma potential in Ar plasma has significantly higher harmonics for the nonlinear characteristics of the grounded electrode sheath. This analysis method serves as an essential tool for modelling RF plasmas View full abstract»

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  • In-situ plasma cleaning by rotating transverse magnetic field

    Page(s): 32 - 35
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    In the new type of method, the rotating transverse magnetic field is added to the plasma by magnetic coils set around the chamber. Ions and radicals are forcibly pulled out from the plasma up to the inner surface of the chamber by the above magnetic field. In this method, the amount and the energy of ions and radicals can be controlled by the magnetic field intensity so as to be effective in removing the residual product. The etching rate on the inner surface gradually increases in proportion to the magnetic field intensity and becomes larger than that on the electrode at 600 Gauss View full abstract»

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  • Equipment-based course development and implementation: a teamwork approach

    Page(s): 93 - 96
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    Advanced Micro Device's (AMD) Austin Wafer Fabrication Division is undergoing an organizational transformation. AMD has named this transformation the Journey to Excellence (JTE). The Journey involves multiple initiatives supporting increasingly sophisticated technology and fab processes. AMD takes the view that only through continuous efforts to learn new skills and improve will the company meet the challenges of a fiercely competitive and constantly changing business environment. JTE requires that employees across the organization learn continuously View full abstract»

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  • Assessing the environment, safety and health impacts of semiconductor manufacturing at the design and process development stages

    Page(s): 193 - 196
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    The semiconductor industry has traditionally focused on cost, yield and logistics as the primary drivers for decision-making. Environment, safety and health (ESH) issues have resulted in major modifications of manufacturing tools and process steps because they are not routinely considered when making process design and manufacturing choices. ESH impacts are becoming important drivers for the industry; however, to date, they have not been adequately addressed by design and process engineers. To empower process engineers to consider the ESH impacts of their materials and processes at the earliest possible stage, SEMATECH has initiated a project entitled “Design for Environment, Safety and Health” (DFESH). The objective of the SEMATECH project is to provide an integrated DFESH tool set to semiconductor engineers which will evaluate the ESH impacts of their operations. The project will develop the framework, metrics, and appropriate training programs to integrate and facilitate the DFESH tool set's use within the semiconductor engineering and manufacturing process. The foundation of this tool set is a software program, Computerized Assessment of Relative Risk Impacts (CARRI), that assesses the ESH impacts of semiconductor manufacturing processes and associated materials. The tool set will also include a comprehensive ESH cost of ownership model (an extension of the SEMATECH equipment Cost of Ownership model) and a materials/energy balance tool View full abstract»

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  • Evaluation for fab performance using CPO

    Page(s): 288 - 291
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    Tries to evaluate the investment effect ofthe whole factory by grasping the process cost precisely, classifying its structure, and identifying useless cost factors. As an evaluation index, we defined and used the CPO (Cost of Process Ownership), which is the cost per wafer in each process step based on the configuration of equipment installed in the factory and the configuration of product types manufactured there. This index was developed by making some improvements to the CEO (Cost of Equipment Ownership) model. We will report the definition ofthe CPO we are using and some examples of CPO utilization View full abstract»

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  • A methodology for the top-down synthesis of semiconductor process flows

    Page(s): 36 - 40
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    Increasing expense of developing microelectronic manufacturing technology threatens to slow the growth of the electronics industry. This paper describes the progress we have made in developing methodologies and techniques to reduce the cost of designing microelectronic manufacturing flows. Our approach is to partition the task of process flow design into a number of abstraction levels and provide mechanisms to translate between these levels. This approach results in a top-down design methodology where requirements from higher levels of abstraction are successively reduced to lower abstraction levels, while meeting the constraints imposed by the lower levels. The paper enumerates the abstraction levels we have identified so far, and describes the translation mechanisms for a class of process design tasks: modification of an existing flow in response to change in performance requirements. Finally, we briefly describe a design environment that incorporates these ideas View full abstract»

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  • Optimal control processing to increase single wafer reactor throughput in LPCVD

    Page(s): 233 - 238
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    In this paper, Optimal Control theory is applied to develop an alternative process protocol in single wafer reactor LPCVD on patterned wafer in an effort to minimize the processing time, for given final step coverage. To achieve this, the operating conditions are changed during the deposition in a prescribed manner. A simplified control model is developed from the simultaneous one-dimensional Knudsen diffusion and chemical reaction description. The optimal control problem is formulated to find a temperature trajectory yielding the minimum processing time and its solution is computed numerically via a modified variation of extremals method. To demonstrate the concept of optimal control CVD (OCCVD), we consider the thermally activated deposition of silicon dioxide (SiO2) from tetraethylorthosilicate (TEOS). Using the simplified control model, the estimated process time to achieve a 96% step coverage at 98% closure with the constant rate CVD (CRCVD) strategy is 729 seconds. Under the same conditions, the optimal control CVD (OCCVD) process time is 278 seconds. Compared to CRCVD, the process time saved with OCCVD is 62% View full abstract»

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  • Applications of queuing theory and simulation to staffing in the semiconductor clean room environment

    Page(s): 252 - 256
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    A major concern of management in the ultra expensive environment of semiconductor fabs and test floors is optimal utilization of equipment. Proper staffing of clean room operators and maintenance technicians in the manufacturing cells and clusters plays a major role in maximizing equipment utilization and overall throughput. This paper is about a more scientific and pro-active approach to the staffing issue than the classic methods used in the industry. It is TOC (Theory of Constraints) oriented, and designed to improve fab throughput. The models described in this paper were developed by engineers from Tefen USA. To date, they have been adopted by management teams in over 30 different fabs and test sites over the past two years, both in the US and in Europe View full abstract»

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  • Advanced water purification system for sub-half-micron devices

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    Summary form only given. Sub-half-micron devices have fine patterns and thin films. Therefore, the wafer surface is very sensitive to contamination. It is important to keep the wafer surface clean for producing high yield. Purified water plays a significant role in cleaning silicon wafers, because wafers are rinsed with water at the end of every process. So water, the final cleaning agent, has to be highly purified. In current water purifying systems, it is difficult to accomplish the water quality targets for sub-half-micron devices. We developed a new water purification system with three new technological innovations: the ion exchange resins capable of absorbing particles, the unit to ionize silicate impurities, and a two-stage vacuum tower. Optimal organization of these technologies makes it possible to achieve the highest purity with reduced cost. We present the technologies on effective removal of particles, efficient elimination of silicate impurities, and strict control of dissolved oxygen View full abstract»

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  • Impact of tool installation delay on factory ramp-up performance

    Page(s): 108 - 111
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    This study examines the effect of delays in tool installation and qualification on plant performance, specified as discounted cumulative cash flow (DCCF) as the plant is ramped from zero to 20,000 wafer starts/month. Two different ramp strategies are addressed-conservative (24 months) and aggressive (9 months). A specific ramp analysis methodology using a discrete event simulator and cost and yield models, applied to the given assumption set, showed: (1) tool qualification delays impacted investment cost by $34 million/month before the fab breaks even and (2) opting for a 62.5% shorter ramp period effected a 19% reduction in break even time View full abstract»

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  • Integration of costing, yield and performance metrics into the TCAD environment through the combination of DOE and RSM

    Page(s): 266 - 270
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    This paper details a procedure that uses a Total TCAD framework for producing costing and yield response surfaces in addition to the normal performance related information. It uses CALPHURNIA to integrate the simulation and experimental design software into the same environment. In addition to the transfer of data between the two packages, CALPHURNIA also automates the fitting of response surfaces and the creation of response distribution information for the design of robust processes. CAESAR is used to manage the process, device and circuit simulators while RS/1 performs the experimental design role. The costing and yield information is held as formulas within RS/1 which, when combined with the process details, can produce response surfaces of cost information that can be used to help the process designer select the most appropriate operating region View full abstract»

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  • Simulating AMHS performance for semiconductor wafer fabrication

    Page(s): 165 - 170
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    This paper presents the methods and results of modeling and simulating the performance of interbay automated material-handling systems (AMHS) for semiconductor wafer fabrication. Along with a case study of a wafer fab AMHS model, this paper includes an alternate approach to modeling interbay arrivals and delays and explores periods of peak transport demands. A From:To matrix was developed from a detailed simulation model with process flows to represent the hourly demand of bay-to-bay movements. A second From:To matrix was generated to represent the mean transport time of automated material handling. We examine the effect that these matrices have on simulation output and model performance. Three distributions, Constant, Normal, and Exponential, were used with each table. The comparison between detailed and matrix input results included the mean and 95th percentile of delivery times and lot cycle time differentials, as well as car utilization and model execution time. The Exponential distribution provided results closest to those of the detailed model View full abstract»

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  • A multi-pronged approach to defect management

    Page(s): 74 - 79
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    This paper describes a comprehensive, three pronged approach to defect management combining the elements of continuous in-line monitoring, yield loss quantification, and short loop analysis. In-line monitoring provides both a historical defect baseline and a trigger for initiating corrective action in the event of out-of-control situations. Yield loss quantification involving conventional bit mapping or bin mapping partitions the yield loss by defect type and process level. Loop monitors relate trouble spots to root causes, providing a continuous measure of the progress of process and equipment improvement programs View full abstract»

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  • Control of Si surface characteristics by a new etching solution BHF/H2O2

    Page(s): 47 - 50
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    We propose a new buffered hydrofluoric acid (BHF) based solution without surfactants, BHF/H2O2, for Si oxide etching. The BHF/H2O2 solution is an application of the FPM (hydrofluoric acid-hydrogen peroxide mixture) technique reported by Shimono and Tsuiji (1991). By using BHF/H2O2 , low microroughness and high wettability to Si surfaces are achieved without adding any surfactants View full abstract»

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  • Cost of “ad hoc” wafer release policies

    Page(s): 97 - 102
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    Modern manufacturing operations must, on one hand, be very flexible in order to react to the rapidly changing market needs, and on the other hand, as cost effective as possible. The chaotic nature of the market, however, does not allow systematic minimization of manufacturing costs. This paper studies manufacturing flexibility, manufacturing cost trade-off. The analysis is performed using a simulation technique and assuming that the chaotic nature of the market can be modeled by `ad hoc' wafer release policies View full abstract»

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  • A high level treatment of fluorine wastewater to reduce sludge

    Page(s): 201 - 204
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    A novel technique for treating fluorine wastewater has been developed in order to reduce sludge. This technique utilizes the dependence of solubility and adsorption characteristics of Al(OH)3 gel on pH, and uses Al(OH)3 gel itself repeatedly as a fluorine adsorbent. The reclamation process of Al(OH)3 gel involves varying the pH level of its slurry to allow Al(OH)3 gel to desorb fluorine and be dissolved as an aluminate ion. This technique can treat fluorine wastewater to several ppm at low-cost, and reduce the resulting volume of sludge to a level one-thirtieth the amount produced by the conventional treatment method View full abstract»

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  • Low cost production by simplified processing

    Page(s): 277 - 282
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    High throughput and low cost production with 100% yield is strictly demanded for ULSI manufacturing, where a decrease of minimum feature size of devices and an increase of wafer diameter is continuously enhanced for the future. It is realized by simplified processing due to a simplified device structure by introducing new concepts of devices and new materials to Si technology. Simplification of manufacturing processes becomes possible based on a full understanding of process mechanisms in a scientific manner, resulting in a dramatic reduction of process steps View full abstract»

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  • Progressive automation system for semiconductor manufacturing

    Page(s): 127 - 130
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    A new semiconductor manufacturing line was set up and subsequently expanded to meet growing demand. The high yields and short turn-around time necessitated by the most recent technology requires current process equipment to operate at the limit of its capacity. Current factory automation systems must continually evolve to meet these new requirements. The semiconductor manufacturing line consists of several bays, such as those for photolithography and ion implantation. Hitachi has developed a progressive, flexible automation system that can be applied to manufacturing at the bay level. This system has two aims: to reduce operators' working hours by fully automating fabrication and semi-automating the inspection of wafers and equipment, and to increase working intervals between required equipment maintenance. The automation system is realized using in-situ monitoring View full abstract»

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  • The influence of tungsten contamination on electrical characteristics of MOS devices in semiconductor processing

    Page(s): 131 - 135
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    The elimination of dedicated process equipment for silicide brings major benefits on equipment investment and pulsation-less production. To achieve the elimination of silicide dedicated process equipments, the influence and criteria of silicide-metal contamination on the electrical characteristics of ULSI MOS devices should be clarified. In this paper, we investigated the influence and criteria of W contamination on the dielectric breakdown reliability and P-N junction leakage current of MOS devices. In addition, feasibility study for common use of equipment such as furnace, wet cleaning, LP-CVD and plasma etcher is discussed View full abstract»

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  • Global planning at Harris Semiconductor

    Page(s): 18 - 23
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    Harris Semiconductor needed an integrated system to manage its entire supply-chain, especially after tripling its manufacturing capacity to enter the commercial markets. The response was to implement the manufacturing planning system known as IMPReSS, Integrated Manufacturing Production Requirements Scheduling System. It is one of the reasons that Harris has been a consistent world-class 95% or better on time delivery company since 1993 with over 30,000 Finished Goods, a fact that was not lost on the Edelman Committee. IMPReSS won the prestigious management science 1995 Franz Edelman Award for its contribution. IMPReSS is a global information network of distributed databases which includes an optimization-based, semiconductor-specific planning engine that scans the entire pipeline. This paper includes the reasons for choosing a Linear Programming based planning engine from the University of California, Berkeley, known as BPS, over the traditional MRP systems; improvements made to BPS resulting in a new planning engine known as the Harris Planning System, HPS; and the lessons learned by Harris View full abstract»

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  • A hierarchical scheduling system using new weight assigned function in VLSI development lines

    Page(s): 85 - 88
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    Many kinds of scheduling systems have been devised in order to realize an efficient operation of production lines by means of, for example, shortening turn around time (TAT). The VLSI development line requires the following special key items: (1) an efficient lot processing schedule as the number of process steps in given period are maximized; (2) the quick making of a schedule counteracting the alternation of recipes and changes of the period demanded for the experimentation. We developed a new hierarchical scheduling system (DYSCHE II: DYnamic SCHEduling system II) using a Weight Assigned Function (WAF) to overcome the problem of conventional scheduling systems View full abstract»

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