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Proceedings of the Eighth International Symposium on System Synthesis

13-15 Sept. 1995

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  • Proceedings of the Eighth International Symposium on System Synthesis

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (138 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (52 KB)
    Freely Available from IEEE
  • An exact methodology for scheduling in a 3D design space

    Publication Year: 1995, Page(s):78 - 83
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3-dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this... View full abstract»

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  • Multiple-process behavioral synthesis for mixed hardware-software systems

    Publication Year: 1995, Page(s):10 - 15
    Cited by:  Papers (21)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Systems composed of microprocessors interacting with ASICs are necessarily multiple-process systems, since the controller in the microprocessor is separate from any controllers on the ASIC. For this reason, the design of such systems offers an opportunity to exploit not only hardware-software tradeoffs, but concurrency tradeoffs as well. The paper describes an automated iterative improvement techn... View full abstract»

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  • Synthesis of pipelined DSP accelerators with dynamic scheduling

    Publication Year: 1995, Page(s):72 - 77
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    To construct complete systems on silicon, application specific DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units. Emphasis is put on the definition of a controller architecture... View full abstract»

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  • WWW based structuring of codesigns

    Publication Year: 1995, Page(s):138 - 143
    Cited by:  Papers (4)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    This paper describes a codesign environment based on the WWW (World Wide Web) and its implementation. Tool invocations and their respective results are linked using hypertext documents. We show how to configure a WWW browser for spawning design tools and how frequent tasks like documentation generation and retrieval are facilitated. The design flow can be adopted to the given application very easi... View full abstract»

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  • Sensitivity-driven co-synthesis of distributed embedded systems

    Publication Year: 1995, Page(s):4 - 9
    Cited by:  Papers (25)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    Describes a new, sensitivity-driven algorithm for the co-synthesis of real-time distributed embedded systems. Many embedded computing systems are distributed systems: communicating periodic processes executing on several CPUs/ASICs connected by communication links. We use performance estimates to compute a local sensitivity of the design to process allocation. We propose a priority prediction meth... View full abstract»

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  • Industrial experience using rule-driven retargetable code generation for multimedia applications

    Publication Year: 1995, Page(s):60 - 65
    Cited by:  Papers (15)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    The increasing usage of application-specific instruction set processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicated compilers. A rule-driven approach to code generation may have benefits over model-based approaches as the user is not confined to the capabilities supported by the model. However, the sole use of transformation rules ma... View full abstract»

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  • Profiling in the ASP codesign environment

    Publication Year: 1995, Page(s):128 - 133
    Cited by:  Papers (2)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    Automation of the hardware/software codesign methodology brings with it the need to develop sophisticated high-level profiling tools. This paper presents a profiling tool which uses execution profiling on standard C code to obtain accurate and consistent times at the level of individual compound code sections. This tool is used in the ASP Hardware/Software Codesign project. The results from this t... View full abstract»

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  • Clustering for improved system-level functional partitioning

    Publication Year: 1995, Page(s):28 - 33
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    Partitioning of system functionality for implementation among multiple system components, such as among hardware and software components, is becoming an increasingly important topic. Various heuristics can accomplish such partitioning. We demonstrate that clustering can be used to merge pieces of functionality before applying other heuristics, resulting in reduced runtimes with little or no loss i... View full abstract»

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  • Real-time multi-tasking in software synthesis for information processing systems

    Publication Year: 1995, Page(s):48 - 53
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    Software synthesis is a new approach which focuses on the support of embedded systems without the use of operating systems. Compared to traditional design practices, a better utilization of the available time and hardware resources can be achieved, because the static information provided by the system specification is fully exploited and an application-specific solution is automatically generated.... View full abstract»

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  • 1995 high level synthesis design repository

    Publication Year: 1995, Page(s):170 - 174
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    In this paper we briefly describe a set of designs that earn serve as examples for high level synthesis (HLS) systems. The designs vary in complexity from simple behavioral finite state machines to more complex designs such as microprocessors and floating point units. Most of the designs are described in the VHDL language at the behavioral level. We divide the designs into two categories. The firs... View full abstract»

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  • A path-based technique for estimating hardware runtime in HW/SW-cosynthesis

    Publication Year: 1995, Page(s):116 - 121
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    One of the key issues in hardware/software-cosynthesis is precise estimation. The usual local estimation techniques are inadequate for globally optimising compilers and synthesis tools. We present a path based estimation technique which allows a computation time/quality tradeoff. The results show acceptable computation times while revealing much more potential parallelism than local list schedulin... View full abstract»

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  • Procedure exlining: a transformation for improved system and behavioral synthesis

    Publication Year: 1995, Page(s):84 - 89
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    We present techniques for solving the inverse problem of procedure inlining, namely the problem of replacing sequences of statements with procedure calls. Two techniques are provided, one for finding redundant sequences of statements that can be replaced by calls to one procedure, and another for dividing a large set of statements into several procedures, where each procedure performs a distinct c... View full abstract»

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  • An approach to interface synthesis

    Publication Year: 1995, Page(s):16 - 21
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Presents a novel interface synthesis approach based on a one-sided interface description. Whereas most other approaches consider interface synthesis as optimizing a channel to existing client/server modules, we consider the interface synthesis as part of the client/server module synthesis (which may contain the re-use of existing modules). The interface synthesis approach describes the basic trans... View full abstract»

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  • System level verification of video and image processing specifications

    Publication Year: 1995, Page(s):144 - 149
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    A formal verification method is presented to verify the loop ordering of a high level transformed description against its original specification. The verification is done in an automatic way and its complexity is independent on the sizes of the loops bounds. Any practical structure of loop nests can be handled. The method is especially suited for applications in the area of speech, image and video... View full abstract»

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  • Optimal code generation for embedded memory non-homogeneous register architectures

    Publication Year: 1995, Page(s):36 - 41
    Cited by:  Papers (28)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper examines the problem of code generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1,∞] model. Optimality is guaranteed by sufficient conditions derived from the register transfer ... View full abstract»

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  • Time-constrained code compaction for DSPs

    Publication Year: 1995, Page(s):54 - 59
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    DSP algorithms are, in most cases, subject to hard real-time constraints. In the case of programmable DSPs, meeting those constraints must be ensured by appropriate code generation techniques. For processors offering instruction-level parallelism, the task of code generation includes code compaction. The exact timing behavior of a DSP program is only known after compaction. Therefore, real-time co... View full abstract»

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  • A comprehensive estimation technique for high-level synthesis

    Publication Year: 1995, Page(s):122 - 127
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it accounts for all types of RT level components (FUs, buses, registers), (2) it is highly flexible, allowing the designer to tradeoff one type of resource with another and considers dependencies between these different type... View full abstract»

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  • Array mapping in behavioral synthesis

    Publication Year: 1995, Page(s):90 - 95
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper discusses the mapping of arrays in a behavior to memories in an implementation. We introduce a design representation based on a variety of array grouping techniques and the binding of array groups to memory components with different dimensions, access times, and number of ports. The results of design actions are computed in terms of the number of memory components and the length of sche... View full abstract»

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  • The Chinook hardware/software co-synthesis system

    Publication Year: 1995, Page(s):22 - 27
    Cited by:  Papers (67)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    Designers of embedded systems are facing ever tighter constraints on design time, but computer-aided design tools for embedded systems have not kept pace with these trends. The Chinook co-synthesis system addresses the automation of the most time-consuming and error-prone tasks in embedded controller design, namely the synthesis of interface hardware and software needed to integrate system compone... View full abstract»

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  • Synthesis of system-level communication by an allocation-based approach

    Publication Year: 1995, Page(s):150 - 155
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Communication synthesis aims to transform a system with processes that communicate via high level primitives through channels into interconnected processes that communicate via signals and share communication control. We present a new algorithm that performs binding/allocation of communication units. This algorithm makes use of a cost function to evaluate different allocation alternatives. The pro... View full abstract»

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  • Optimal register assignment to loops for embedded code generation

    Publication Year: 1995, Page(s):42 - 47
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    One of the challenging tasks in code generation for embedded systems is register assignment. When more live variables than registers exist, some variables are necessarily accessed from data memory. Because loops are typically executed many times and are often time-critical, good register assignment in loops is exceedingly important, since accessing data memory can degrade performance. The issue of... View full abstract»

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  • On the use of VHDL-based behavioral synthesis for telecom ASIC design

    Publication Year: 1995, Page(s):96 - 101
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    VHDL-based behavioral synthesis is appearing on the market but it still has to prove that it can have a significant impact. In the past, most applications for behavioral synthesis came from the DSP area and from the academic world. In contrast, this paper describes the results of an investigation and evaluation of several behavioral synthesis tools, carried out on recent designs of Alcatel-Bell, l... View full abstract»

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  • Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model

    Publication Year: 1995, Page(s):156 - 161
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    An approach to system-level modeling and simulation of a class of heterogeneous real-time systems the timing behaviour of which can be modeled by deterministic discrete event systems is described. Examples of systems we consider are self-timed systems, synchronously clocked systems, and mixed asynchronous/synchronous systems. Our model is based on several extensions to the model of timed marked gr... View full abstract»

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