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# IEEE Journal of Solid-State Circuits

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2017, Page(s): C1
| PDF (198 KB)
• ### IEEE JOURNAL OF SOLID-STATE CIRCUITS

Publication Year: 2017, Page(s): C2
| PDF (66 KB)

Publication Year: 2017, Page(s): 1989
| PDF (198 KB)
• ### Frequency Reconfigurable mm-Wave Power Amplifier With Active Impedance Synthesis in an Asymmetrical Non-Isolated Combiner: Analysis and Design

Publication Year: 2017, Page(s):1990 - 2008
| | PDF (7699 KB) | HTML

A frequency reconfigurable millimeter-wave (mm-wave) power amplifier (PA), which can be programmed to operate efficiently for a wide swathe of the spectrum, approaching an universal transmitter, can enable a wide range of novel applications in high-speed communication, sensing, and imaging. Classical techniques to allow large operating range either rely on broadband higher order output combining n... View full abstract»

• ### Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components

Publication Year: 2017, Page(s):2009 - 2025
| | PDF (4291 KB) | HTML

This paper presents a low power and highly linear passive spectrum scanner based on the filtering by aliasing principle. The scanner utilizes a linear periodically time-varying circuit followed by a sampler to achieve sharp apparent filters from a continuous-time input to a discrete-time output. This paper describes the design of the scanner and provides an analysis of the expected and measured pe... View full abstract»

• ### Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects

Publication Year: 2017, Page(s):2026 - 2037
| | PDF (3802 KB) | HTML

This paper presents an energy efficient full-duplex (FD) current-mode transceiver for on-chip global interconnects. As it shares the same signaling port for transmitting and receiving signal, the wire efficiency is increased by $2\times$ compared to unidirectional transceivers. The proposed hybrid transceiver has a direction... View full abstract»

• ### Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems

Publication Year: 2017, Page(s):2038 - 2054
| | PDF (5003 KB) | HTML

An active transmitter (TX) cancellation scheme enabling integration of the antenna interface for frequency division duplex systems is presented. A replica of the TX current is synthesized in shunt with the receiver (RX) by a digital-to-analog converter (DAC). The replica DAC virtually shorts out the TX signal at the RX input while having minimal impact on the TX insertion loss. Propagation of the ... View full abstract»

• ### A 0.038-mm2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop

Publication Year: 2017, Page(s):2055 - 2070
| | PDF (3544 KB) | HTML

An N-path switched-capacitor (SC) gain loop is proposed as an area-efficient surface acoustic wave-less wireless transceiver (TXR) for multiband TDD communications. Unlike the direct-conversion transmitter (TX: baseband (BB) filter $\to$ I/Q modulation $\to$ View full abstract»

• ### On the Design of Wideband Transformer-Based Fourth Order Matching Networks for ${E}$ -Band Receivers in 28-nm CMOS

Publication Year: 2017, Page(s):2071 - 2082
| | PDF (5499 KB) | HTML

This paper discusses the design of on-chip transformer-based fourth order filters, suitable for mm-Wave highly sensitive broadband low-noise amplifiers (LNAs) and receivers (RXs) implemented in deep-scaled CMOS. Second order effects due to layout parasitics are analyzed and new design techniques are introduced to further enhance the gain-bandwidth product of this class of filters. The design and m... View full abstract»

• ### Distributed Injection-Locked Frequency Dividers

Publication Year: 2017, Page(s):2083 - 2093
| | PDF (2875 KB) | HTML

Distributed injection-locked frequency division is introduced as a method to increase the locking range beyond that of conventional injection-locked frequency dividers. It is analytically shown that continuous frequency division can be achieved over a frequency range that spans over multiples of the self-oscillation frequency of the core divider. Design techniques in millimeter-waves are discussed... View full abstract»

• ### A 190-GHz VCO With 20.7% Tuning Range Employing an Active Mode Switching Block in a 130 nm SiGe BiCMOS

Publication Year: 2017, Page(s):2094 - 2104
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A voltage controlled oscillator (VCO) incorporating a system of coupled oscillators with two active mode switching (AMS) blocks is presented. The AMS blocks excite the main VCOs to operate in two distinct frequency bands. An overlap between the two frequency bands has extended the tuning range of the VCO. By turning the AMS blocks off, low-loss and low-capacitance behaviors of these blocks result ... View full abstract»

• ### On-Chip Two-Tone Synthesizer Based on a Mixing-FIR Architecture

Publication Year: 2017, Page(s):2105 - 2116
| | PDF (2846 KB) | HTML

A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-finite impulse response (FIR) architecture is proposed. The proposed robust synthesizer adopts only digital blocks. It implements a two-stage cascade FIR harmonic cancellation technique that generates a single tone quasi-sinusoidal waveform and suppress the odd-order harmonics up to the 21st order. Different... View full abstract»

• ### A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer

Publication Year: 2017, Page(s):2117 - 2127
| | PDF (2858 KB) | HTML

A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the $\Sigma \Delta$ modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily ... View full abstract»

• ### A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs

Publication Year: 2017, Page(s):2128 - 2140
| | PDF (2943 KB) | HTML

A novel phase-noise-filtering technique based on phase-domain averaging is proposed to suppress the large injection spurs and poor high-frequency phase noise of inductor-less injection-locked phase-locked loops (IL-PLLs). Demonstrated using a 1.2-GHz fractional-N IL-PLL based on a capacitive-ring-coupled ring oscillator, wideband spur-and-phase-noise suppression of up to 20 dB is achieved allowing... View full abstract»

• ### A Mostly Digital VCO-Based CT-SDM With Third-Order Noise Shaping

Publication Year: 2017, Page(s):2141 - 2153
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This paper presents the architectural concept and implementation of a mostly digital voltage-controlled oscillator-analog-to-digital converter (VCO-ADC) with third-order quantization noise shaping. The system is based on the combination of a VCO and a digital counter. It is shown how this combination can function as a continuous-time integrator to form a high-order continuous-time sigma–del... View full abstract»

• ### A Fully Passive Compressive Sensing SAR ADC for Low-Power Wireless Sensors

Publication Year: 2017, Page(s):2154 - 2167
| | PDF (4285 KB) | HTML

The compressive sensing (CS) theory states that the sparsity of a signal can be exploited to reduce the analog-to-digital converter (ADC) conversion rate and save power. However, most previous CS frameworks require dedicated analog CS encoders built by power-hungry active amplifiers, which limit the overall power saving. Differently, this paper proposes a fully passive switched-capacitor-based CS ... View full abstract»

• ### A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS

Publication Year: 2017, Page(s):2168 - 2179
| | PDF (3819 KB) | HTML

While high-speed analog-to-digital converter (ADC) front-ends in serial link receivers enable flexible and powerful digital signal processing-based (DSP-based) equalization, the robustness and power consumption of these ADCs can limit overall receiver energy efficiency. This paper presents a 25 GS/s 6b 8-way time-interleaved multi-bit search ADC that employs a soft-decision selection algorithm to ... View full abstract»

• ### A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS

Publication Year: 2017, Page(s):2180 - 2193
| | PDF (4808 KB) | HTML

An all-pass filter architecture that can be generalized to high orders, and can be realized using active circuits is proposed. Using this, a compact true-time-delay element with a widely tunable delay and a large delay-bandwidth product (DBW) is demonstrated. This is useful for beamforming and equalization in the lower GHz range where the use of $LC$ View full abstract»

• ### A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

Publication Year: 2017, Page(s):2194 - 2207
| | PDF (6825 KB) | HTML

Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and wake-up time while maintaining critical local computing states through parallel data movement between volatile FFs and local nonvolatile memory (NVM) devices. However, current nvFFs face challenges in large store energy ( $\text{E}_{\mathrm {S}}$ View full abstract»

• ### A Voltage Multiplier With Adaptive Threshold Voltage Compensation

Publication Year: 2017, Page(s):2208 - 2214
| | PDF (1776 KB) | HTML

A voltage multiplier (VM) with adaptive threshold voltage compensation is presented to enhance the power conversion efficiency (PCE). It is fabricated in a 0.18- $\mu \text{m}$ CMOS process. With the input frequency of 402 MHz and a load resistor of 30 $\text{k}\Omega$ View full abstract»

• ### A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS

Publication Year: 2017, Page(s):2215 - 2220
| | PDF (5516 KB) | HTML

This paper presents a sub-threshold SRAM, which eliminates bitline (BL) leakage-induced read failures. The proposed architecture clamps the current ratio between differential BLs to a fixed value, thus permitting reliable ultra-low-voltage read-out. A de-multiplexed wordline interleaving scheme is presented to compensate for bitcell area overhead. The interleaving technique achieves 9% redu... View full abstract»

• ### Information For Authors

Publication Year: 2017, Page(s): C3
| PDF (56 KB)
• ### Blank page

Publication Year: 2017, Page(s): C4
| PDF (3 KB)

## Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Jan Craninckx
Imec
Kapeldreef 75
B-3001 Leuven, Belgium
jssc.craninckx@gmail.com