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EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference

Date 2-5 Sept. 1996

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  • Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (390 KB)
    Freely Available from IEEE
  • Preliminary analysis cycle for B-method software development

    Publication Year: 1996, Page(s):319 - 325
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The main benefit of using formal specifications early in the software life-cycle is to allow a priori errors detection. More precisely, incompleteness and inconsistency deficiencies can be detected very early and confidence resulting from correctness proofs increases. Thus, formal methods fit into the Verification and Validation activities, relieving but not replacing Software Testing. In the pres... View full abstract»

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  • Software monitoring and debugging using compressed signature sequences

    Publication Year: 1996, Page(s):311 - 318
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    Signature based error detection techniques (e.g. the application of watchdog processors) can be easily extended to support software debugging. The run-time sequence of signatures is stored in an extension of the traditional checker. As the signatures identify the states of the program, a trace of the statements executed by the checked processor is available. The signature buffer can be efficiently... View full abstract»

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  • Communication mechanism independent protocol specification based on CSP: a case study

    Publication Year: 1996, Page(s):303 - 310
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    When specifying and designing computer network protocols, it is convenient to use an abstract synchronous communication mechanism. In practice, however, asynchronous communication mechanisms cannot be avoided. This paper presents a formal approach, based on Hoare's Communicating Sequential Processes (1985) and some other theoretical results on the specification and design of protocols which ensure... View full abstract»

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  • A FPGA based square-root coprocessor

    Publication Year: 1996, Page(s):520 - 525
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    We present an FPGA implementation of a non-restoring integer square-root algorithm, that uses estimates for result-digit selection and radix-2 redundant addition in recurrence. On-the-fly conversion of the result-digit and signed-digit adder/substractor are used to simplify the hardware realization. Modifications of the equations for th optimal use of Xilinx CLBs, and the necessary CLB resources f... View full abstract»

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  • Recovery blocks and algorithm-based fault tolerance

    Publication Year: 1996, Page(s):292 - 299
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Algorithm-based fault-tolerance has been used for a number of years in the field of numerical processing. It has advantages over more `explicit' fault-tolerant methods in that it operates concurrently with the application, thus reducing the time overhead associated with the added redundancy. Recovery blocks and similar fault-tolerant methods are critically dependent on the detection of errors in t... View full abstract»

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  • A prototyping technique with an asynchronous specification language

    Publication Year: 1996, Page(s):151 - 157
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    This paper presents principles of a rapid prototyping technique aimed at software design for embedded distributed systems. It introduces the principles of a local time concept supporting real-time distributed systems specifications: the developed local-time model stems both from counting asynchronous events and from modelling a physical generator of periodic events. The asynchronous specification ... View full abstract»

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  • Design and performance of a main memory hardware data compressor

    Publication Year: 1996, Page(s):423 - 430
    Cited by:  Papers (23)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    In this paper we show that hardware main memory data compression is both feasible and worthwhile. We demonstrate that paging due to insufficient memory resources can reduce system performance several fold, and argue that hardware memory compression can eliminate this paging hence providing a substantial performance improvement. We describe the design and implementation of a novel compression metho... View full abstract»

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  • Causal modeling of a video-on-demand system using predicate/transition net formalism

    Publication Year: 1996, Page(s):625 - 632
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    We give a high-level net model for a specific video on demand system. This system has some very interesting modeling features: FIFO queues, the bunching property, parallel machine scheduling and a complicated resource allocation mechanism. The bunching property is the feasibility of several requests being served together by one resource. The resource allocation mechanism for this video on demand s... View full abstract»

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  • Design of a hybrid digital-analog neural co-processor for signal processing

    Publication Year: 1996, Page(s):513 - 519
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A hybrid architecture for neural coprocessing is presented. A fixed set of analog multipliers and capacitors (analog memory) emulates multilayer perceptrons through digitally-controlled multiplexing. Thus parallelism is partially preserved without direct analog implementation of the whole structure. Details of system VLSI implementation are given, along with simulation results and performance esti... View full abstract»

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  • Transparency in a replicated network file system

    Publication Year: 1996, Page(s):285 - 291
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    File servers acting as centralized data sharing and storage stations are very crucial in modern network environments. Failure and inefficiency of a file server would be unacceptable and thus data replication is necessary to provide fault-tolerant and high-performance services. In this article, we present a replicated network file service that follows the Sun NFS protocol. Replication transparency ... View full abstract»

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  • Functional validation of fault-tolerant asynchronous algorithms

    Publication Year: 1996, Page(s):143 - 150
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    The paper presents an alternative approach to the formal specification and validation of distributed asynchronous algorithms. It begins with a syntactically correct description of the algorithm whose correctness is then to be validated. The validation of the algorithm is based on the process-oriented discrete simulation and permits a partial correctness validation of the algorithm implemented by a... View full abstract»

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  • A multi-agent environment for user interface design

    Publication Year: 1996, Page(s):242 - 247
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    This paper presents a framework for the conceptual and detailed design of user interface. The framework describes an environment that assists people involved in the user interface design task, by helping them to build an interface template. The multidisciplinary nature of the user interface design task has led us to adopt a multi-agent approach in this framework. The environment is thus a multi-ag... View full abstract»

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  • Connection rerouting method for general application to connection-oriented mobile communication networks

    Publication Year: 1996, Page(s):412 - 419
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    Various connection rerouting methods have been proposed for connection-oriented mobile networks. The previous methods, however, are limited to specific topologies or environments. In this paper, we propose a new connection rerouting method based on connection information. In the method when a connection is established between two mobile hosts, the connection information about the connection is pro... View full abstract»

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  • Broadcast with time and causality constraints for multimedia applications

    Publication Year: 1996, Page(s):617 - 624
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    Δ-causal ordering is a communication abstraction designed for distributed applications whose messages (i) have to be delivered according to causal ordering and (ii) have a limited lifetime after which their data can no longer be used by the application. Example of such applications are: multimedia real-time collaborative applications and groupware real-time applications. For such application... View full abstract»

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  • Architecture and implementation for scalable transfer of live videos in multimedia applications

    Publication Year: 1996, Page(s):572 - 579
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    Todays networks are characterized by heterogeneous environments. Various transmission techniques coexist and offer different bandwidths at different costs. Because of videoconferences and similar applications becoming more and more important this paper presents the architecture of the video communication system “XNetvideo” which is scalable in terms of SNR (signal to noise ratio)-scali... View full abstract»

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  • Real-time scheduling co-processor in hardware for single and multiprocessor systems

    Publication Year: 1996, Page(s):509 - 512
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Multiprocessor real-time systems are difficult to design to achieve predictable time behaviour. Our approach to simplification of the design and timing analysis is to use a scheduling coprocessor. We present the real-time services provided by the coprocessor as well as its implementation and timing. The scheduling coprocessor is a specially designed digital chip and is called the Real-Time Unit (R... View full abstract»

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  • Retiming for circuits with enable registers

    Publication Year: 1996, Page(s):275 - 280
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    This paper presents a new method for improving the timing behaviour of digital circuits, which contain enable-registers and, e.g., come from the high level synthesis. Known techniques optimize all long combinational paths assuming only one clock cycle between registers. But enable-registers cause also paths having more time than one clock cycle. The consideration of this paths leads to a larger op... View full abstract»

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  • Performance analysis of packet switching interconnection networks with finite buffers

    Publication Year: 1996, Page(s):390 - 396
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    In this paper, a mathematical method for analysis of synchronous packet-switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed mathematical method is general in that it analyzed interconnection networks under uniform and nonuniform traffic with blocking. The existing methods for analysis of buffered interconnection networks ... View full abstract»

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  • A macro expansion approach to embedded processor code generation

    Publication Year: 1996, Page(s):136 - 142
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    This paper describes an experimental prototype of a code generation tool for embedded special-purpose processors. The tool is a retargetable assembly-code-level macro expander capable of program flow analysis. The main advantage of the tool is its strong support for macro hierarchy: hierarchical macro libraries make the code (produced either by the compiler writer or by the assembly language progr... View full abstract»

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  • Reachability and timing analysis in data flow networks: a case study

    Publication Year: 1996, Page(s):193 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    The need of efficient implementation, safety and performance requires early validation in the design of computer control systems. The detailed timing and reachability analysis in the development process is particularly important if we design equipments or algorithms of high performance and availability. In this paper we present a case study related to the early validation of control systems modele... View full abstract»

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  • A general framework for positioning, evaluating and selecting the new generation of development tools

    Publication Year: 1996, Page(s):233 - 240
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    This paper focuses on the evaluation and positioning of a new generation of development tools containing subtools (browsers, debuggers, GUI-builders, …) and programming languages that are designed to work together and have a common graphical user interface and are therefore called environments. Several trends in IT have led to a pluriform range of development tools that can be classified in... View full abstract»

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  • Towards extremely fast context switching in a block-multithreaded processor

    Publication Year: 1996, Page(s):592 - 599
    Cited by:  Papers (2)  |  Patents (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    Multithreaded processors use a fast context switch to bridge latencies caused by memory accesses or by synchronization operations. In the block-multithreaded processor-called Rhamma-load/store, synchronization and execution operations of different threads of control are executed simultaneously by appropriate functional units. A fast context switch is performed, whenever a functional unit comes acr... View full abstract»

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  • Performance comparison of experimented switching architectures for ATM

    Publication Year: 1996, Page(s):405 - 411
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    This article surveys some interconnection networks, especially rings, utilized in broadband switching and compares their transfer delay performance. Special attention is paid to a ring, named Frame Synchronized Ring (FSR), which is developed for high speed switching and experimented as an ATM-switch. The study concentrates on analysing the transfer delay performance of the switching architectures ... View full abstract»

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  • A fast capability extension to a RISC architecture

    Publication Year: 1996, Page(s):606 - 613
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    The concept of capability-based addressing originated in the 60's a means of promoting security and information sharing in computer systems; however, poor performance of early capability-based machines prevented it from becoming widespread. We describe a capability-based architecture implemented as a fairly straightforward extension of a conventional RISC architecture. Without compromising the sec... View full abstract»

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