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EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference

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EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference

Date 2-5 Sept. 1996

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Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies

Performance assessment of contents management in multilevel on-chip caches

A system for heuristic modifications on PLA-specifications

Using method lookup caches and register windowing to speed up dynamically-bound object-oriented applications

Load balancing in superscalar architectures

Increasing the effective memory bandwidth in multivector processors

Separating application functionality from the user interface in a distributed environment

DELFIM: error detection by thin memory protection

Comparing performances and quality of service of group communication protocols

Preliminary analysis cycle for B-method software development

Efficient simulation of multiprocessors through finite state machines

Recovery blocks and algorithm-based fault tolerance

Broadcast with time and causality constraints for multimedia applications

Low-power embedded microprocessor design

Experience of adaptive replication in distributed file systems

A semantic model of VHDL for validating rewriting algebras

Design and performance of a main memory hardware data compressor

Results given by a new evaluation system for placement and routing heuristics

Statistical admission control in video servers with variable bit rate streams and constant time length retrieval

Automating system-level design: from specification to architecture

Application of the V-Ray technology for optimization of the TRFD and FL052 Perfect Club Benchmarks to CRAY Y-MP and CRAY T3D supercomputers

Functional validation of fault-tolerant asynchronous algorithms

N-version programming: a unified modeling approach

A new control service model based on CORBA for distributed multimedia objects

A hybrid approach to trace generation for performance evaluation of shared-bus multiprocessors

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