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Low Power Electronics and Design, 1996., International Symposium on

Date 12-14 Aug. 1996

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  • Proceedings of 1996 International Symposium on Low Power Electronics and Design

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    Freely Available from IEEE
  • Energy recovery for the design of high-speed, low-power static RAMs

    Page(s): 55 - 60
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    We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-recovery SRAM was evaluated through SPICE simulations and compared with a standard design. Simulation results of a 256 × 256 memory configuration indicate that, for successive write operations, energy saving for the different SRAM functions vary from 59% to 76% at 200 MHz operating frequency compared to the conventional design. View full abstract»

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  • Author index

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    Freely Available from IEEE
  • How to design low-power digital cellular phones

    Page(s): 177 - 180
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    Over the last decade, analog cellular phones have been continuously reducing their size and weight, extending the battery life, and increasing the sales. The advent of digital cellular phones is expected to further accelerate this trend. This paper will review the semiconductor technologies to reduce power consumption in existing digital cellular phones and discuss the possibility of further improvement View full abstract»

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  • Concurrency-oriented optimization for low-power asynchronous systems

    Page(s): 151 - 156
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    We introduce new architectural optimizations for low-power asynchronous systems, such as Tangram-based systems of van Berkel et al. (1994). Our goal is to reduce power consumption by improving system concurrency. We introduce two new sequencer designs, with greater concurrency than existing ones, that provide the opportunity for substantial power savings through voltage scaling. To safely accommodate this added concurrency, new latch designs are presented, for both dual-rail and single-rail implementations View full abstract»

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  • A 0.5 V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

    Page(s): 49 - 54
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    This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses an over-VCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimize the charge amount supplied from the embedded charge pump circuits, which are required to boost the effective gate to source voltage (V0=V GS-VT) up to 0.8 V necessary to achieve 100 MHz-operation even at 0.5 V single power-supply. Thus, the key low-power strategy of OVGS is “putting the right (higher efficiency) boosted power-supply from the charge pump circuit into the right position in the SRAM cell”. This paper focuses on why OVGS can realize a greater saving of the charge amount supplied from the boosted power-line and can reduce the power dissipation to ⩽1/30.4 and ⩽1/3.9 compared to the previously reported negative source drive (NSD) scheme (Mizuno et al., 1995) and negative word-line drive (NWD) scheme (Itoh et al., 1996), respectively, while achieving a 0.5 V/100 MHz-operation View full abstract»

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  • Clock-skew optimization for peak current reduction

    Page(s): 265 - 270
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    The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced by more than a factor of two without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern View full abstract»

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  • Micro power “relative precision” 13 bits cyclic RSD A/D converter

    Page(s): 253 - 257
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    “Relative precision” A/D and D/A converters are presented. They feature a limited signal-to-noise ratio but have a dynamic range of 13 to 14 bits. These characteristics are achieved by using a so called RSD (Redundant Signed Digit) algorithm conducting to a minimal implementation complexity. The elements of the analog parr of the A/D converter and its digital control consumes less than 50 μW at 2.4 V power supply voltage, whereas the D/A converter with its track and hold circuit consumes 75 μW at the same supply voltage View full abstract»

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  • Fixed-phase retiming for low power design

    Page(s): 259 - 264
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    In this paper we introduce fixed-phase retiming, an optimization technique for reducing the power dissipation of digital circuits without sacrificing their performance. In fixed-phase retiming, we first transform any given edge-triggered circuit into a two-phase level-clocked circuit by replacing each flip-flop by two level-sensitive latches. Subsequently, while keeping the latches clocked on one of the phases fixed, we relocate the remaining latches onto interconnections with high glitching activity and capacitive load. We formulate fixed-phase retiming as a Boolean monotonic linear program and give an O(V6 log V)-time algorithm for solving it, where V is the number of combinational blocks in the circuit View full abstract»

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  • Floating body effects in partially-depleted SOI CMOS circuits

    Page(s): 139 - 144
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    This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for View full abstract»

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  • Effects of correlations on accuracy of power analysis-an experimental study

    Page(s): 113 - 116
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    In this paper, we describe the correlation assumptions made by different power analysis methods and evaluate the impact on the accuracy of total power dissipation calculation as well as of the power dissipated by individual signals. Industrial circuits and applications are used. The results show that some assumptions cause inaccuracies of more than 100% for certain circuit types View full abstract»

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  • A 1-V 1-Mb SRAM for portable equipment

    Page(s): 61 - 66
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    Low-power and high-speed circuit techniques are described for 1-V battery operated SRAMs. A design concept is shown that uses two kinds of MOSFETs different in threshold voltages to reduce power dissipation due to the subthreshold leakage current in both standby and active modes. We propose a step-down boosted word-line scheme to reduce power dissipation in the memory array to 57% while accelerating the sensing speed. A novel bidirectional differential internal-bus architecture provides data transmission that is 45% faster than in the conventional architecture, yet without area or power penalty. A charge-recycling I/O buffer incorporating a data transition detector reduces the power dissipation of the I/O buffer by 30%. A 1-Mb SRAM designed using these techniques and 0.5-μm CMOS technology demonstrated 4.8-mW power dissipation and a 75-ns address access time with standby power of 1.2-μW at a 1-V power supply View full abstract»

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  • Circuit techniques for low power CMOS GSI

    Page(s): 193 - 196
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    For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60°K above room temperature View full abstract»

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  • Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models

    Page(s): 197 - 200
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    Accurate MOSFET Idsat model including LDD parasitic resistance and channel subthreshold leakage models current MOSFET operation regions, particularly moderate inversion and subthreshold regions that are important for low power electronics, have been presented with measurement data. Based on these accurate models, CMOS gate performance and power consumption optimization guidelines have been discussed in terms of device Tox, Vdd and Vt . It predicts that there exists certain Tox value that can minimize the gate delay. Device designs for low power electronics considering trade-offs by varying Vdd, Tox and V t are highlighted View full abstract»

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  • Lower bounds on power-dissipation for DSP algorithms

    Page(s): 43 - 48
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    The author presents a fundamental mathematical basis for determining the lower bounds on power dissipation in digital signal processing (DSP) algorithms. This basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Different architectures implementing a given algorithm are equivalent to different communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. The proposed framework is employed to determine the lower bounds for simple digital filters. Furthermore, lower bounds on the power dissipation achievable via adiabatic logic are also presented, thus demonstrating the versatility of the proposed approach View full abstract»

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  • Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

    Page(s): 353 - 358
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    This paper presents a new pipeline structure that dramatically reduces the power consumption of multimedia processors by using the commonly observed characteristic that most of the execution cycles of signal processing programs are used for loop executions. In our pipeline, the signals obtained by decoding the instructions included in a loop are temporarily stored in a small-capacity RAM that we call decoded instruction buffer (DIB), and are reused at every cycle of the loop iterations. The power saving is achieved by stopping the instruction fetch and decode stages of the processor during the loop execution except its first iteration. The result of our power analysis shows that about 40% power saving can be achieved when our pipeline structure is incorporated into a digital signal processor or RISC processor. The area of the DIB is estimated to be about 0.7 mm2 assuming triple-metal 0.5 μm CMOS technology View full abstract»

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  • A 200 μA, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm

    Page(s): 305 - 308
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    A 78 MHz crystal oscillator consuming 200 μA at 1.7 V supply is described. The oscillator is part of a regulated system in a wireless device where the oscillation frequency is controlled digitally. This digital trimming of oscillation frequency is realized by binary capacitor banks of 10-bit resolution. The oscillator can be pulled from ±35 ppm to the required frequency with 0.3 ppm accuracy. The circuit has been fabricated in a 1 μm CMOS technology. The measured phase noise is -100 dBc at 100 Hz offset View full abstract»

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  • An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits

    Page(s): 145 - 150
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    In this paper the effects of technology scaling on the fraction of active power Pa wasted as short-circuit power Ps are studied through SPICE simulations. The accuracy of SPICE is verified against experimental data. SPICE simulations show that lowering VT below 0.1 V can increase Ps/Pa significantly beyond what is expected from increased subthreshold leakage. Ps/Pa is typically higher at higher Vcc but to first order Ps/Pa is determined by signal slew rates and VT. It is shown that the input slew rate is constrained by Ps/Pa at low V T and by performance at higher VT. We show that P s increases with increasing gate sheet resistance. A simple analytical model for this effect is verified against the experimental data and used to determine the gate sheet requirements to maintain Ps/Pa<10% for sub-0.25 μm technologies View full abstract»

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  • Power comparisons for barrel shifters

    Page(s): 209 - 212
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    Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of mobile computing, power has become as important as speed for circuit designs. In this paper we present a power-delay analysis for a range of 32-bit barrel shifters that vary at the gate, architecture, and environment levels View full abstract»

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  • Integrated resynthesis for low power

    Page(s): 169 - 174
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    Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the power of a mapped circuit under the given delay constraints. It produces 24% savings in power View full abstract»

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  • Substrate noise influence on circuit performance in variable threshold-voltage scheme

    Page(s): 309 - 312
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    This paper investigates substrate noise influence on circuit performance in a variable threshold-voltage scheme (VT scheme) where threshold voltage is dynamically varied by substrate-bias control to reduce active power dissipation. It is experimentally examined that substrate-bias can be controlled stably with very few substrate-contacts. Measured tracking jitter of a delay-locked loop implemented by interconnections in an 8 mm-square gate array does not degrade even when substrate-contacts are removed except for one at every strip of p-sub and n-well: A 2 mm-square discrete cosine transform core processor with no substrate-contact except in its periphery operates at supply voltages from 1.3 V to above 3 V even though it employs small-swing differential dynamic pass-transistor logic. No performance degradation nor latchup is observed in these chips even when 100 kΩ resistance is added to the substrate. These experimental results demonstrate noise immunity of the VT scheme, and indicate the possibility that the VT scheme can be applied to existing macro design easily View full abstract»

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  • Design techniques for high-performance, energy-efficient control logic

    Page(s): 97 - 100
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    This paper investigates delay, power and area of critical components in designing energy-efficient control logic. To improve performance and energy efficiency, a split-slave dual-path (SSDP) register is proposed which improves the energy efficiency of the prior art by 30%. For multiplexers (MUX) three MUXes are proposed and compared to existing solutions. The proposed MUXes improve performance by 50% or power by 22%. The impact of scaling supply voltage alone and scaling threshold voltage with supply voltage on delay and power is also examined View full abstract»

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  • Leap frog multiplier

    Page(s): 221 - 223
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    Array multipliers are popular due to their regular compact structure. Timing analysis of a full adder has resulted in a different array connection pattern that provides improved throughput for the multiplier while reducing its power dissipation from spurious transitions. The paper details the new array design and some results obtained View full abstract»

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  • Symbolic computation of logic implications for technology-dependent low-power synthesis

    Page(s): 163 - 168
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    This paper presents a novel technique for re-synthesizing circuits for low-power dissipation. Power consumption is reduced through redundancy addition and removal by using learning to identify indirect logic implications within a circuit. Such implications are exploited by adding gates and connections to the circuit without altering its overall behavior and thereby enabling us to eliminate other, high power dissipating, nodes. We propose a new BDD-based method for computing indirect implications in a logic network; furthermore, we present heuristic techniques to perform redundancy addition and removal without destroying the topology of the mapped circuit. Experimental results show the effectiveness of the proposed technique in reducing power while keeping within delay and area constraints View full abstract»

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  • Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

    Page(s): 117 - 120
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    In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with that of actual VLSI chip. To evaluate the accuracy of several kind of power dissipation model such as chip-level, block-level and gate-level etc., we examined as follows: (i) Measuring power consumption of actual micro-processors. (ii) Estimating power consumption with several kinds of power dissipation model. (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate View full abstract»

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