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Proceedings of 1996 International Symposium on Low Power Electronics and Design

12-14 Aug. 1996

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  • Proceedings of 1996 International Symposium on Low Power Electronics and Design

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (480 KB)
    Freely Available from IEEE
  • The design of a high performance low power microprocessor

    Publication Year: 1996, Page(s):11 - 16
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    The StrongARM 11O/sup TM/ is the first example of a new generation of very high performance embedded processors. Developed by UK-based ARM Ltd. approximately ten years ago, the ARM microprocessor architecture is exclusively focused on low-cost and low-power applications. It is used extensively in consumer-oriented applications such as mobile phones, PDAs, organizers, and video games. View full abstract»

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  • Energy recovery for the design of high-speed, low-power static RAMs

    Publication Year: 1996, Page(s):55 - 60
    Cited by:  Papers (12)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (599 KB)

    We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-recovery SRAM was evaluated through SPICE simulations and compared with a standard design. Simulation results of a 256 × 256 memory configuration indicate that, for successive write operations, energy saving for th... View full abstract»

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  • Author index

    Publication Year: 1996
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    Freely Available from IEEE
  • Floating body effects in partially-depleted SOI CMOS circuits

    Publication Year: 1996, Page(s):139 - 144
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state erro... View full abstract»

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  • Fabrication and performance of mesa interconnect

    Publication Year: 1996, Page(s):133 - 137
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    This paper explores the decrease in interconnect capacitance that can be achieved by the use of mesa-shaped wires. A methodology for creating mesa interconnect is described that uses simple postprocessing steps following standard CMOS IC foundry processes. By removing the oxide between metal lines and replacing it with air, the fringing capacitance between metal lines and the substrate is reduced ... View full abstract»

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  • A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications

    Publication Year: 1996, Page(s):129 - 132
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    Graded-Channel MOS (GCMOS) VLSI technology has been developed to meet the growing demand for low power and high performance applications. In this paper, it will be shown that, compared with conventional CMOS, the GCMOS device offers the advantage of significantly higher drive current, capable of lower threshold voltage with improved punchthrough resistance, lower body effect and lower series resis... View full abstract»

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  • Low power mapping of behavioral arrays to multiple memories

    Publication Year: 1996, Page(s):289 - 292
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Large data arrays in behavioral specifications are usually mapped to off-chip memories during system synthesis. We address the problem of system power reduction through transition count minimization on the address bus during memory accesses, when mapping behavioral arrays to multiple memory modules drawn from a library. We formulate the problem as three logical-to-physical memory mapping subtask, ... View full abstract»

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  • Short circuit power consumption of glitches

    Publication Year: 1996, Page(s):125 - 128
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    Short circuit currents are analyzed for glitch and glitch-free cases within this paper. Within the glitch power-formulas introduced in literature short circuit power consumption is neglected. We examined that short-circuit power consumption contributes more significantly to a gate-transition's total power consumption for glitches than for common complete transitions. Simulation results are present... View full abstract»

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  • A 1.5 V class AB output buffer

    Publication Year: 1996, Page(s):285 - 288
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Most class AB push-pull output buffers have been developed for supply voltages ⩾3.0 V. Recently developed class AB buffers, which operate at a voltage supply lower than 3.0 V, use sophisticated feedback circuits to control the quiescent current. In this paper, a simple class AB buffer is proposed. It can be used at 1.5 V power supply and has the capability to drive small resistive loads (<1... View full abstract»

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  • Simulation based architectural power estimation for PLA-based controllers

    Publication Year: 1996, Page(s):121 - 124
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    We present an architectural power simulation technique for PLA-based controllers. The contributions of this work are (1) a simple but efficient power characterization of PLAs; and (2) a strategy for developing a simulatable power model from the input description. Node Switching Capacitance (NSC) of a sub-component (such as AND plane) in a PLA is the average capacitance switched by a node in the su... View full abstract»

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  • How to design low-power digital cellular phones

    Publication Year: 1996, Page(s):177 - 180
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Over the last decade, analog cellular phones have been continuously reducing their size and weight, extending the battery life, and increasing the sales. The advent of digital cellular phones is expected to further accelerate this trend. This paper will review the semiconductor technologies to reduce power consumption in existing digital cellular phones and discuss the possibility of further impro... View full abstract»

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  • Low-power frequency multiplier with one cycle lock-in time and 100 ppm frequency resolution, for system power-management

    Publication Year: 1996, Page(s):281 - 284
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    A low-power Frequency Multiplier (FMUL) with 100 ppm frequency resolution, +/-100 ps jitter, and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a reference frequency of 32,768 Hz, for advanced power management both at a device level and at a system level. The FMUL is implemented in a standard digital CMOS process and its area is 0.5 mm View full abstract»

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  • A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)

    Publication Year: 1996, Page(s):371 - 375
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    A novel quasi-adiabatic, precharge-evaluate logic family, Dynamic Adiabatic MOS (DAMOS), is proposed. Wave-pipelined DAMOS inverter chain datapaths in a 0.25 μm, 2.5 V CMOS device technology are shown to successfully recycle 73% and 89% of the energy available from the power-clock in high-performance (200 MHz) and fixed-throughput (10 MHz) applications, respectively. DAMOS offers significantly ... View full abstract»

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  • Concurrency-oriented optimization for low-power asynchronous systems

    Publication Year: 1996, Page(s):151 - 156
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    We introduce new architectural optimizations for low-power asynchronous systems, such as Tangram-based systems of van Berkel et al. (1994). Our goal is to reduce power consumption by improving system concurrency. We introduce two new sequencer designs, with greater concurrency than existing ones, that provide the opportunity for substantial power savings through voltage scaling. To safely accommod... View full abstract»

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  • Gate-level synthesis for low-power using new transformations

    Publication Year: 1996, Page(s):297 - 300
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A new logic optimization method of multi-level combinational CMOS circuits is presented, which minimizes both power as well as power dissipation per unit area. The method described here uses Boolean transformations which exploit implications at the gate-level, based on both controllability and observability relationships. New transformations which form the basis of our synthesis method are present... View full abstract»

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  • Static power driven voltage scaling and delay driven buffer sizing in Mixed Swing QuadRail for sub-1 V I/O swings

    Publication Year: 1996, Page(s):381 - 386
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    This paper describes and explores the design space of a four power-supply rail methodology (called Mixed Swing QuadRail) for performing low voltage logic in a high threshold voltage CMOS fabrication process. Power and delay trade-offs are studied to suggest approaches for efficient selection of voltage levels and buffer transistor sizes. Polynomial models for QuadRail power and delay are derived t... View full abstract»

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  • A 200 μA, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm

    Publication Year: 1996, Page(s):305 - 308
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A 78 MHz crystal oscillator consuming 200 μA at 1.7 V supply is described. The oscillator is part of a regulated system in a wireless device where the oscillation frequency is controlled digitally. This digital trimming of oscillation frequency is realized by binary capacitor banks of 10-bit resolution. The oscillator can be pulled from ±35 ppm to the required frequency with 0.3 ppm accu... View full abstract»

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  • A low power switching power supply for self-clocked systems

    Publication Year: 1996, Page(s):313 - 317
    Cited by:  Papers (48)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    This paper presents a digital power supply controller for variable frequency and voltage circuits. By using a ring oscillator as a method of predicting circuit performance, the regulated voltage is set to the minimum required to operate at a reference frequency which maximizes energy efficiency. Our initial test silicon, implemented with a fixed frequency controller is analyzed and reveals that th... View full abstract»

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  • Entropic bounds on FSM switching

    Publication Year: 1996, Page(s):323 - 328
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Several state assignment algorithms have attempted to minimize the average Hamming distance per transition in the hopes of generating low power assignments. There has not been a reasonable theoretical lower bound on the average Hamming distance per transition that is applicable to every state assignment for a given FSM. Such a lower bound serves many roles-a target for algorithm designers, provide... View full abstract»

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  • Two-dimensional codes for low power

    Publication Year: 1996, Page(s):335 - 340
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    Coding was previously proposed for reducing power consumption in CMOS. The original formulations use extra redundancy in space (number of bus lines) for reducing the bus transition activity (and consequently the dynamic power and simultaneous switching noise). This paper proposes several new coding techniques for low power. First it looks at codes in which redundancy in time is used for reduced bu... View full abstract»

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  • Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

    Publication Year: 1996, Page(s):117 - 120
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with that of actual VLSI chip. To evaluate the accuracy of s... View full abstract»

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  • Energy delay analysis of partial product reduction methods for parallel multiplier implementation

    Publication Year: 1996, Page(s):201 - 204
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is currently the most popular choice for partial product reduction in parallel multipliers although 4:2 compressors can also produce equivalent results. Our energy delay analysis of these two schemes taking into account the a... View full abstract»

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  • Switching activity analysis for sequential circuits using Boolean approximation method

    Publication Year: 1996, Page(s):79 - 84
    Cited by:  Papers (4)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    We propose an incremental probabilistic approach to calculate the signal probabilities and switching activities of the internal nodes of sequential logic circuits. Spatio-temporal correlations are fully considered by using Multi-Terminal Binary Decision Diagrams (MTBDD) with real number valued terminals. The running time of our approach is short because the depth of the MTBDD does not depend on ci... View full abstract»

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  • Fixed-phase retiming for low power design

    Publication Year: 1996, Page(s):259 - 264
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    In this paper we introduce fixed-phase retiming, an optimization technique for reducing the power dissipation of digital circuits without sacrificing their performance. In fixed-phase retiming, we first transform any given edge-triggered circuit into a two-phase level-clocked circuit by replacing each flip-flop by two level-sensitive latches. Subsequently, while keeping the latches clocked on one ... View full abstract»

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