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Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on

Date 19-21 Aug. 1996

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  • Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (197 KB)
    Freely Available from IEEE
  • Index of authors

    Publication Year: 1996
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    Freely Available from IEEE
  • Microphone array for hearing aid and speech enhancement applications

    Publication Year: 1996, Page(s):231 - 239
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Microphone array technology has been proposed for various audio, teleconference, hearing aid and voice recognition applications. By forming a focused beam toward the desired speech source, attenuating background noises and rejecting discrete spatial interferers, a microphone array can enhance the signal-to-noise-ratio (SNR) in a noisy environment with notable improvement in speech intelligibility.... View full abstract»

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  • A VLSI system architecture for real-time intelligent decision making

    Publication Year: 1996, Page(s):221 - 230
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    In this paper, we describe a VLSI system architecture for real-time intelligent decision making. The architecture integrates the adaptability of a backpropagation based neural network and the decision making ability of a rule based fuzzy expert system on a chip. The intelligent decision making system consists of a back-propagation based neural network for adaptive learning and a rule-based fuzzy e... View full abstract»

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  • Diagnosis algorithm for mobility-oriented system

    Publication Year: 1996, Page(s):209 - 220
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    Mobile communication imposes a number of restrictions in terms of resources, memory, capacity, ... . So as to limit the use of the wireless link between the mobile device and the base station, a representation of the user on the wired network will be used; namely the representation agent. It can be viewed as a useful user's delegate caring of important regarding problems such as task delegation, c... View full abstract»

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  • An abstract model for a low cost SIMD architecture

    Publication Year: 1996, Page(s):145 - 154
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    In this paper we present the abstract model of the Rapid-2 SIMD architecture. Rapid-2 is a low cost additional board for PCs. The abstract model is the basis for the design of a high level language, which is an extension of C. It includes new data types, with appropriate semantics. The L1 language enables co-specification of the board driver code and of Rapid-2 microcode. The L1 compiler was imple... View full abstract»

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  • Kestrel: a programmable array for sequence analysis

    Publication Year: 1996, Page(s):25 - 34
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Kestrel is a programmable linear systolic array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, and efficient communication using systolic shared registers. This paper describes Kestrel's functional units in detail, and examines each of their effects on system performance. With prototypes currently in prog... View full abstract»

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  • A flexible motion estimation chip for variable size block matching

    Publication Year: 1996, Page(s):112 - 121
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    A flexible block matching motion estimation architecture is described. The block size can be adaptively refined with blocks of 8×8, 16×16 and 32×32 pixels or can be set to one of these sizes without significant loss in efficiency in comparison with standard block matching. The chip performs block matching on a search area of ±15 vertically and horizontally for a block size... View full abstract»

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  • Overcoming chip-to-chip delays and clock skews

    Publication Year: 1996, Page(s):199 - 208
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    In general, mapping a circuit onto several chips incurs a physical setting which differs from those within a chip. Specifically, the delay of chip-to-chip interconnections is much longer than on-chip delays of wires and gates. This delay effects the bandwidth as well. In addition, the clock skew between chips is larger than the clock skew within a chip. One may mistakenly conclude that the feasibl... View full abstract»

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  • A coalescing-partitioning algorithm for optimizing processor specification and task allocation

    Publication Year: 1996, Page(s):342 - 352
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    This paper considers the design problems of processor specification and task allocation for embedded computer systems. A graph partitioning-based representation is proposed that allows these problems to be solved concurrently. A custom design automation algorithm bared on this representation is then presented. This algorithm, named CP*-2, was benchmarked against two baseline algorithms on a combin... View full abstract»

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  • A synthesis system for bus-based wavefront array architectures

    Publication Year: 1996, Page(s):274 - 283
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the array simplifies the access of the processing elements for data manipulations. The DPSS allows automatic mapping of high level datapath structures onto the rDPA without manual interaction. Optimization techniques are sketched... View full abstract»

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  • Scheduling of partitioned regular algorithms on processor arrays with constrained resources

    Publication Year: 1996, Page(s):131 - 144
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: (1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also processor caches and constraints on the size of available memories ... View full abstract»

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  • A decomposition method for efficient use of distributed supercomputers for finite element applications

    Publication Year: 1996, Page(s):12 - 24
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    The interconnection of geographically distributed supercomputers via highspeed networks makes available the needed compute power for large-scale scientific applications, such as finite element applications. In this paper we propose a two-level data decomposition method for efficient execution of finite element applications on a network of supercomputers. Our method exploits the following features ... View full abstract»

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  • Area-efficient parallel FIR digital filter implementations

    Publication Year: 1996, Page(s):93 - 111
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    This paper presents a novel approach for implementing area-efficient parallel (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. However, a traditional block filter imp... View full abstract»

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  • On supernode transformation with minimized total running time

    Publication Year: 1996, Page(s):402 - 414
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Supernode transformation has been proposed to reduce the communication startup cost by grouping a number of iterations in a loop as a supernode which is assigned to a processor as a single unit. A supernode transformation is specified by n families of hyperplanes which slice the iteration space into parallelepiped supernodes, the grain size of a supernode, and the relative side lengths of the para... View full abstract»

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  • A common architecture for the DWT and IDWT

    Publication Year: 1996, Page(s):193 - 198
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    This paper presents an architecture which is equally efficient at computing both the discrete wavelet transform (the DWT) and the inverse discrete wavelet transform (the IDWT). Given the seemingly fundamental difference between the structure of a DWT filter bank and the structure of an IDWT filter bank, it is somewhat surprising that such an architecture can be derived. Our architecture allows the... View full abstract»

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  • Efficient finite field serial/parallel multiplication

    Publication Year: 1996, Page(s):72 - 82
    Cited by:  Papers (28)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    Finite field has received a lot of attention due to its widespread applications in cryptography, coding theory, etc. Design of efficient finite field arithmetic architectures is very important and of great practical concern. In this paper, a new bit-serial/parallel finite field multiplier is presented with standard basis representation. This design is regular and well suited for VLSI implementatio... View full abstract»

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  • Jacobi-specific processor arrays

    Publication Year: 1996, Page(s):323 - 341
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    We present a processor and a compiler for prototyping array implementations of algorithms from the class of Jacobi algorithms. We use adaptive matrix QR decomposition as an illustrative example View full abstract»

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  • Hierarchical static analysis of structured systems of affine recurrence equations

    Publication Year: 1996, Page(s):381 - 390
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    The ALPHA language, based on systems of affine recurrence equations over polyhedral domains, allows the expression of complex algorithms as hierarchical, parameterized structures of such systems. This paper discusses the static analysis of ALPHA programs, an extended type-checking process based on the single assignment rule. We present techniques ensuring, on one hand, that a system is valid (with... View full abstract»

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  • NULL Convention LogicTM: a complete and consistent logic for asynchronous digital circuit synthesis

    Publication Year: 1996, Page(s):261 - 273
    Cited by:  Papers (123)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    NULL Convention Logic (NCL) is a symbolically complete logic which expresses process completely in terms of the logic itself and inherently and conveniently expresses asynchronous digital circuits. The traditional form of Boolean logic is not symbolically complete in the sense that it requires the participation of a fundamentally different form of expression, time in the form of the clock, which h... View full abstract»

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  • Monitoring and debugging a hard real-time distributed computer for aircraft industry

    Publication Year: 1996, Page(s):175 - 182
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Distributed systems offer efficient solutions to answer the requirements of embedded computers for aircraft industry. Indeed, performances and reliability can be considerably increased compared with existing computers. Today, such computers often rely on massively redundant architectures, but distributed architectures seem to be a great challenge for the aeronautic community. In this paper, we sho... View full abstract»

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  • Radix-4 vectoring CORDIC algorithm and architectures

    Publication Year: 1996, Page(s):55 - 64
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    In this paper we present a new CORDIC algorithm for the vectoring mode, based on the use of radix-4 preserving a complexity in the microrotations that is similar to that of the conventional radix-2 CORDIC. The use of this radix, together with the inclusion in the CORDIC algorithm of the zero skipping technique, reduces by more than half the number of iterations with respect to the conventional rad... View full abstract»

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  • Rapid prototyping of reconfigurable coprocessors

    Publication Year: 1996, Page(s):303 - 312
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    We describe the process of hardware-software codesign of a JPEG-like still image compression system. The hardware components are targeted to execute on a reconfigurable hardware coprocessor which communicates with a host computer that executes all the software tasks. Central to our codesign methodology is the usage of software profiling, high-level estimation and synthesis tools. We describe the p... View full abstract»

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  • Static communication scheduling for minimizing collisions in application specific parallel systems

    Publication Year: 1996, Page(s):240 - 249
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    In applications requiring very high throughput or which have real-time deadlines, the use of parallel processing techniques has become widespread. Although there exists potential for vast performance gains, the communication overhead inherent in such systems can significantly lessen these gains. In this paper, with tightly-coupled architectures as the platform, the static communication scheduling ... View full abstract»

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  • Automatic generation of modular mappings

    Publication Year: 1996, Page(s):155 - 164
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Modular mappings have been recently proposed for optimization of algorithms that cannot be efficiently mapped by affine mappings. This paper addresses the problem of generating modular mappings that satisfy conditions for validity and optimality. In general, this is a difficult problem due to the presence of non-linear constraints. Hence, a method of O(n2) complexity is provided to assi... View full abstract»

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