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Application Specific Array Processors, 1995. Proceedings. International Conference on

Date 24-26 July 1995

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  • Proceedings The International Conference on Application Specific Array Processors

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (154 KB)
    Freely Available from IEEE
  • Index of Authors

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB)

    Presents an index of the authors whose papers are published in the conference. View full abstract»

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  • A scalable halftoning coprocessor architecture

    Publication Year: 1995, Page(s):76 - 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Exact-angle superscreen dithering requires large dither tiles. Since storing precomputed screen elements for each intensity level would require too much memory, dithering must be executed on the fly at halftoning time. For this purpose a dithering coprocessor is presented which generates halftoned images at high speed. The proposed hardware architecture is based on a pipelined and scalable design ... View full abstract»

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  • MOVIE: a building block for the design of real time simulator of moving pictures compression algorithms

    Publication Year: 1995, Page(s):193 - 203
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper shows how a real-time simulator of moving pictures compression algorithms can be rapidly assembled using a basic building block, here called MOVIE (MOdule for Video Experimentation). The internal architecture of the MOVIE VLSI chip can be compared to a small systolic machine made of a 32-bit I/O processor, a reduced linear array of 16-bit computation processors and data video input/outp... View full abstract»

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  • Synthesis of multirate VLSI arrays

    Publication Year: 1995, Page(s):310 - 321
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    Many applications in signal and image processing can be implemented on regular VLSI architectures such as systolic arrays. Multirate arrays, or MRAs are an extension of systolic arrays where different data streams propagate with different clocks. It is known that they can be modelled as systems of uniform recurrence equations over sparse polyhedral domains. Using well known linear index transforma... View full abstract»

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  • The systolic design of a block regularised parameter estimator using hierarchical signal flow graphs

    Publication Year: 1995, Page(s):141 - 144
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Hierarchical Signal Flow Graphs (HSFGs) am used to illustrate the computations and the data flow required for the block regularised parameter estimation algorithm. This algorithm protects the parameter estimation from numerical difficulties associated with insufficiently exciting data or where the behaviour of the underlying model is unknown. Hierarchical signal flow graphs (HSFGs) aid the user's ... View full abstract»

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  • Design of a systolic coprocessor for rational addition

    Publication Year: 1995, Page(s):282 - 289
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    We design a systolic coprocessor for the addition of signed normalized rational numbers. This is the most complicated rational operation: it involves GCD, exact division, multiplication and addition/subtraction. In particular the implementation of GCD and exact division improve significantly (2 to 4 times) previously known solutions. In contrast to the traditional approach, all operations are perf... View full abstract»

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  • Data alignments for modular time-space mappings of BLAS-like algorithms

    Publication Year: 1995, Page(s):34 - 41
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Modular time-space transformations have been recently proposed for algorithm mappings that cannot be described by affine functions. This paper extends affine data alignments to a new class of data alignments, called expanded modular data alignments (EMDAs), for algorithms that are mapped by modular time-space transformations. An EMDA is a set of modular data alignments (MDAs) which are described b... View full abstract»

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  • Time-optimal ranking algorithms on sorted matrices

    Publication Year: 1995, Page(s):42 - 53
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Answering rank queries is a recurring operation in various application domains including geographic data processing, information retrieval, database design, information management, and medical image processing. Many of these applications involve data stored in a matrix satisfying a number of properties. One property that occurs time and again in applications specifies that the rows and the columns... View full abstract»

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  • Precise tiling for uniform loop nests

    Publication Year: 1995, Page(s):330 - 337
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The subject of this article is a hyperplane partitioning problem applied to perfect loop nests. This work is aimed at increasing the computation granularity to reduce the overhead due to communication. This study is different from previous work as it takes redundant communication into account. We propose an algorithm giving the optimal solution and various examples to show the validity of this rep... View full abstract»

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  • A simple array processor for binary prefix sums

    Publication Year: 1995, Page(s):113 - 120
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    The task of computing the prefix sums of a binary sequence (BPS, for short) arises frequently in expression evaluation, data and storage compaction, routing, processor assignment, and operating system design. The main goal of this work is to propose an efficient special-purpose architecture for the BPS problem. Our design exploits a novel and elegant idea that allows us to considerably reduce the ... View full abstract»

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  • Column compression pipelined multipliers

    Publication Year: 1995, Page(s):93 - 103
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessary to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, ... View full abstract»

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  • Implementation of parallel arithmetic in a cellular automaton

    Publication Year: 1995, Page(s):238 - 245
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    We describe an approach to parallel computation using particle propagation and collisions in a one-dimensional cellular automaton using a Particle model-a Particle Machine (PM). Such a machine has the parallelism, structural regularity, and local connectivity of systolic arrays, but is general and programmable. It contains no explicit multipliers, adders, or other fixed arithmetic operations; thes... View full abstract»

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  • Systolic filter for fast DNA similarity search

    Publication Year: 1995, Page(s):145 - 156
    Cited by:  Papers (1)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    This paper presents a systolic filter for speeding up the scan of DNA databases. The filter acts as a co-processor which performs the more intensive computations occurring during the process. Our validation, based on a FPGA prototype board tightly connected to a workstation, has shown that the filter may boost the performance of the machine by a factor ranging from 50 to 400 over current workstati... View full abstract»

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  • Multilayer cellular algorithm for complex number multiplication

    Publication Year: 1995, Page(s):290 - 297
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A new multilayer cellular algorithm for complex number multiplication is presented. The upper estimate of the time complexity is obtained. The design is based on an original model of distributed computation which is called Parallel Substitution Algorithm View full abstract»

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  • The naive execution of affine recurrence equations

    Publication Year: 1995, Page(s):1 - 12
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    In recognition of the fundamental relation between regular arrays and systems of affine recurrence equations, the ALPHA language was developed as the basis of a computer aided design methodology for regular array architectures. ALPHA is used to initially specify algorithms at a very high algorithmic level. Regular array architectures can then be derived from the algorithmic specification using a t... View full abstract»

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  • Input buffering requirements of a systolic array for the inverse discrete wavelet transform

    Publication Year: 1995, Page(s):166 - 173
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The Discrete Wavelet Transform (DWT) is a signal processing technique popularised by its results in data compression. Considerable work has been done in designing novel architectures to perform the DWT, including a systolic architecture designed by the authors, but little attention has been given to the inverse DWT which is needed in applications such as data compression for signal reconstruction.... View full abstract»

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  • Recomputing by operand exchanging: a time-redundancy approach for fault-tolerant neural networks

    Publication Year: 1995, Page(s):54 - 64
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    The use of neural networks in mission-critical applications requires concurrent error detection and correction at architectural level to provide high consistency and reliability of system's outputs. Time redundancy allows for fault tolerance in digital realizations with low circuit complexity increase. In this paper, we propose the use of REcomputation with eXchanged Operands-an approach based on ... View full abstract»

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  • Bit level block matching systolic arrays

    Publication Year: 1995, Page(s):214 - 221
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    We present two bit-level systolic arrays for block matching which are designed by using a well-known methodology. Hardware complexities and speeds of both bit-level designs and conventional word-level arrays are compared by using synthesis tools. We pay special attention to a class of issues which were somewhat overlooked by previous publications, including power consumption due to high frequency,... View full abstract»

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  • Parallel sequence comparison and alignment

    Publication Year: 1995, Page(s):137 - 140
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Sequence comparisons, a vital research tool in computational biology, is based on a simple O(n2) algorithm that easily maps to a linear array of processors. This paper reviews and compares high-performance sequence analysis on general-purpose supercomputers and single-purpose, reconfigurable, and programmable co-processors. The difficulty of comparing hardware from published performance... View full abstract»

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  • The VLSI design and implementation of the array processors of a multilayer vision system architecture

    Publication Year: 1995, Page(s):125 - 128
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    This paper describes the VLSI design and simulation of the lower layer processors of the KYDON vision system. KYDON is a completely autonomous, hierarchical, multilayered image understanding system. The VLSI design of the individual components as well as the timing simulation results of the processor array have been presented. The system runs at 50 MHz and promises a high processing rate of 300 im... View full abstract»

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  • A processor-time-minimal schedule for 3D rectilinear mesh algorithms

    Publication Year: 1995, Page(s):26 - 33
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The paper, using a directed acyclic graph (dag) model of algorithms, investigates precedence constrained multiprocessor schedules for the nx×ny×nz directed rectilinear mesh. Its completion requires at least nx+ny +nz-2 multiprocessor steps. Time-minimal multiprocessor schedules that use as few processors as possible are ... View full abstract»

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  • Parallel implementation of the full search block matching algorithm for motion estimation

    Publication Year: 1995, Page(s):182 - 192
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    Motion estimation is a key technique in most algorithms for video compression and particularly in the MPEG and H.261 standards. The most frequently used technique is based on a Full Search Block Matching Algorithm which is highly computing intensive and requires the use of special purpose architectures to obtain real-time performance. We propose an approach to the parallel implementation of the Fu... View full abstract»

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  • A processor for staggered interval arithmetic

    Publication Year: 1995, Page(s):104 - 112
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    The paper presents the design of a high-speed processor which performs staggered interval arithmetic. Each staggered interval is represented as the sum of a set of floating point numbers plus an interval, which consists of two floating point endpoints. Staggered interval arithmetic allows the precision of the computation to be specified and the accuracy of the result to be determined. Efficient ar... View full abstract»

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  • Horizontal microcode compaction for programmable systolic accelerators

    Publication Year: 1995, Page(s):85 - 92
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    This paper addresses the problem of compacting microcode for complex systolic systems used as accelerators for traditional computers. For this sort of system, the purpose is to have a low-level programming paradigm that is simple enough for those users that are not completely aware of hardware details. The microcode should be issued from a high-level language application developed on the host proc... View full abstract»

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