Proceedings The International Conference on Application Specific Array Processors

24-26 July 1995

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  • Proceedings The International Conference on Application Specific Array Processors

    Publication Year: 1995
    Request permission for commercial reuse | |PDF file iconPDF (154 KB)
    Freely Available from IEEE
  • Index of Authors

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (51 KB)

    Presents an index of the authors whose papers are published in the conference. View full abstract»

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  • A scalable halftoning coprocessor architecture

    Publication Year: 1995, Page(s):76 - 84
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (436 KB)

    Exact-angle superscreen dithering requires large dither tiles. Since storing precomputed screen elements for each intensity level would require too much memory, dithering must be executed on the fly at halftoning time. For this purpose a dithering coprocessor is presented which generates halftoned images at high speed. The proposed hardware architecture is based on a pipelined and scalable design ... View full abstract»

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  • Minimizing synchronization overhead in statically scheduled multiprocessor systems

    Publication Year: 1995, Page(s):298 - 309
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (648 KB)

    Synchronization overhead can significantly degrade performance in embedded multiprocessor systems. This paper develops techniques to determine a minimal set of processor synchronizations that are essential for correct execution in an embedded multiprocessor implementation. Our study is based in the context of self-timed execution of iterative dataflow programs; dataflow programming in this form ha... View full abstract»

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  • Input buffering requirements of a systolic array for the inverse discrete wavelet transform

    Publication Year: 1995, Page(s):166 - 173
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (348 KB)

    The Discrete Wavelet Transform (DWT) is a signal processing technique popularised by its results in data compression. Considerable work has been done in designing novel architectures to perform the DWT, including a systolic architecture designed by the authors, but little attention has been given to the inverse DWT which is needed in applications such as data compression for signal reconstruction.... View full abstract»

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  • Design and implementation of a parallel image processor chip for a SIMD array processor

    Publication Year: 1995, Page(s):66 - 75
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    This paper presents the design and implementation of a sliding memory plane (SliM) image processor chip to build a mesh-connected SIMD architecture called a SliM array processor. The SliM image processor chip consists of 5×5 processing elements (PEs) connected by a mesh topology. A set of SliM image processor chips can form the SliM array processor. Due to the idea of sliding, that is, overl... View full abstract»

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  • Multilayer cellular algorithm for complex number multiplication

    Publication Year: 1995, Page(s):290 - 297
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (420 KB)

    A new multilayer cellular algorithm for complex number multiplication is presented. The upper estimate of the time complexity is obtained. The design is based on an original model of distributed computation which is called Parallel Substitution Algorithm View full abstract»

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  • A solid translation engine using ray representation

    Publication Year: 1995, Page(s):157 - 165
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    We describe an extension to the geometric domain of solid modeling to include solids defined by spatial sweeping and Minkowski sums. We develop an efficient, parallel algorithm for the translation of such solid models. An architecture and design of an array processor that implements this algorithm are presented. We discuss some applications of the new computer to solid modeling an CAD/CAM and mode... View full abstract»

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  • Recomputing by operand exchanging: a time-redundancy approach for fault-tolerant neural networks

    Publication Year: 1995, Page(s):54 - 64
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (696 KB)

    The use of neural networks in mission-critical applications requires concurrent error detection and correction at architectural level to provide high consistency and reliability of system's outputs. Time redundancy allows for fault tolerance in digital realizations with low circuit complexity increase. In this paper, we propose the use of REcomputation with eXchanged Operands-an approach based on ... View full abstract»

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  • Digit on-line large radix CORDIC rotator

    Publication Year: 1995, Page(s):246 - 257
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (460 KB)

    Many applications figure the evaluation of rotations at high speeds. However there is a trade-off between the chip area and the latency. In this paper we develop a digit on-line pipelined array architecture based on the radix-4 CORDIC algorithm in rotation mode. The radix-4 CORDIC algorithm halves the number of microrotations with respect the traditionally radix-2 algorithm with the drawback of a ... View full abstract»

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  • The MGAP's programming environment and the *C++ language

    Publication Year: 1995, Page(s):121 - 124
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (200 KB)

    The MGAP is a special-purpose, workstation co-processor board in which the computing elements are fine grain processors implemented as custom ASICs. In this paper we present the language *CC++, used for programming on the MGAP. Using the class concept of C++ we create special parallel data-types like bit, digit, word and array and overload operators to manipulate the parallel data required by the ... View full abstract»

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  • A processor for staggered interval arithmetic

    Publication Year: 1995, Page(s):104 - 112
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (416 KB)

    The paper presents the design of a high-speed processor which performs staggered interval arithmetic. Each staggered interval is represented as the sum of a set of floating point numbers plus an interval, which consists of two floating point endpoints. Staggered interval arithmetic allows the precision of the computation to be specified and the accuracy of the result to be determined. Efficient ar... View full abstract»

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  • Design of a systolic coprocessor for rational addition

    Publication Year: 1995, Page(s):282 - 289
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (344 KB)

    We design a systolic coprocessor for the addition of signed normalized rational numbers. This is the most complicated rational operation: it involves GCD, exact division, multiplication and addition/subtraction. In particular the implementation of GCD and exact division improve significantly (2 to 4 times) previously known solutions. In contrast to the traditional approach, all operations are perf... View full abstract»

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  • Systolic filter for fast DNA similarity search

    Publication Year: 1995, Page(s):145 - 156
    Cited by:  Papers (1)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    This paper presents a systolic filter for speeding up the scan of DNA databases. The filter acts as a co-processor which performs the more intensive computations occurring during the process. Our validation, based on a FPGA prototype board tightly connected to a workstation, has shown that the filter may boost the performance of the machine by a factor ranging from 50 to 400 over current workstati... View full abstract»

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  • Time-optimal ranking algorithms on sorted matrices

    Publication Year: 1995, Page(s):42 - 53
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (648 KB)

    Answering rank queries is a recurring operation in various application domains including geographic data processing, information retrieval, database design, information management, and medical image processing. Many of these applications involve data stored in a matrix satisfying a number of properties. One property that occurs time and again in applications specifies that the rows and the columns... View full abstract»

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  • Implementation of parallel arithmetic in a cellular automaton

    Publication Year: 1995, Page(s):238 - 245
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (316 KB)

    We describe an approach to parallel computation using particle propagation and collisions in a one-dimensional cellular automaton using a Particle model-a Particle Machine (PM). Such a machine has the parallelism, structural regularity, and local connectivity of systolic arrays, but is general and programmable. It contains no explicit multipliers, adders, or other fixed arithmetic operations; thes... View full abstract»

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  • Horizontal microcode compaction for programmable systolic accelerators

    Publication Year: 1995, Page(s):85 - 92
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (420 KB)

    This paper addresses the problem of compacting microcode for complex systolic systems used as accelerators for traditional computers. For this sort of system, the purpose is to have a low-level programming paradigm that is simple enough for those users that are not completely aware of hardware details. The microcode should be issued from a high-level language application developed on the host proc... View full abstract»

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  • A design tool for the specification and the simulation of array processors architectures application to image processing: the extraction of regions of interests

    Publication Year: 1995, Page(s):322 - 329
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    This paper deals with a CAD tool dedicated to the design and the simulation of specific array processor architectures. These architectures are described into a specific notation which includes major characteristics of the VHDL syntax. This language provides a very concise and legible means to specify array processors. A preprocessor generates full standard VHDL code describing the behavior of the ... View full abstract»

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  • Synthesis of VLSI architectures for two-dimensional discrete wavelet transforms

    Publication Year: 1995, Page(s):174 - 181
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (428 KB)

    We propose VLSI architectures with parallel I/O capability to compute the Two-Dimensional Discrete Wavelet Transform. Our design can handle large images arriving at high frame rates. A video codec based on our architecture can support multiple channels in parallel and can provide the needed performance for network based video applications. Our architecture with parallel I/O offers a solution for t... View full abstract»

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  • CORDIC architectures with parallel compensation of the scale factor

    Publication Year: 1995, Page(s):258 - 269
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (392 KB)

    The compensation of scale factor imposes significant computation overhead on the CORDIC algorithm. In this paper we will propose two algorithms and architectures in order to perform the compensation of the scale factor in parallel with the computation of the CORDIC iterations. This way it is not necessary to carry out the final multiplication or add scaling iterations in order to achieve the compe... View full abstract»

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  • The VLSI design and implementation of the array processors of a multilayer vision system architecture

    Publication Year: 1995, Page(s):125 - 128
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (212 KB)

    This paper describes the VLSI design and simulation of the lower layer processors of the KYDON vision system. KYDON is a completely autonomous, hierarchical, multilayered image understanding system. The VLSI design of the individual components as well as the timing simulation results of the processor array have been presented. The system runs at 50 MHz and promises a high processing rate of 300 im... View full abstract»

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  • A simple array processor for binary prefix sums

    Publication Year: 1995, Page(s):113 - 120
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (392 KB)

    The task of computing the prefix sums of a binary sequence (BPS, for short) arises frequently in expression evaluation, data and storage compaction, routing, processor assignment, and operating system design. The main goal of this work is to propose an efficient special-purpose architecture for the BPS problem. Our design exploits a novel and elegant idea that allows us to considerably reduce the ... View full abstract»

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  • Column compression pipelined multipliers

    Publication Year: 1995, Page(s):93 - 103
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    The paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessary to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, ... View full abstract»

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  • Precise tiling for uniform loop nests

    Publication Year: 1995, Page(s):330 - 337
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    The subject of this article is a hyperplane partitioning problem applied to perfect loop nests. This work is aimed at increasing the computation granularity to reduce the overhead due to communication. This study is different from previous work as it takes redundant communication into account. We propose an algorithm giving the optimal solution and various examples to show the validity of this rep... View full abstract»

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  • Parallel implementation of the full search block matching algorithm for motion estimation

    Publication Year: 1995, Page(s):182 - 192
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (576 KB)

    Motion estimation is a key technique in most algorithms for video compression and particularly in the MPEG and H.261 standards. The most frequently used technique is based on a Full Search Block Matching Algorithm which is highly computing intensive and requires the use of special purpose architectures to obtain real-time performance. We propose an approach to the parallel implementation of the Fu... View full abstract»

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