Proceedings The International Conference on Application Specific Array Processors

24-26 July 1995

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  • Proceedings The International Conference on Application Specific Array Processors

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (154 KB)
    Freely Available from IEEE
  • Index of Authors

    Publication Year: 1995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB)

    Presents an index of the authors whose papers are published in the conference. View full abstract»

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  • Interfacing FPGA/VLSI processor arrays

    Publication Year: 1995, Page(s):230 - 237
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Mapping DSP algorithms to FPGA/VLSI circuits is an important issue in Application-Specific Array Processor design. Since a DSP algorithm can be abstracted as a graph where each node is a shift-invariant DG (Dependence Graph) and the edges denote the data flow, it is possible to map a DSP algorithm to a set of processor arrays with some interface circuits. The interface design depends on the projec... View full abstract»

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  • Techniques for yield enhancement of VLSI adders

    Publication Year: 1995, Page(s):222 - 229
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    For VLSI application-specific arrays and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modifications. In this paper, we compare these two yield enhancement approaches by using adders as an example. Our yield projections indicate that the layout modification technique is more efficient when the defect density is low, while reconf... View full abstract»

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  • Parallel implementation of the full search block matching algorithm for motion estimation

    Publication Year: 1995, Page(s):182 - 192
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    Motion estimation is a key technique in most algorithms for video compression and particularly in the MPEG and H.261 standards. The most frequently used technique is based on a Full Search Block Matching Algorithm which is highly computing intensive and requires the use of special purpose architectures to obtain real-time performance. We propose an approach to the parallel implementation of the Fu... View full abstract»

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  • Multilayer cellular algorithm for complex number multiplication

    Publication Year: 1995, Page(s):290 - 297
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A new multilayer cellular algorithm for complex number multiplication is presented. The upper estimate of the time complexity is obtained. The design is based on an original model of distributed computation which is called Parallel Substitution Algorithm View full abstract»

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  • Systolic filter for fast DNA similarity search

    Publication Year: 1995, Page(s):145 - 156
    Cited by:  Papers (1)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    This paper presents a systolic filter for speeding up the scan of DNA databases. The filter acts as a co-processor which performs the more intensive computations occurring during the process. Our validation, based on a FPGA prototype board tightly connected to a workstation, has shown that the filter may boost the performance of the machine by a factor ranging from 50 to 400 over current workstati... View full abstract»

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  • Bit level block matching systolic arrays

    Publication Year: 1995, Page(s):214 - 221
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    We present two bit-level systolic arrays for block matching which are designed by using a well-known methodology. Hardware complexities and speeds of both bit-level designs and conventional word-level arrays are compared by using synthesis tools. We pay special attention to a class of issues which were somewhat overlooked by previous publications, including power consumption due to high frequency,... View full abstract»

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  • Synthesis of VLSI architectures for two-dimensional discrete wavelet transforms

    Publication Year: 1995, Page(s):174 - 181
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    We propose VLSI architectures with parallel I/O capability to compute the Two-Dimensional Discrete Wavelet Transform. Our design can handle large images arriving at high frame rates. A video codec based on our architecture can support multiple channels in parallel and can provide the needed performance for network based video applications. Our architecture with parallel I/O offers a solution for t... View full abstract»

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  • Design of a systolic coprocessor for rational addition

    Publication Year: 1995, Page(s):282 - 289
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    We design a systolic coprocessor for the addition of signed normalized rational numbers. This is the most complicated rational operation: it involves GCD, exact division, multiplication and addition/subtraction. In particular the implementation of GCD and exact division improve significantly (2 to 4 times) previously known solutions. In contrast to the traditional approach, all operations are perf... View full abstract»

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  • Recomputing by operand exchanging: a time-redundancy approach for fault-tolerant neural networks

    Publication Year: 1995, Page(s):54 - 64
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    The use of neural networks in mission-critical applications requires concurrent error detection and correction at architectural level to provide high consistency and reliability of system's outputs. Time redundancy allows for fault tolerance in digital realizations with low circuit complexity increase. In this paper, we propose the use of REcomputation with eXchanged Operands-an approach based on ... View full abstract»

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  • The systolic design of a block regularised parameter estimator using hierarchical signal flow graphs

    Publication Year: 1995, Page(s):141 - 144
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Hierarchical Signal Flow Graphs (HSFGs) am used to illustrate the computations and the data flow required for the block regularised parameter estimation algorithm. This algorithm protects the parameter estimation from numerical difficulties associated with insufficiently exciting data or where the behaviour of the underlying model is unknown. Hierarchical signal flow graphs (HSFGs) aid the user's ... View full abstract»

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  • Revisiting the decomposition of Karp, Miller and Winograd

    Publication Year: 1995, Page(s):13 - 25
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    This paper is devoted to the construction of multi-dimensional schedules for a system of uniform recurrence equations. We show that this problem is dual to the problem of computability of a system of uniform recurrence equations. We propose a new study of the decomposition algorithm first proposed by Karp, Miller and Winograd: we base our implementation on linear programming resolutions whose dual... View full abstract»

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  • Digit on-line large radix CORDIC rotator

    Publication Year: 1995, Page(s):246 - 257
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Many applications figure the evaluation of rotations at high speeds. However there is a trade-off between the chip area and the latency. In this paper we develop a digit on-line pipelined array architecture based on the radix-4 CORDIC algorithm in rotation mode. The radix-4 CORDIC algorithm halves the number of microrotations with respect the traditionally radix-2 algorithm with the drawback of a ... View full abstract»

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  • Motion estimation algorithms on fine grain array processors

    Publication Year: 1995, Page(s):204 - 213
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Motion estimation plays a key role in video coding, (e.g., video telephone, MPEG, HDTV). Among the previous motion estimation algorithms, full-search block matching algorithms (BMA) are preferred because of their simplicity and lower control overhead when those algorithms are implemented in VLSI array processors. Previous full-search BMAs have considered one block matching at a time. There exist, ... View full abstract»

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  • Input buffering requirements of a systolic array for the inverse discrete wavelet transform

    Publication Year: 1995, Page(s):166 - 173
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The Discrete Wavelet Transform (DWT) is a signal processing technique popularised by its results in data compression. Considerable work has been done in designing novel architectures to perform the DWT, including a systolic architecture designed by the authors, but little attention has been given to the inverse DWT which is needed in applications such as data compression for signal reconstruction.... View full abstract»

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  • A scalable halftoning coprocessor architecture

    Publication Year: 1995, Page(s):76 - 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Exact-angle superscreen dithering requires large dither tiles. Since storing precomputed screen elements for each intensity level would require too much memory, dithering must be executed on the fly at halftoning time. For this purpose a dithering coprocessor is presented which generates halftoned images at high speed. The proposed hardware architecture is based on a pipelined and scalable design ... View full abstract»

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  • An array processor for inner product computations using a Fermat number ALU

    Publication Year: 1995, Page(s):270 - 281
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    This paper explores an architecture for parallel independent computations of inner products over the direct product ring ℜ257×17. The structure is based on the polynomial mapping of the Modulus Replication RNS for calculations over dynamic ranges much larger than the product of the computational moduli. We show that the computational ring is optimal for our purposes, and intro... View full abstract»

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  • Column compression pipelined multipliers

    Publication Year: 1995, Page(s):93 - 103
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessary to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, ... View full abstract»

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  • Precise tiling for uniform loop nests

    Publication Year: 1995, Page(s):330 - 337
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The subject of this article is a hyperplane partitioning problem applied to perfect loop nests. This work is aimed at increasing the computation granularity to reduce the overhead due to communication. This study is different from previous work as it takes redundant communication into account. We propose an algorithm giving the optimal solution and various examples to show the validity of this rep... View full abstract»

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  • Time-optimal ranking algorithms on sorted matrices

    Publication Year: 1995, Page(s):42 - 53
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Answering rank queries is a recurring operation in various application domains including geographic data processing, information retrieval, database design, information management, and medical image processing. Many of these applications involve data stored in a matrix satisfying a number of properties. One property that occurs time and again in applications specifies that the rows and the columns... View full abstract»

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  • The MGAP's programming environment and the *C++ language

    Publication Year: 1995, Page(s):121 - 124
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    The MGAP is a special-purpose, workstation co-processor board in which the computing elements are fine grain processors implemented as custom ASICs. In this paper we present the language *CC++, used for programming on the MGAP. Using the class concept of C++ we create special parallel data-types like bit, digit, word and array and overload operators to manipulate the parallel data required by the ... View full abstract»

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  • Parallel sequence comparison and alignment

    Publication Year: 1995, Page(s):137 - 140
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Sequence comparisons, a vital research tool in computational biology, is based on a simple O(n2) algorithm that easily maps to a linear array of processors. This paper reviews and compares high-performance sequence analysis on general-purpose supercomputers and single-purpose, reconfigurable, and programmable co-processors. The difficulty of comparing hardware from published performance... View full abstract»

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  • The naive execution of affine recurrence equations

    Publication Year: 1995, Page(s):1 - 12
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    In recognition of the fundamental relation between regular arrays and systems of affine recurrence equations, the ALPHA language was developed as the basis of a computer aided design methodology for regular array architectures. ALPHA is used to initially specify algorithms at a very high algorithmic level. Regular array architectures can then be derived from the algorithmic specification using a t... View full abstract»

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  • Implementation of parallel arithmetic in a cellular automaton

    Publication Year: 1995, Page(s):238 - 245
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    We describe an approach to parallel computation using particle propagation and collisions in a one-dimensional cellular automaton using a Particle model-a Particle Machine (PM). Such a machine has the parallelism, structural regularity, and local connectivity of systolic arrays, but is general and programmable. It contains no explicit multipliers, adders, or other fixed arithmetic operations; thes... View full abstract»

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