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Proceedings Sixth International Parallel Processing Symposium

23-26 March 1992

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Displaying Results 1 - 25 of 119
  • Comparisons and analysis of massively parallel SIMD architectures for parallel logic simulation

    Publication Year: 1992, Page(s):671 - 674
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB)

    This paper compares and analyzes massively parallel SIMD architectures as processing environments for parallel logic simulation. The CM-2 and the MP-1 are considered as target machines for the comparison. Detailed contrasts between the two parallel schemes are made based on actual simulation results and system performance. Distributed event-driven simulation protocols are used to obtain experiment... View full abstract»

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  • Proceedings. Sixth International Parallel Processing Symposium (Cat. No.92TH0419-2)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (30 KB)
    Freely Available from IEEE
  • Prototyping N-body simulation in Proteus

    Publication Year: 1992, Page(s):476 - 482
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    This paper explores the use of Proteus, an architecture-independent language suitable for prototyping parallel and distributed programs. Proteus is a high-level imperative notation based on sets and sequences with a single construct for the parallel composition of processes communicating through shared memory. Several different parallel algorithms for N-body simulation are presented in Proteus, il... View full abstract»

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  • A library environment for distributed memory multiprocessors

    Publication Year: 1992, Page(s):483 - 486
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The authors propose the design of a library environment, called PARUL (PARallel User Library), for distributed memory multiprocessor systems. An important feature of the environment is that it allows the data distributed for use of a library function as well as the results generated by the function to be retained in the network of processors to be used by subsequent library functions. The user of ... View full abstract»

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  • Performability studies of hypercube architectures

    Publication Year: 1992, Page(s):488 - 495
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    The authors propose a novel technique to study composite reliability and performance (performability) measures of hypercube systems using generalized stochastic Petri nets (GSPNs). This technique essentially consists of the following: (i) a GSPN reliability model; (ii) a GSPN performance model; and (iii) a way of combining the results from these two models. Models and performability results for an... View full abstract»

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  • Generalized compressed tree machines

    Publication Year: 1992, Page(s):95 - 102
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Parallel machines interconnecting up to thousands of processors have been proposed and recently built. One of the earliest and the most prominent one is a complete binary tree machine. The authors propose a family of tree machines called generalized compressed tree machines. Generalized compressed tree machines may, in general, be viewed as a derivative of the complete binary tree networks View full abstract»

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  • Banyan heap machine

    Publication Year: 1992, Page(s):224 - 231
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    New designs for performing a group of priority queue operations on a set of elements are presented. Processors in this design, called the banyan heap machine are connected together to form a linear chain. The algorithms for the banyan heap machine are the generalization of binary heap algorithms to a more general acyclic graph called banyan. This design, unlike existing designs, requires fewer pro... View full abstract»

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  • VLSI architectures for recursive and multiple-window order statistic filtering

    Publication Year: 1992, Page(s):294 - 297
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Based on a recently developed class of sorting networks, new VLSI architectures suitable for order statistic filtering are developed. The major advantage of these architectures is minimal response-time regardless of the number of stages in the pipeline; an effective characteristic for implementing recursive order statistic filters. The devised word-parallel architecture is the only one introduced ... View full abstract»

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  • Cluster-M parallel programming model

    Publication Year: 1992, Page(s):462 - 465
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Present a novel parallel programming model called Cluster-M. This model provides an environment for efficiently designing highly parallel machine independent software. Cluster-M is a generic model consisting of a collection of clusters such that each cluster represents a set of processors having similar level of interconnectivity. For every multiprocessor architecture there exists a Cluster-M repr... View full abstract»

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  • A functional execution model for a non-dataflow tagged token architecture

    Publication Year: 1992, Page(s):496 - 501
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    The author proposes a new execution model for a non-dataflow tagged-token architecture which is not Petri-net based but rather more closely related to the lambda calculus. The model exploits a functional programming style having applicative-order evaluation. The computation's execution graph is dynamically generated according to easily understood dynamic tagging rules which have been demonstrated ... View full abstract»

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  • Parallel implementation of divide-and-conquer algorithms on binary de Bruijn networks

    Publication Year: 1992, Page(s):103 - 107
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Studies the problem of parallel implementation of divide-and-conquer algorithms on binary de Bruijn network using a temporal binomial tree (rather than the usual binary tree) computation structure. Two cases of message volumes are considered: (i) uniform, and (ii) logarithmically decreasing (increasing) weights. A single mapping is proposed for both cases. It has average extra dilation 1 and is co... View full abstract»

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  • Dominant representations: a paradigm for mapping parallel computations

    Publication Year: 1992, Page(s):67 - 71
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Proposes a simple paradigm for constructing heuristics for the static assignment of parallel programs onto asynchronous, distributed memory, multiprocessor architectures. The proposed paradigm involves capturing the dominant computation and communication components of an application and using this relatively simpler program representation to determine an assignment. Thus, the mapping problem is re... View full abstract»

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  • A latency-hiding scheme for multiprocessors with buffered multistage networks

    Publication Year: 1992, Page(s):39 - 42
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Multistage networks for large-scale shared-memory multiprocessors are buffered to increase the throughput and hide the latency. This is achieved by pipelining consecutive memory requests from the same processor. However, unrestrictive pipelining may violate strict memory consistency models such as sequential consistency since memory requests are not guaranteed to be performed in program order. The... View full abstract»

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  • Determining maximum k-width-connectivity on meshes

    Publication Year: 1992, Page(s):234 - 241
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    Let I be a n×n binary image stored in a n×n mesh of processors with one pixel per processor. Image I is k-width-connected if, informally, between any pair of pixels of value `I' there exists a path of width k (composed of 1-pixels only). The authors consider the problem of determining the largest integer k... View full abstract»

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  • Preventing recursion deadlock in concurrent object-oriented systems

    Publication Year: 1992, Page(s):665 - 670
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    This paper presents solutions to the problem of deadlock due to recursion in concurrent object-oriented programming languages. Two language-independent, system-level mechanisms are proposed: a novel technique using multi-ported objects, and a named-threads scheme that borrows from previous work in distributed computing. The authors compare the solutions, and present an analysis of their relative m... View full abstract»

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  • A software tool for cellular mapping of discrete unitary transforms

    Publication Year: 1992, Page(s):298 - 304
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    The paper describes a software tool that facilitates mapping onto array processors of a wide class of unitary transforms. The mapping formalism of the tool depends on matrix factorizations combined with abstract constructs that link the linear concepts to a model of the array's architecture. A prototype design of the tool is graphics-based and user-driven View full abstract»

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  • Associative parallel lexing

    Publication Year: 1992, Page(s):466 - 469
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Presents near constant time associative parallel lexing (APL) algorithms. The best time complexity thus far claimed is O(log n) (n denotes the number of input characters for the parallel prefix lexing (PPL) algorithm. The linear state recording step in the PPL algorithm, which needs to be done only once for each grammar has been ignored in claiming the log n tim... View full abstract»

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  • Visualization of a simple routing scheme for meshes

    Publication Year: 1992, Page(s):606 - 609
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The authors propose a simple quasi-static routing scheme for buffered mesh connected network computers. Under the assumption of uniform traffic demands, it is demonstrated numerically that their simple routing scheme achieves near-optimal performance; in the sense of minimizing the total number of outstanding packets in a Jackson-type network. Simulation results are also presented for the case of ... View full abstract»

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  • The vesicular dataflow model

    Publication Year: 1992, Page(s):502 - 507
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The Vesicular Dataflow (VDF) model is presented in the paper. The VDF model has been formulated to introduce a way of storing and retrieving information and hence to reduce the main drawback of the basic DF model. Tokens can be stored in vesicles in the VDF model and then distributed in non-deterministic way. State-dependent computations and global variables can be expressed in the dataflow manner... View full abstract»

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  • A near-optimal parallel algorithm for edge-coloring outerplanar graphs

    Publication Year: 1992, Page(s):262 - 266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The article presents a parallel EREW PRAM algorithm that runs in O(log2n) time using n/logn processors to optimally color the edges of an outerplanar graph. The algorithm improves the best known algorithm in both time, and number of processors. This more efficient algorithm is a result of a new approach for solving the problem. Also presented is a par... View full abstract»

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  • Embedding and reconfiguration of binary trees in faulty hypercubes

    Publication Year: 1992, Page(s):2 - 9
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    Considers the problem of embedding and reconfiguring binary tree structures in faulty hypercubes. The authors assume that the number of faulty nodes is about n, where n is the number of dimensions of the hypercube; they further assume that the location of faulty nodes are known. The embedding techniques are based on a key concept called free dimension, which can be used to partit... View full abstract»

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  • Efficient parallel algorithms for selection and searching on sorted matrices

    Publication Year: 1992, Page(s):108 - 111
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Parallel algorithms for more general versions of the well known selection and searching problems are formulated. The authors look at these problems when the set of elements can be represented as an n ×n matrix with sorted rows and columns. The selection algorithm takes O(lognloglogn log* n) time with O(n/log nlo... View full abstract»

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  • Assignment of ADT modules to processors

    Publication Year: 1992, Page(s):72 - 75
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The utilization of reusable software components can help to reduce the complexity of developing and maintaining parallel programs, but can lead to inefficiencies. The potential inefficiencies are addressed by providing a model of parallel execution (asynchronous remote procedure call, or ARPC) that not only speeds up programs, but also encourages the development of layered software by increasing p... View full abstract»

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  • A hierarchical directory scheme for large-scale cache-coherent multiprocessors

    Publication Year: 1992, Page(s):43 - 46
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Cache coherence problem is a major design issue for shared-memory multiprocessors. As the system size scales, traditional bus-based snoopy cache coherence schemes are no longer adequate. Instead, the directory-based scheme is a promising approach to deal with the large-scale cache coherence problem. However, the storage overhead of directory schemes often becomes too prohibitive as the system size... View full abstract»

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  • Scalable parallel arc consistency algorithms for shared memory computers

    Publication Year: 1992, Page(s):242 - 249
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    The paper introduces three scalable static parallel arc consistency algorithms (SPAC-1, SPAC-2 and SPAC-3) designed for any general-purpose shared memory multiple instruction-stream, multiple data-stream (MIMD) computer. The algorithms are intended for constraint satisfaction problems in AI applications. Arc consistency is ensured of a finite domain binary constraint network. Through actual machin... View full abstract»

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