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University/Government/Industry Microelectronics Symposium, 1995., Proceedings of the Eleventh Biennial

Date 16-17 May 1995

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  • Eleventh Biennial University/ Government/Industry Microelectronics Symposium

    Publication Year: 1995
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    Freely Available from IEEE
  • An investigation of the chemical mechanical polishing of copper thin films to form in-laid interconnections in the dielectric (SiO2 ) films

    Publication Year: 1995 , Page(s): 120 - 121
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    Summary form only given. Describes an investigation of the chemical mechanical polishing (CMP) of copper films for the purpose of delineating and planarizing inlaid copper interconnections for multilevel metallization in silicon integrated circuits. Copper CMP has been shown to be an effective method of patterning interconnections and for providing the global planarity required to build multilevel structures. CMP processes in general, however, remain poorly understood and unoptimized. The task of optimizing a process is hampered by the lack of a fundamental understanding of the removal mechanisms at work in CMP. A fundamental understanding of these mechanisms will allow greater control of the CMP process in the manufacturing environment View full abstract»

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  • A microwave model for high electron mobility transistors

    Publication Year: 1995 , Page(s): 182 - 186
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    A physically based model is used to predict the S and Y-parameters of the high electron mobility transistor as function of the applied gate bias and the operating frequency. The model is used to estimate the power gain and the maximum stable gain characteristics for HEMTs with different physical and structural parameters which helps in the optimization of the amplifier design View full abstract»

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  • A monolithically integrated silicon NMOS-PIN photoreceiver

    Publication Year: 1995 , Page(s): 140 - 146
    Cited by:  Papers (1)
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    For large-volume optoelectronics applications, the low cost, manufacturability and reliability of silicon MOSFET technology are advantageous. In addition, silicon photodetectors operate quite efficiently at the 0.8 μm wavelength of economical AlGaAs light sources. In this paper, we report on a silicon-based monolithic optical receiver. The fabrication of the integrated lightwave receiver was carried out on a nominally undoped p-type Si substrate. The p-i-n photodetector was fabricated directly on the high-resistivity substrate so that the thickness of the detector depletion layer was approximately equal to the optical absorption length of 0.8 μm light in silicon. A more heavily-doped p-well was formed for the NMOSFET fabrication. The silicon photodiodes had a dark current of 20 nA at 5 V, a break-down voltage greater than 60 V, and a zero-bias capacitance of 40 fF. The external quantum efficiency of the photodiode at 870 nm was approximately 45% at 5 V without an AR coating, and the bandwidth of the device was approximately 1.5 GHz. Frequency response evaluation of the receiver indicated a bandwidth of 30 MHz with open eye diagrams demonstrated at 40 MB/s View full abstract»

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  • Evaluation of low dielectric constant materials for on-chip interconnects-an industry/university research collaboration

    Publication Year: 1995 , Page(s): 122 - 125
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    This paper describes the collaboration between university and industry in the evaluation of low dielectric materials for on-chip interconnect applications. The collaboration has established selection criteria and characterization methodologies for materials evaluation of dielectric thin films in the micron range. A review on the concerted efforts of semiconductor industry, materials suppliers, university and consortium in materials and processing evaluation and in improving the interlayer dielectrics (ILD) materials in alignment of SIA Technology Roadmap are described. The characterization techniques of thin films and results of materials evaluation are discussed View full abstract»

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  • A first generation generic system simulator (GENESYS) and its relation to the NTRS

    Publication Year: 1995 , Page(s): 147 - 154
    Cited by:  Papers (1)
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    The National Technology Roadmap for Semiconductors (NTRS) presents projections and goals for microelectronics over the next fifteen years. A set of physical and empirical models encompassing material, device, circuit, architecture, interconnection, and packaging characteristics that describe microelectronic systems have been captured in the first generation of GENESYS, a GENEric SYstem Simulator. From technology parameters projected in the NTRS, GENESYS predicts maximum clock frequency, physical size, power dissipation, and packaging requirements of an ASIC. The outputs of GENESYS are compared to the on-chip clock frequency, chip size, and maximum power projections of the NTRS for ASICs, and then used both to calibrate GENESYS and to subject the NTRS projections to self-consistency checks View full abstract»

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  • Semiconductor technology transfer from universities to industry

    Publication Year: 1995 , Page(s): 1 - 5
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    Technology transfer is a critical issue for any corporate or academic research institution. Benefits to the customer are only derived when the research “product” is disseminated out of the research lab and into the commercial environment. At the Semiconductor Research Corporation (SRC), such technology transfer is essential to the success of its cooperative research program. However, universities and semiconductor manufacturing companies have their own distinct cultures, interests and reward systems. This paper identifies some of the major barriers that currently exist in SRC's realm of technology transfer, both technically and managerially. It will also address current and alternative methods for overcoming such barriers and management issues. Additionally, some examples of successes and failures in technology transfer as documented by the SRC are presented. The key role of technology transfer champion/mentor in various phases of technology development and transfer is described. Differences in the methods for transferring technical knowledge, process recipes, software and hardware are highlighted. It is shown that the transfer of semiconductor technology is becoming a new discipline which intertwines engineering with management science View full abstract»

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  • A new methodology for fast development of multilevel metallization for ULSI technology

    Publication Year: 1995 , Page(s): 113 - 117
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    A methodology has been developed for fast process development and integration of multilevel metallization systems for ultra large scale integration technology. This methodology defines a set of primitive processes, which are then arranged in the required configuration to build or develop multilevel metallization systems. Each primitive process will have a predictive model and process control and calibration strategy including a set of test structures. This paper will describe how the methodology defined above has been applied to develop contacts and vias for multilevel metallization View full abstract»

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  • A 2000 transistor p-well CMOS gate array a vehicle for microelectronics manufacturing education

    Publication Year: 1995 , Page(s): 205 - 208
    Cited by:  Papers (2)
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    A 2000 transistor p-well CMOS gate array has been designed for use as a teaching tool in the microelectronic engineering program at RIT. Students in microelectronic engineering study integrated circuit design and integrated circuit manufacturing starting in the first year of the five year program. The gate array is manufactured up to level 8 of the 11 level process by students in 5th year manufacturing classes. Levels 8 through 11 include contact cut, metal-one, via and metal-two. These levels are where the gate array is customized. The first year students design simple digital circuits, learn about schematic capture, simulation, bread boarding and layout. They also complete the wafer fabrication as part of their laboratory experience Students in more advanced courses design more complex analog and digital circuits to be realized using the 2000 transistor gate array. The gate array project has provided an interesting educational experience in design, layout and manufacturing for students from freshmen year to graduate level. The device turn around time is about one week for the last 4 levels of the process View full abstract»

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  • The science and technology of micro-machines: development of an undergraduate course

    Publication Year: 1995 , Page(s): 230 - 236
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    The technological foundations of microelectronics provide the basis for the emerging science and technology of micro-machines. Most instruction in micro-machines has occurred at the graduate level, leaving a relative void in the undergraduate curriculum. With industrial and governmental support, we have incorporated hands-on fabrication and foundry-based device design into a comprehensive undergraduate course View full abstract»

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  • Joint development of a topography simulator at National Semiconductor Corporation and Arizona State University

    Publication Year: 1995 , Page(s): 160 - 163
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    A joint effort between Arizona State University, Tempe, and National Semiconductor Corporation to bring academic research work from a University to the every-day's work at a real production line has been carried out. Ti and TiN sputter deposition processes-collimated as well as uncollimated were studied. By succeeding and exceeding the initial expectations we could demonstrate that theoretical work can be definitely of great value to practical applications. A product has been developed which allows the process engineer a fast and accurate study of the results of changes in various process parameters as well as to monitor the current process View full abstract»

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  • Breakdown mechanisms and stress-induced leakage current in ultra-thin oxides and N2O oxynitrides

    Publication Year: 1995 , Page(s): 90 - 93
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    In this paper, we investigate breakdown mechanisms and stress-induced leakage current (SILC) for conventional thermal oxides and N2O oxynitrides. The role of hole generation and trapping in the breakdown of both thermal oxides and oxynitrides is studied in samples with thicknesses ranging from 33-87 Å. SILC characteristics of these dielectrics thicknesses are scaled downwards; instead there is a “turnaround” near a thickness of 50 Å View full abstract»

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  • SEMATECH and the University of Texas cooperative research in semiconductor manufacturing technology

    Publication Year: 1995 , Page(s): 36 - 40
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    An overview is provided of current research in microelectronics manufacturing technology being conducted by University of Texas graduate students for SEMATECH's Factory Integration division. As part of these planned internships, the candidates for Master of Science degrees in Operations Research selected academic report topics related to factory performance issues for advanced-technology wafer fabrication facilities. The relevance of such work to understanding the robustness of high-technology production operations is discussed. Additionally, the paper critiques the internship program itself, sharing successes and lessons learned View full abstract»

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  • K-12 workplace simulations: a university, government, business and industry collaboration with the Newburgh (NY) Enlarged City School District

    Publication Year: 1995 , Page(s): 27 - 30
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    The staff of the Newburgh, NY, Enlarged City School District queried whether their students would be prepared to enter the workforce of the rapidly changing, highly technological, environmentally conscious world of the 21st century. Were the courses equipping the students with the maths, science, technology, and communication skills they needed? Sensing this concern, the authors embarked upon a multi-faceted approach to career preparation. In buildings throughout the school district, a series of unique workplace simulations have been created for all K-12 students View full abstract»

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  • Characterization of a PVD-TiN as the diffusion barrier/adhesion promoter for use in a multilevel copper interconnection technology

    Publication Year: 1995 , Page(s): 118 - 119
    Cited by:  Papers (1)
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    The use of copper, as the interconnection metal in a multilevel scheme, will require a diffusion barrier/adhesion promoter (DB/AP) layer between the metal and the dielectric. The use of TiN as a DB/AP layer in a first generation copper metallization scheme has thus been investigated. It is projected that this 0.25 μm technology will utilize 0.5 μm wide metal interconnections with aspect ratio of 1.0. Because using a 40 nm TiN cladding will only marginally increase the overall interconnection resistance, this barrier thickness was chosen as the default thickness for this study View full abstract»

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  • Interdisciplinary university research and education in electronic materials

    Publication Year: 1995 , Page(s): 209 - 214
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    Preparing the next generation of leaders in science and technology requires new approaches, often collaborative and interdisciplinary, to university research, education and training. In no area are collaborative approaches more important than in microelectronics. This paper describes the organization, management, and education and outreach activities of a successful interdisciplinary academic program-the Science and Technology Center for the Synthesis, Growth and Analysis of Electronic Materials at the University of Texas at Austin View full abstract»

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  • Introduction of a surface charge analysis instrument into the microelectronic engineering curricula at the Rochester Institute of Technology

    Publication Year: 1995 , Page(s): 237 - 240
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    A SCA-2000 Surface Charge Analyzer has been loaned to the Microelectronic Engineering Department at RIT for use in undergraduate laboratories and research projects. To illustrate the process monitoring capability of the SCA, a designed experiment was performed to study the effects of variations in post-oxidation anneal and pull temperature on total oxide charge (Qox). The SCA measurements on the as grown oxide were compared to C-V results from capacitors fabricated on the same films. Although absolute values of Qox did not match, an overall correlation between the two sets of data was observed. It is hypothesized that the lower Qox values observed with C-V are the result of hydrogen passivation of Qit View full abstract»

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  • The effect of implant dose rates and two step anneals on p+ -n ultra-shallow junctions

    Publication Year: 1995 , Page(s): 108 - 112
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    Ultra-shallow junctions are obtained using low energy BF2 (5 keV) implants in crystalline Si. The variation in junction depth as a function of dose rate and two-step anneals is studied for doses of 1×1014 and 1×1015 cm-2 . B diffusion is retarded in the tail region for the higher dose rates and consequently the junction depth decreases as compared to the lower dose rates. Junction depth is further reduced for the two-step anneals as compared to the single-step RTA View full abstract»

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  • The influence of LOCOS related oxide etch backs on thin oxide leakage in memory devices

    Publication Year: 1995 , Page(s): 94 - 100
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    The influence of oxide etch backs done in LOCOS based isolation technologies on the low level leakage and reliability of tunnel oxide capacitors has been studied. Tunnel oxide structures are part of nonvolatile memory devices such as Flash EEPROMs and are critical to their overall performance. LOCOS isolated, area and edge intensive capacitors with 94 A tunnel oxide have been manufactured and tested. Test results indicate that the extent of the etch back and the use of HF instead of buffered HF as etch chemical do not adversely affect the low level leakage of the tunnel capacitors. However, oxide endurance analysis based on constant current charge to breakdown tests shows a significant degradation if an aggressive pretunnel oxide etch back strategy is adopted View full abstract»

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  • Software as a method of technology transfer

    Publication Year: 1995 , Page(s): 6 - 11
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    The CALCE Electronics Packaging Research Center (EPRC) located at the University of Maryland in College Park, Maryland uses software tools developed in-house to transfer technology to industry. Over the past seven years, the CALCE EPRC has developed and fielded various software tools which have aided industry in evaluating electronic packaging designs from a physics of failure standpoint. The software is used to model and assess Printed Wiring Assembly and microelectronic designs. Tools include thermal analysis, vibrational analysis, solder joint fatigue assessment and plated-through hole assessment. In the field, the CALCE software has enjoyed dual use by both government and industry consortium members. In this paper, we present lessons learned in the successful implementation of software as a technology transfer vehicle. To this end, several case studies of industrial usage are presented. The following examples are included. Honeywell has used CALCE software to perform thermal assessments of a new cooling technology which could not be performed with existing software tools. AlliedSignal has integrated CALCE software into their Integrated Product Design System. Texas Instruments has incorporated software tools developed by the CALCE EPRC into their internally used Computer Aided Reliability and Maintainability Applications (CARMA) tool suite. The U.S. Army has used the CALCE PWA software to compare commercial and ruggedized microelectronic assemblies View full abstract»

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  • Surface roughness studies of deep plasma etching in crystalline silicon

    Publication Year: 1995 , Page(s): 134 - 139
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    A study of the parameters influencing the roughness of plasma etched surfaces of monocrystalline silicon was conducted, using a commercial reactive ion etcher (RIE) and a Gaseous Electronic Conference (GEC) Plasma Standard Cell as the etching tools. Relatively deep (6 micrometer) etching was done using pure SF6 and mixtures of SF6 with additions of either oxygen or hydrogen. Other parameters studied included chamber pressure and rf power. Roughness was determined qualitatively by the use of a Scanning Electron Microscope (SEM). An Atomic Force Microscope (AFM) was used on selected samples to obtain quantitative roughness measurements. A wide range of surface roughness was observed. Both pure SF6 and SF6 plus 7.5% H2 mere capable of producing very smooth bottom and wall surfaces. Increasing H2 to 17.5% caused the sidewalls to become rough while maintaining bottom smoothness. Oxygen additions caused all surfaces to be rough. With most gas compositions, surfaces could be made smoother by decreasing power and increasing pressure. Silicon etch rates generally increased with power, but showed a maximum near a pressure of 400 mT, decreasing at both higher and lower pressures. Although similar trends were observed with both etch tools, further comparisons will require a more detailed investigation View full abstract»

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  • MDQ's role in highly integrated IC silicon solutions: a corporate culture transformation utilizing TQM methodology

    Publication Year: 1995 , Page(s): 45 - 51
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    Advanced Micro Devices (AMD) recognized that the outdated quality control culture was ineffective in the swift and efficient introduction of new products. Total Quality Management (TQM) was recognized as the necessary foundation of the company if it was to grow and flourish. An integral portion of TQM requires the direct involvement of the end customer, beginning with the design concept through to product satisfaction. From this foundation, TQM was adapted as Market Driven Quality (MDQ) to initiate the corporate culture transformation View full abstract»

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  • Motorola/Arizona State University-an experiment towards industrial/academic excellence

    Publication Year: 1995 , Page(s): 41 - 44
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    In August, Motorola and Arizona State University entered a partnering arrangement, new to both groups, in which Motorola placed a full time employee at ASU to co-direct a university research center, the Center for Solid State Electronics Research (CSSER). In this paper, the details of this two year `experiment' between ASU and Motorola are presented. After giving a brief introduction, the Center for Solid State Electronics Research is described. Responsibilities for the industrial co-director and metrics for success, both from ASU's perspective and from Motorola's perspective are then given. Specific examples of improved linkages and accomplishments are illustrated. Finally, observations for the first nine months are presented and some future directions are outlined View full abstract»

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  • World wide web based technology transfer testbed

    Publication Year: 1995 , Page(s): 16 - 20
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    We present here a distributed computational environment based on the world wide web designed to effect technology transfer between university and industry. The prototype is based on the integration of computational modules, scientific visualization tools, and a friendly WWW based user-interface. This prototype allows users with simple personal computer based web browsers (e.g. Mosaic browser) to gain access to research information and computational modules located on high-end computational platforms. This WWW based integration scheme opens new horizons for cooperation among researchers, engineers, scientists, students, and businesses View full abstract»

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  • An undergraduate laboratory in the design, fabrication and test of semiconductor processes and integrated circuits

    Publication Year: 1995 , Page(s): 31 - 35
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    In a semester-long integrated circuits fabrication laboratory at Northern Arizona University, senior electrical engineering students design a silicon process, design and lay out integrated circuits, fabricate wafers, and test working die. Breaking into small teams, students arrive at a preliminary process now using first order models, refine the process based on simulations, and carry out process verification on actual wafers. Concurrent with the process development, students design and lay out circuits according to rules they establish (lambda-based, with λ from 3 to 6 μm). Circuits include test devices, logic gates and oscillators, Students set up a process schedule and fabricate their integrated circuits in a clean room. Finally, they perform electrical test to extract parameters and verify circuit operation. Also discussed in this paper is the experience students gain in soft skills such as team work, time management, communication and presentation View full abstract»

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